#define APCI3120_RD_STATUS 0x02
#define APCI3120_RD_FIFO 0x00
-/* Enable external trigger bit in nWrAddress */
-#define APCI3120_ENABLE_EXT_TRIGGER 0x8000
-
/* ANALOG OUTPUT AND INPUT DEFINE */
#define APCI3120_UNIPOLAR 0x80
#define APCI3120_BIPOLAR 0x00
{
struct apci3120_private *devpriv = dev->private;
- devpriv->ctrl |= APCI3120_ENABLE_EXT_TRIGGER;
+ devpriv->ctrl |= APCI3120_CTRL_EXT_TRIG;
outw(devpriv->ctrl, dev->iobase + APCI3120_WR_ADDRESS);
return 0;
}
{
struct apci3120_private *devpriv = dev->private;
- devpriv->ctrl &= ~APCI3120_ENABLE_EXT_TRIGGER;
+ devpriv->ctrl &= ~APCI3120_CTRL_EXT_TRIG;
outw(devpriv->ctrl, dev->iobase + APCI3120_WR_ADDRESS);
return 0;
}
/*
* PCI BAR 1 register map (dev->iobase)
*/
+#define APCI3120_CTRL_EXT_TRIG (1 << 15)
#define APCI3120_CTRL_GATE(x) (1 << (12 + (x)))
#define APCI3120_CTRL_PR(x) (((x) & 0xf) << 8)
#define APCI3120_CTRL_PA(x) (((x) & 0xf) << 0)