};
};
+ gmac: eth@fe300000 {
+ compatible = "rockchip,rk3399-gmac";
+ reg = <0x0 0xfe300000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+ <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
+ <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
+ <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru SRST_A_GMAC>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
emmc_phy: phy {
compatible = "rockchip,rk3399-emmc-phy";
reg-offset = <0xf780>;
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins =
- <3 11 RK_FUNC_1 &pcfg_pull_none>,
- <3 13 RK_FUNC_1 &pcfg_pull_none>,
- <3 8 RK_FUNC_1 &pcfg_pull_none>,
- <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txclk */
<3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_rxclk */
+ <3 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
+ <3 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
<3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_clk */
+ <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <3 9 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <3 8 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
<3 7 RK_FUNC_1 &pcfg_pull_none>,
- <3 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_rxd3 */
<3 3 RK_FUNC_1 &pcfg_pull_none>,
- <3 14 RK_FUNC_1 &pcfg_pull_none>,
- <3 9 RK_FUNC_1 &pcfg_pull_none>;
+ /* mac_rxd2 */
+ <3 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd2 */
+ <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
};
rmii_pins: rmii-pins {
rockchip,pins =
- <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
<3 13 RK_FUNC_1 &pcfg_pull_none>,
- <3 8 RK_FUNC_1 &pcfg_pull_none>,
- <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txen */
<3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 6 RK_FUNC_1 &pcfg_pull_none>,
- <3 7 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_clk */
+ <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxer */
+ <3 10 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
<3 9 RK_FUNC_1 &pcfg_pull_none>,
- <3 10 RK_FUNC_1 &pcfg_pull_none>;
+ /* mac_mdc */
+ <3 8 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <3 7 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
};
};