Merge commit 'v3.2-rc6' into x86/platform

diff --combined arch/x86/Kconfig
index c3c9343e4498394c09ed666078ee461ed3ff1b4f,efb42949cc09349e37246baa07f018648186386f..07620bc913db779674524e6ac50dd4bf7eb79dab
--- 1/arch/x86/Kconfig
--- 2/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@@ -390,7 -390,7 +390,7 @@@ config X86_INTEL_C
          This option compiles in support for the CE4100 SOC for settop
          boxes and media devices.
  
- config X86_INTEL_MID
+ config X86_WANT_INTEL_MID
        bool "Intel MID platform support"
        depends on X86_32
        depends on X86_EXTENDED_PLATFORM
@@@ -399,7 -399,10 +399,10 @@@
          systems which do not have the PCI legacy interfaces (Moorestown,
          Medfield). If you are building for a PC class system say N here.
  
- if X86_INTEL_MID
+ if X86_WANT_INTEL_MID
+ 
+ config X86_INTEL_MID
+       bool
  
  config X86_MRST
         bool "Moorestown MID platform"
@@@ -411,6 -414,7 +414,7 @@@
        select SPI
        select INTEL_SCU_IPC
        select X86_PLATFORM_DEVICES
+       select X86_INTEL_MID
        ---help---
          Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin
          Internet Device(MID) platform. Moorestown consists of two chips:
@@@ -419,24 -423,6 +423,24 @@@
          nor standard legacy replacement devices/features. e.g. Moorestown does
          not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
  
 +config X86_MDFLD
 +       bool "Medfield MID platform"
 +      depends on PCI
 +      depends on PCI_GOANY
 +      depends on X86_IO_APIC
 +      select APB_TIMER
 +      select I2C
 +      select SPI
 +      select INTEL_SCU_IPC
 +      select X86_PLATFORM_DEVICES
 +      select X86_INTEL_MID
 +      ---help---
 +        Medfield is Intel's Low Power Intel Architecture (LPIA) based Moblin
 +        Internet Device(MID) platform. 
 +        Unlike standard x86 PCs, Medfield does not have many legacy devices
 +        nor standard legacy replacement devices/features. e.g. Medfield does
 +        not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
 +
  endif
  
  config X86_RDC321X
@@@ -634,7 -620,7 +638,7 @@@ config X86_SUMMIT_NUM
  
  config X86_CYCLONE_TIMER
        def_bool y
 -      depends on X86_32_NON_STANDARD
 +      depends on X86_SUMMIT
  
  source "arch/x86/Kconfig.cpu"
  
@@@ -662,10 -648,9 +666,10 @@@ config HPET_EMULATE_RT
        depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)
  
  config APB_TIMER
 -       def_bool y if MRST
 -       prompt "Langwell APB Timer Support" if X86_MRST
 +       def_bool y if X86_INTEL_MID
 +       prompt "Intel MID APB Timer Support" if X86_INTEL_MID
         select DW_APB_TIMER
 +       depends on X86_INTEL_MID && SFI
         help
           APB timer is the replacement for 8254, HPET on X86 MID platforms.
           The APBT provides a stable time base on SMP

diff --combined arch/x86/platform/mrst/mrst.c
index b6a33d2bd4d67f658d0cc9e0c96bb601f2688973,ad4ec1cb097ecfae17e4a99aed37cf985b03cb78..475e2cd0f3c3f5f10c668129f9ebd4a4e4754c0d
--- 1/arch/x86/platform/mrst/mrst.c
--- 2/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@@ -76,6 -76,20 +76,20 @@@ struct sfi_rtc_table_entry sfi_mrtc_arr
  EXPORT_SYMBOL_GPL(sfi_mrtc_array);
  int sfi_mrtc_num;
  
+ static void mrst_power_off(void)
+ {
+       if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
+               intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 1);
+ }
+ 
+ static void mrst_reboot(void)
+ {
+       if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
+               intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
+       else
+               intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
+ }
+ 
  /* parse all the mtimer info to a static mtimer array */
  static int __init sfi_parse_mtmr(struct sfi_table_header *table)
  {
@@@ -265,17 -279,6 +279,6 @@@ static int mrst_i8042_detect(void
        return 0;
  }
  
- /* Reboot and power off are handled by the SCU on a MID device */
- static void mrst_power_off(void)
- {
-       intel_scu_ipc_simple_command(0xf1, 1);
- }
- 
- static void mrst_reboot(void)
- {
-       intel_scu_ipc_simple_command(0xf1, 0);
- }
- 
  /*
   * Moorestown does not have external NMI source nor port 0x61 to report
   * NMI status. The possible NMI sources are from pmu as a result of NMI
@@@ -484,6 -487,46 +487,46 @@@ static void __init *max7315_platform_da
        return max7315;
  }
  
+ static void *tca6416_platform_data(void *info)
+ {
+       static struct pca953x_platform_data tca6416;
+       struct i2c_board_info *i2c_info = info;
+       int gpio_base, intr;
+       char base_pin_name[SFI_NAME_LEN + 1];
+       char intr_pin_name[SFI_NAME_LEN + 1];
+ 
+       strcpy(i2c_info->type, "tca6416");
+       strcpy(base_pin_name, "tca6416_base");
+       strcpy(intr_pin_name, "tca6416_int");
+ 
+       gpio_base = get_gpio_by_name(base_pin_name);
+       intr = get_gpio_by_name(intr_pin_name);
+ 
+       if (gpio_base == -1)
+               return NULL;
+       tca6416.gpio_base = gpio_base;
+       if (intr != -1) {
+               i2c_info->irq = intr + MRST_IRQ_OFFSET;
+               tca6416.irq_base = gpio_base + MRST_IRQ_OFFSET;
+       } else {
+               i2c_info->irq = -1;
+               tca6416.irq_base = -1;
+       }
+       return &tca6416;
+ }
+ 
+ static void *mpu3050_platform_data(void *info)
+ {
+       struct i2c_board_info *i2c_info = info;
+       int intr = get_gpio_by_name("mpu3050_int");
+ 
+       if (intr == -1)
+               return NULL;
+ 
+       i2c_info->irq = intr + MRST_IRQ_OFFSET;
+       return NULL;
+ }
+ 
  static void __init *emc1403_platform_data(void *info)
  {
        static short intr2nd_pdata;
@@@ -646,12 -689,15 +689,15 @@@ static void *msic_ocd_platform_data(voi
  static const struct devs_id __initconst device_ids[] = {
        {"bma023", SFI_DEV_TYPE_I2C, 1, &no_platform_data},
        {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
+       {"pmic_gpio", SFI_DEV_TYPE_IPC, 1, &pmic_gpio_platform_data},
        {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
        {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
        {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
+       {"tca6416", SFI_DEV_TYPE_I2C, 1, &tca6416_platform_data},
        {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
        {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
        {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
+       {"mpu3050", SFI_DEV_TYPE_I2C, 1, &mpu3050_platform_data},
  
        /* MSIC subdevices */
        {"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data},
@@@ -802,7 -848,8 +848,7 @@@ static void __init sfi_handle_ipc_dev(s
        if (mrst_has_msic())
                return;
  
 -      /* ID as IRQ is a hack that will go away */
 -      pdev = platform_device_alloc(entry->name, entry->irq);
 +      pdev = platform_device_alloc(entry->name, 0);
        if (pdev == NULL) {
                pr_err("out of memory for SFI platform device '%s'.\n",
                        entry->name);
@@@ -983,7 -1030,6 +1029,7 @@@ static int __init pb_keys_init(void
        num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
        for (i = 0; i < num; i++) {
                gb[i].gpio = get_gpio_by_name(gb[i].desc);
 +              pr_debug("info[%2d]: name = %s, gpio = %d\n", i, gb[i].desc, gb[i].gpio);
                if (gb[i].gpio == -1)
                        continue;