// Since the offset is too large for the load/store instruction
// get the reg+offset into a register.
if (needsLowering) {
- Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
- /*Op0IsKill*/false, Addr.Offset, MVT::i32);
+ ARMCC::CondCodes Pred = ARMCC::AL;
+ unsigned PredReg = 0;
+
+ TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
+ ARM::GPRRegisterClass;
+ unsigned BaseReg = createResultReg(RC);
+
+ if (!isThumb)
+ emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ BaseReg, Addr.Base.Reg, Addr.Offset,
+ Pred, PredReg,
+ static_cast<const ARMBaseInstrInfo&>(TII));
+ else {
+ assert(AFI->isThumb2Function());
+ emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ BaseReg, Addr.Base.Reg, Addr.Offset, Pred, PredReg,
+ static_cast<const ARMBaseInstrInfo&>(TII));
+ }
Addr.Offset = 0;
+ Addr.Base.Reg = BaseReg;
}
}
+++ /dev/null
-; RUN: llc -O0 -regalloc=linearscan < %s
-; This isn't exactly a useful set of command-line options, but check that it
-; doesn't crash. (It was crashing because a register was getting redefined.)
-
-target triple = "thumbv7-apple-macosx10.6.7"
-
-define i32 @f(i32* %x) nounwind ssp {
- %y = getelementptr inbounds i32* %x, i32 5000
- %tmp103 = load i32* %y, align 4
- ret i32 %tmp103
-}