Change latency of setuw and setsw to 2 cycles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@681 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9Instr.def b/lib/Target/SparcV9/SparcV9Instr.def
index e4fae4d7ef15ca692a334cc1e19f3133d2b59af0..13efaa33ae7704eb91deebb9546599a06c970736 100644 (file)
--- a/lib/Target/SparcV9/SparcV9Instr.def
+++ b/lib/Target/SparcV9/SparcV9Instr.def
@@ -38,16 +38,17 @@
 //                                             instr class flags (defined in MachineInstrInfo.h)
 
 
-I(NOP, "nop",          0,  -1,  0, false, 0,   1,  SPARC_NONE,  M_NOP_FLAG)
+I(NOP, "nop",          0,  -1,  0, false, 0,  1,  SPARC_NONE,  M_NOP_FLAG)
   
 // Synthetic SPARC assembly opcodes for setting a register to a constant.
 // Max immediate constant should be ignored for both these instructions.
-I(SETSW, "setsw",      2,   1,  0, true ,  0,  1,  SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG)
-I(SETUW, "setuw",      2,   1,  0, false, 0,  1,  SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG)
+// Use a latency > 1 since this may generate as many as 3 instructions.
+I(SETSW, "setsw",      2,   1,  0, true , 0,  2,  SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG)
+I(SETUW, "setuw",      2,   1,  0, false, 0,  2,  SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG)
 
 // Set high-order bits of register and clear low-order bits
 I(SETHI, "sethi",      2,  1, B22, false, 0,  1,  SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG)
-  
+
 // Add or add with carry.
 // Immed bit specifies if second operand is immediate(1) or register(0)
 I(ADD   , "add",       3,  2, B12, true , 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG)