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mtd: denali.h: fixed checkpatch errors
authorDong, Chuanxiao <chuanxiao.dong@intel.com>
Wed, 21 Jul 2010 17:32:26 +0000 (01:32 +0800)
committerDavid Woodhouse <David.Woodhouse@intel.com>
Mon, 2 Aug 2010 08:09:34 +0000 (09:09 +0100)
Fix all checkpatch.pl complaints.

Artem: tweaked a little and fix tab indentations, so now this is not
       only about checkpatch, but also about making indentations look
       sane.

Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
drivers/mtd/nand/denali.h patch | blob | history

diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index 422a29ab2f60f08f70d38d9e9e1e37a9b10ec0cd..b56fa3c7c1667b173f6199f7fb57c66fc62ffd4e 100644 (file)
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -17,7 +17,7 @@
  *
  */
 
-#include <linux/mtd/nand.h> 
+#include <linux/mtd/nand.h>
 
 #define DEVICE_RESET                           0x0
 #define     DEVICE_RESET__BANK0                                0x0001
@@ -29,7 +29,7 @@
 #define     TRANSFER_SPARE_REG__FLAG                   0x0001
 
 #define LOAD_WAIT_CNT                          0x20
-#define     LOAD_WAIT_CNT__VALUE                               0xffff
+#define     LOAD_WAIT_CNT__VALUE                       0xffff
 
 #define PROGRAM_WAIT_CNT                       0x30
 #define     PROGRAM_WAIT_CNT__VALUE                    0xffff
@@ -83,7 +83,7 @@
 #define RE_2_WE                                        0x120
 #define     RE_2_WE__VALUE                             0x003f
 
-#define ACC_CLKS                               0x130
+#define ACC_CLKS                               0x130
 #define     ACC_CLKS__VALUE                            0x000f
 
 #define NUMBER_OF_PLANES                       0x140
@@ -140,7 +140,7 @@
 #define DEVICES_CONNECTED                      0x250
 #define     DEVICES_CONNECTED__VALUE                   0x0007
 
-#define DIE_MASK                                       0x260
+#define DIE_MASK                               0x260
 #define     DIE_MASK__VALUE                            0x00ff
 
 #define FIRST_BLOCK_OF_NEXT_PLANE              0x270
@@ -152,7 +152,7 @@
 #define RE_2_RE                                        0x290
 #define     RE_2_RE__VALUE                             0x003f
 
-#define MANUFACTURER_ID                        0x300
+#define MANUFACTURER_ID                                0x300
 #define     MANUFACTURER_ID__VALUE                     0x00ff
 
 #define DEVICE_ID                              0x310
@@ -173,13 +173,13 @@
 #define LOGICAL_PAGE_SPARE_SIZE                        0x360
 #define     LOGICAL_PAGE_SPARE_SIZE__VALUE             0xffff
 
-#define REVISION                                       0x370
+#define REVISION                               0x370
 #define     REVISION__VALUE                            0xffff
 
 #define ONFI_DEVICE_FEATURES                   0x380
 #define     ONFI_DEVICE_FEATURES__VALUE                        0x003f
 
-#define ONFI_OPTIONAL_COMMANDS         0x390
+#define ONFI_OPTIONAL_COMMANDS                 0x390
 #define     ONFI_OPTIONAL_COMMANDS__VALUE              0x003f
 
 #define ONFI_TIMING_MODE                       0x3a0
@@ -201,12 +201,12 @@
 #define FEATURES                                       0x3f0
 #define     FEATURES__N_BANKS                          0x0003
 #define     FEATURES__ECC_MAX_ERR                      0x003c
-#define     FEATURES__DMA                                      0x0040
+#define     FEATURES__DMA                              0x0040
 #define     FEATURES__CMD_DMA                          0x0080
 #define     FEATURES__PARTITION                                0x0100
 #define     FEATURES__XDMA_SIDEBAND                    0x0200
 #define     FEATURES__GPREG                            0x0400
-#define     FEATURES__INDEX_ADDR                               0x0800
+#define     FEATURES__INDEX_ADDR                       0x0800
 
 #define TRANSFER_MODE                          0x400
 #define     TRANSFER_MODE__VALUE                       0x0003
@@ -235,12 +235,12 @@
 #define     INTR_EN0__DMA_CMD_COMP                     0x0004
 #define     INTR_EN0__TIME_OUT                         0x0008
 #define     INTR_EN0__PROGRAM_FAIL                     0x0010
-#define     INTR_EN0__ERASE_FAIL                               0x0020
+#define     INTR_EN0__ERASE_FAIL                       0x0020
 #define     INTR_EN0__LOAD_COMP                                0x0040
 #define     INTR_EN0__PROGRAM_COMP                     0x0080
-#define     INTR_EN0__ERASE_COMP                               0x0100
+#define     INTR_EN0__ERASE_COMP                       0x0100
 #define     INTR_EN0__PIPE_CPYBCK_CMD_COMP             0x0200
-#define     INTR_EN0__LOCKED_BLK                               0x0400
+#define     INTR_EN0__LOCKED_BLK                       0x0400
 #define     INTR_EN0__UNSUP_CMD                                0x0800
 #define     INTR_EN0__INT_ACT                          0x1000
 #define     INTR_EN0__RST_COMP                         0x2000
@@ -253,7 +253,7 @@
 #define ERR_PAGE_ADDR0                         0x440
 #define     ERR_PAGE_ADDR0__VALUE                      0xffff
 
-#define ERR_BLOCK_ADDR0                        0x450
+#define ERR_BLOCK_ADDR0                                0x450
 #define     ERR_BLOCK_ADDR0__VALUE                     0xffff
 
 #define INTR_STATUS1                           0x460
@@ -280,12 +280,12 @@
 #define     INTR_EN1__DMA_CMD_COMP                     0x0004
 #define     INTR_EN1__TIME_OUT                         0x0008
 #define     INTR_EN1__PROGRAM_FAIL                     0x0010
-#define     INTR_EN1__ERASE_FAIL                               0x0020
+#define     INTR_EN1__ERASE_FAIL                       0x0020
 #define     INTR_EN1__LOAD_COMP                                0x0040
 #define     INTR_EN1__PROGRAM_COMP                     0x0080
-#define     INTR_EN1__ERASE_COMP                               0x0100
+#define     INTR_EN1__ERASE_COMP                       0x0100
 #define     INTR_EN1__PIPE_CPYBCK_CMD_COMP             0x0200
-#define     INTR_EN1__LOCKED_BLK                               0x0400
+#define     INTR_EN1__LOCKED_BLK                       0x0400
 #define     INTR_EN1__UNSUP_CMD                                0x0800
 #define     INTR_EN1__INT_ACT                          0x1000
 #define     INTR_EN1__RST_COMP                         0x2000
@@ -298,7 +298,7 @@
 #define ERR_PAGE_ADDR1                         0x490
 #define     ERR_PAGE_ADDR1__VALUE                      0xffff
 
-#define ERR_BLOCK_ADDR1                        0x4a0
+#define ERR_BLOCK_ADDR1                                0x4a0
 #define     ERR_BLOCK_ADDR1__VALUE                     0xffff
 
 #define INTR_STATUS2                           0x4b0
@@ -325,12 +325,12 @@
 #define     INTR_EN2__DMA_CMD_COMP                     0x0004
 #define     INTR_EN2__TIME_OUT                         0x0008
 #define     INTR_EN2__PROGRAM_FAIL                     0x0010
-#define     INTR_EN2__ERASE_FAIL                               0x0020
+#define     INTR_EN2__ERASE_FAIL                       0x0020
 #define     INTR_EN2__LOAD_COMP                                0x0040
 #define     INTR_EN2__PROGRAM_COMP                     0x0080
-#define     INTR_EN2__ERASE_COMP                               0x0100
+#define     INTR_EN2__ERASE_COMP                       0x0100
 #define     INTR_EN2__PIPE_CPYBCK_CMD_COMP             0x0200
-#define     INTR_EN2__LOCKED_BLK                               0x0400
+#define     INTR_EN2__LOCKED_BLK                       0x0400
 #define     INTR_EN2__UNSUP_CMD                                0x0800
 #define     INTR_EN2__INT_ACT                          0x1000
 #define     INTR_EN2__RST_COMP                         0x2000
@@ -343,7 +343,7 @@
 #define ERR_PAGE_ADDR2                         0x4e0
 #define     ERR_PAGE_ADDR2__VALUE                      0xffff
 
-#define ERR_BLOCK_ADDR2                        0x4f0
+#define ERR_BLOCK_ADDR2                                0x4f0
 #define     ERR_BLOCK_ADDR2__VALUE                     0xffff
 
 #define INTR_STATUS3                           0x500
@@ -370,12 +370,12 @@
 #define     INTR_EN3__DMA_CMD_COMP                     0x0004
 #define     INTR_EN3__TIME_OUT                         0x0008
 #define     INTR_EN3__PROGRAM_FAIL                     0x0010
-#define     INTR_EN3__ERASE_FAIL                               0x0020
+#define     INTR_EN3__ERASE_FAIL                       0x0020
 #define     INTR_EN3__LOAD_COMP                                0x0040
 #define     INTR_EN3__PROGRAM_COMP                     0x0080
-#define     INTR_EN3__ERASE_COMP                               0x0100
+#define     INTR_EN3__ERASE_COMP                       0x0100
 #define     INTR_EN3__PIPE_CPYBCK_CMD_COMP             0x0200
-#define     INTR_EN3__LOCKED_BLK                               0x0400
+#define     INTR_EN3__LOCKED_BLK                       0x0400
 #define     INTR_EN3__UNSUP_CMD                                0x0800
 #define     INTR_EN3__INT_ACT                          0x1000
 #define     INTR_EN3__RST_COMP                         0x2000
@@ -388,7 +388,7 @@
 #define ERR_PAGE_ADDR3                         0x530
 #define     ERR_PAGE_ADDR3__VALUE                      0xffff
 
-#define ERR_BLOCK_ADDR3                        0x540
+#define ERR_BLOCK_ADDR3                                0x540
 #define     ERR_BLOCK_ADDR3__VALUE                     0xffff
 
 #define DATA_INTR                              0x550
@@ -412,9 +412,9 @@
 #define     GPREG_3__VALUE                             0xffff
 
 #define ECC_THRESHOLD                          0x600
-#define     ECC_THRESHOLD__VALUE                               0x03ff
+#define     ECC_THRESHOLD__VALUE                       0x03ff
 
-#define ECC_ERROR_BLOCK_ADDRESS                0x610
+#define ECC_ERROR_BLOCK_ADDRESS                        0x610
 #define     ECC_ERROR_BLOCK_ADDRESS__VALUE             0xffff
 
 #define ECC_ERROR_PAGE_ADDRESS                 0x620
@@ -466,7 +466,7 @@
 #define     CHNL_ACTIVE__CHANNEL3                      0x0008
 
 #define ACTIVE_SRC_ID                          0x800
-#define     ACTIVE_SRC_ID__VALUE                               0x00ff
+#define     ACTIVE_SRC_ID__VALUE                       0x00ff
 
 #define PTN_INTR                                       0x810
 #define     PTN_INTR__CONFIG_ERROR                     0x0001
@@ -485,7 +485,7 @@
 #define     PTN_INTR_EN__REG_ACCESS_ERROR              0x0020
 
 #define PERM_SRC_ID_0                          0x830
-#define     PERM_SRC_ID_0__SRCID                               0x00ff
+#define     PERM_SRC_ID_0__SRCID                       0x00ff
 #define     PERM_SRC_ID_0__DIRECT_ACCESS_ACTIVE                0x0800
 #define     PERM_SRC_ID_0__WRITE_ACTIVE                        0x2000
 #define     PERM_SRC_ID_0__READ_ACTIVE                 0x4000
@@ -502,7 +502,7 @@
 #define     MIN_MAX_BANK_0__MAX_VALUE                  0x000c
 
 #define PERM_SRC_ID_1                          0x870
-#define     PERM_SRC_ID_1__SRCID                               0x00ff
+#define     PERM_SRC_ID_1__SRCID                       0x00ff
 #define     PERM_SRC_ID_1__DIRECT_ACCESS_ACTIVE                0x0800
 #define     PERM_SRC_ID_1__WRITE_ACTIVE                        0x2000
 #define     PERM_SRC_ID_1__READ_ACTIVE                 0x4000
@@ -519,7 +519,7 @@
 #define     MIN_MAX_BANK_1__MAX_VALUE                  0x000c
 
 #define PERM_SRC_ID_2                          0x8b0
-#define     PERM_SRC_ID_2__SRCID                               0x00ff
+#define     PERM_SRC_ID_2__SRCID                       0x00ff
 #define     PERM_SRC_ID_2__DIRECT_ACCESS_ACTIVE                0x0800
 #define     PERM_SRC_ID_2__WRITE_ACTIVE                        0x2000
 #define     PERM_SRC_ID_2__READ_ACTIVE                 0x4000
@@ -536,7 +536,7 @@
 #define     MIN_MAX_BANK_2__MAX_VALUE                  0x000c
 
 #define PERM_SRC_ID_3                          0x8f0
-#define     PERM_SRC_ID_3__SRCID                               0x00ff
+#define     PERM_SRC_ID_3__SRCID                       0x00ff
 #define     PERM_SRC_ID_3__DIRECT_ACCESS_ACTIVE                0x0800
 #define     PERM_SRC_ID_3__WRITE_ACTIVE                        0x2000
 #define     PERM_SRC_ID_3__READ_ACTIVE                 0x4000
@@ -553,7 +553,7 @@
 #define     MIN_MAX_BANK_3__MAX_VALUE                  0x000c
 
 #define PERM_SRC_ID_4                          0x930
-#define     PERM_SRC_ID_4__SRCID                               0x00ff
+#define     PERM_SRC_ID_4__SRCID                       0x00ff
 #define     PERM_SRC_ID_4__DIRECT_ACCESS_ACTIVE                0x0800
 #define     PERM_SRC_ID_4__WRITE_ACTIVE                        0x2000
 #define     PERM_SRC_ID_4__READ_ACTIVE                 0x4000
@@ -570,7 +570,7 @@
 #define     MIN_MAX_BANK_4__MAX_VALUE                  0x000c
 
 #define PERM_SRC_ID_5                          0x970
-#define     PERM_SRC_ID_5__SRCID                               0x00ff
+#define     PERM_SRC_ID_5__SRCID                       0x00ff
 #define     PERM_SRC_ID_5__DIRECT_ACCESS_ACTIVE                0x0800
 #define     PERM_SRC_ID_5__WRITE_ACTIVE                        0x2000
 #define     PERM_SRC_ID_5__READ_ACTIVE                 0x4000
@@ -587,7 +587,7 @@
 #define     MIN_MAX_BANK_5__MAX_VALUE                  0x000c
 
 #define PERM_SRC_ID_6                          0x9b0
-#define     PERM_SRC_ID_6__SRCID                               0x00ff
+#define     PERM_SRC_ID_6__SRCID                       0x00ff
 #define     PERM_SRC_ID_6__DIRECT_ACCESS_ACTIVE                0x0800
 #define     PERM_SRC_ID_6__WRITE_ACTIVE                        0x2000
 #define     PERM_SRC_ID_6__READ_ACTIVE                 0x4000
@@ -604,7 +604,7 @@
 #define     MIN_MAX_BANK_6__MAX_VALUE                  0x000c
 
 #define PERM_SRC_ID_7                          0x9f0
-#define     PERM_SRC_ID_7__SRCID                               0x00ff
+#define     PERM_SRC_ID_7__SRCID                       0x00ff
 #define     PERM_SRC_ID_7__DIRECT_ACCESS_ACTIVE                0x0800
 #define     PERM_SRC_ID_7__WRITE_ACTIVE                        0x2000
 #define     PERM_SRC_ID_7__READ_ACTIVE                 0x4000
@@ -622,43 +622,40 @@
 
 /* flash.h */
 struct device_info_tag {
-        uint16_t wDeviceMaker;
-        uint16_t wDeviceID;
+       uint16_t wDeviceMaker;
+       uint16_t wDeviceID;
        uint8_t  bDeviceParam0;
        uint8_t  bDeviceParam1;
        uint8_t  bDeviceParam2;
-        uint32_t wDeviceType;
-        uint32_t wSpectraStartBlock;
-        uint32_t wSpectraEndBlock;
-        uint32_t wTotalBlocks;
-        uint16_t wPagesPerBlock;
-        uint16_t wPageSize;
-        uint16_t wPageDataSize;
-        uint16_t wPageSpareSize;
-        uint16_t wNumPageSpareFlag;
-        uint16_t wECCBytesPerSector;
-        uint32_t wBlockSize;
-        uint32_t wBlockDataSize;
-        uint32_t wDataBlockNum;
-        uint8_t bPlaneNum;
-        uint16_t wDeviceMainAreaSize;
-        uint16_t wDeviceSpareAreaSize;
-        uint16_t wDevicesConnected;
-        uint16_t wDeviceWidth;
-        uint16_t wHWRevision;
-        uint16_t wHWFeatures;
-
-        uint16_t wONFIDevFeatures;
-        uint16_t wONFIOptCommands;
-        uint16_t wONFITimingMode;
-        uint16_t wONFIPgmCacheTimingMode;
-
-        uint16_t MLCDevice;
-        uint16_t wSpareSkipBytes;
-
-        uint8_t nBitsInPageNumber;
-        uint8_t nBitsInPageDataSize;
-        uint8_t nBitsInBlockDataSize;
+       uint32_t wDeviceType;
+       uint32_t wSpectraStartBlock;
+       uint32_t wSpectraEndBlock;
+       uint32_t wTotalBlocks;
+       uint16_t wPagesPerBlock;
+       uint16_t wPageSize;
+       uint16_t wPageDataSize;
+       uint16_t wPageSpareSize;
+       uint16_t wNumPageSpareFlag;
+       uint16_t wECCBytesPerSector;
+       uint32_t wBlockSize;
+       uint32_t wBlockDataSize;
+       uint32_t wDataBlockNum;
+       uint8_t bPlaneNum;
+       uint16_t wDeviceMainAreaSize;
+       uint16_t wDeviceSpareAreaSize;
+       uint16_t wDevicesConnected;
+       uint16_t wDeviceWidth;
+       uint16_t wHWRevision;
+       uint16_t wHWFeatures;
+       uint16_t wONFIDevFeatures;
+       uint16_t wONFIOptCommands;
+       uint16_t wONFITimingMode;
+       uint16_t wONFIPgmCacheTimingMode;
+       uint16_t MLCDevice;
+       uint16_t wSpareSkipBytes;
+       uint8_t nBitsInPageNumber;
+       uint8_t nBitsInPageDataSize;
+       uint8_t nBitsInBlockDataSize;
 };
 
 /* ffsdefs.h */
@@ -684,11 +681,11 @@ struct device_info_tag {
 #define NAND_DBG_TRACE 3
 
 #ifdef VERBOSE
-#define nand_dbg_print(level, args...)                  \
-        do {                                            \
-                if (level <= nand_debug_level)          \
-                        printk(KERN_ALERT args);        \
-        } while (0)
+#define nand_dbg_print(level, args...)                         \
+       do {                                                    \
+                       if (level <= nand_debug_level)          \
+                               printk(KERN_ALERT args);        \
+       } while (0)
 #else
 #define nand_dbg_print(level, args...)
 #endif
@@ -772,10 +769,9 @@ struct device_info_tag {
 #define ECC_SECTOR_SIZE     512
 #define LLD_MAX_FLASH_BANKS     4
 
-#define DENALI_BUF_SIZE                NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE
+#define DENALI_BUF_SIZE                (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
 
-struct nand_buf
-{
+struct nand_buf {
        int head;
        int tail;
        uint8_t buf[DENALI_BUF_SIZE];
@@ -808,9 +804,9 @@ struct denali_nand_info {
        int idx;
 };
 
-static uint16_t  NAND_Flash_Reset(struct denali_nand_info *denali);
-static uint16_t  NAND_Read_Device_ID(struct denali_nand_info *denali);
-static void NAND_LLD_Enable_Disable_Interrupts(struct denali_nand_info *denali, uint16_t INT_ENABLE);
+static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali);
+static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali);
+static void NAND_LLD_Enable_Disable_Interrupts(struct denali_nand_info *denali,
+                                               uint16_t INT_ENABLE);
 
 #endif /*_LLD_NAND_*/
-
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