drm/i915: add TDL unit clock gating disable for VLV
authorJesse Barnes <jbarnes@virtuousgeek.org>
Thu, 14 Jun 2012 18:04:49 +0000 (11:04 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 18 Jun 2012 16:41:14 +0000 (18:41 +0200)
Another required workaround for a potential hang:
WaDisableTDLUnitClockGating.

v2: only apply this to VLV, IVB doesn't need it anymore (Eugeni)

References: https://bugs.freedesktop.org/show_bug.cgi?id=50245
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index e748f665a0d946a9dbd1f6f6b634fd790285681a..5d7cf5f7e750ad85879a80ff4e22c716691cc715 100644 (file)
 
 #define GEN6_UCGCTL2                           0x9404
 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE               (1 << 30)
+# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE               (1 << 22)
 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE               (1 << 13)
 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE              (1 << 12)
 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE               (1 << 11)
index 83c0e226f50cb7f533327fa103405577a52bba31..47c1a3e9b4af03f874880faa38d41cc4bb70341d 100644 (file)
@@ -3512,6 +3512,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
         */
        I915_WRITE(GEN6_UCGCTL2,
                   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
+                  GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
                   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
                   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
                   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);