Merge branch 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux into drm...
authorDave Airlie <airlied@redhat.com>
Tue, 2 Jul 2013 03:31:26 +0000 (13:31 +1000)
committerDave Airlie <airlied@redhat.com>
Tue, 2 Jul 2013 03:31:26 +0000 (13:31 +1000)
A few more patches for 3.11:
- add debugfs interface to check current DPM state
- Fix a bug that caused problems with DPM on BTC+ asics.

* 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/dpm: add debugfs support for SI
  drm/radeon/dpm: add debugfs support for cayman
  drm/radeon/dpm: add debugfs support for TN
  drm/radeon/dpm: add debugfs support for ON/LN
  drm/radeon/dpm: add debugfs support for 7xx/evergreen/btc
  drm/radeon/dpm: add debugfs support for rv6xx
  drm/radeon/dpm: add infrastructure to support debugfs info
  drm/radeon/dpm: re-enable state transitions for Cayman
  drm/radeon/dpm: re-enable state transitions for BTC
  drm/radeon: fix typo in radeon_atom_init_mc_reg_table()
  drm/radeon/atom: fix endian bug in radeon_atom_init_mc_reg_table()
  drm/radeon: remove sumo dpm/uvd bringup leftovers

15 files changed:
drivers/gpu/drm/radeon/btc_dpm.c
drivers/gpu/drm/radeon/ni_dpm.c
drivers/gpu/drm/radeon/nid.h
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_atombios.c
drivers/gpu/drm/radeon/radeon_pm.c
drivers/gpu/drm/radeon/rv6xx_dpm.c
drivers/gpu/drm/radeon/rv770_dpm.c
drivers/gpu/drm/radeon/rv770d.h
drivers/gpu/drm/radeon/si_dpm.c
drivers/gpu/drm/radeon/sid.h
drivers/gpu/drm/radeon/sumo_dpm.c
drivers/gpu/drm/radeon/trinity_dpm.c

index bab01858341746e40b228e8eca385c0353e60ee1..f072660c7665a6e1b653254527cf3075d9bfd112 100644 (file)
@@ -2326,14 +2326,11 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
                return ret;
        }
 
-#if 0
-       /* XXX */
        ret = rv770_unrestrict_performance_levels_after_switch(rdev);
        if (ret) {
                DRM_ERROR("rv770_unrestrict_performance_levels_after_switch failed\n");
                return ret;
        }
-#endif
 
        return 0;
 }
index 777d17e613120954ff34667d3d4d9203eb744dd1..8497ca6bb0b160cdd54d70d0faab2cc8b9f7480e 100644 (file)
@@ -1036,7 +1036,6 @@ static int ni_restrict_performance_levels_before_switch(struct radeon_device *rd
                0 : -EINVAL;
 }
 
-#if 0
 static int ni_unrestrict_performance_levels_after_switch(struct radeon_device *rdev)
 {
        if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
@@ -1045,7 +1044,6 @@ static int ni_unrestrict_performance_levels_after_switch(struct radeon_device *r
        return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) == PPSMC_Result_OK) ?
                0 : -EINVAL;
 }
-#endif
 
 static void ni_stop_smc(struct radeon_device *rdev)
 {
@@ -3832,14 +3830,11 @@ int ni_dpm_set_power_state(struct radeon_device *rdev)
                return ret;
        }
 
-#if 0
-       /* XXX */
        ret = ni_unrestrict_performance_levels_after_switch(rdev);
        if (ret) {
                DRM_ERROR("ni_unrestrict_performance_levels_after_switch failed\n");
                return ret;
        }
-#endif
 
        return 0;
 }
@@ -4292,6 +4287,26 @@ void ni_dpm_print_power_state(struct radeon_device *rdev,
        r600_dpm_print_ps_status(rdev, rps);
 }
 
+void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                   struct seq_file *m)
+{
+       struct radeon_ps *rps = rdev->pm.dpm.current_ps;
+       struct ni_ps *ps = ni_get_ps(rps);
+       struct rv7xx_pl *pl;
+       u32 current_index =
+               (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
+               CURRENT_STATE_INDEX_SHIFT;
+
+       if (current_index >= ps->performance_level_count) {
+               seq_printf(m, "invalid dpm profile %d\n", current_index);
+       } else {
+               pl = &ps->performance_levels[current_index];
+               seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+               seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
+                          current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
+       }
+}
+
 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)
 {
        struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
index 95693c77351d9074157e4f82c115293e1c6d4231..fe24a93542ecdb654c5a5597611ff76ff341ef00 100644 (file)
 #       define MRDCKD0_BYPASS                           (1 << 30)
 #       define MRDCKD1_BYPASS                           (1 << 31)
 
+#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x66c
+#       define CURRENT_STATE_INDEX_MASK                   (0xf << 4)
+#       define CURRENT_STATE_INDEX_SHIFT                  4
+
 #define CG_AT                                           0x6d4
 #       define CG_R(x)                                 ((x) << 0)
 #       define CG_R_MASK                               (0xffff << 0)
index 7e3fef4e6938c3122fc2552eaf64e3b2628cb3ec..f51807f04f65c6a0d8b63b7ceafb7f9eb0a36c29 100644 (file)
@@ -1667,6 +1667,7 @@ struct radeon_asic {
                u32 (*get_sclk)(struct radeon_device *rdev, bool low);
                u32 (*get_mclk)(struct radeon_device *rdev, bool low);
                void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
+               void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
        } dpm;
        /* pageflipping */
        struct {
@@ -2433,6 +2434,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
+#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
 
 /* Common functions */
 /* AGP */
index c3df589715a04b7ec1a4f091ecd4e35200d6331f..a5b244dc50cae53cff2d0f7b88e2e2f382ff6721 100644 (file)
@@ -1160,6 +1160,7 @@ static struct radeon_asic rv6xx_asic = {
                .get_sclk = &rv6xx_dpm_get_sclk,
                .get_mclk = &rv6xx_dpm_get_mclk,
                .print_power_state = &rv6xx_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &rs600_pre_page_flip,
@@ -1391,6 +1392,7 @@ static struct radeon_asic rv770_asic = {
                .get_sclk = &rv770_dpm_get_sclk,
                .get_mclk = &rv770_dpm_get_mclk,
                .print_power_state = &rv770_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &rs600_pre_page_flip,
@@ -1513,6 +1515,7 @@ static struct radeon_asic evergreen_asic = {
                .get_sclk = &rv770_dpm_get_sclk,
                .get_mclk = &rv770_dpm_get_mclk,
                .print_power_state = &rv770_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
@@ -1635,6 +1638,7 @@ static struct radeon_asic sumo_asic = {
                .get_sclk = &sumo_dpm_get_sclk,
                .get_mclk = &sumo_dpm_get_mclk,
                .print_power_state = &sumo_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
@@ -1757,6 +1761,7 @@ static struct radeon_asic btc_asic = {
                .get_sclk = &btc_dpm_get_sclk,
                .get_mclk = &btc_dpm_get_mclk,
                .print_power_state = &rv770_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
@@ -1931,6 +1936,7 @@ static struct radeon_asic cayman_asic = {
                .get_sclk = &ni_dpm_get_sclk,
                .get_mclk = &ni_dpm_get_mclk,
                .print_power_state = &ni_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
@@ -2103,6 +2109,7 @@ static struct radeon_asic trinity_asic = {
                .get_sclk = &trinity_dpm_get_sclk,
                .get_mclk = &trinity_dpm_get_mclk,
                .print_power_state = &trinity_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
@@ -2275,6 +2282,7 @@ static struct radeon_asic si_asic = {
                .get_sclk = &ni_dpm_get_sclk,
                .get_mclk = &ni_dpm_get_mclk,
                .print_power_state = &ni_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
index 2497d0a02de588a06f9bf81a51dd52bfe83fe6bc..6822c7aeacaadd3e37c12413d67f35981917d613 100644 (file)
@@ -416,6 +416,8 @@ u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
                                 struct radeon_ps *ps);
+void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                      struct seq_file *m);
 /* rs780 dpm */
 int rs780_dpm_init(struct radeon_device *rdev);
 int rs780_dpm_enable(struct radeon_device *rdev);
@@ -474,6 +476,8 @@ u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
 void rv770_dpm_print_power_state(struct radeon_device *rdev,
                                 struct radeon_ps *ps);
+void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                      struct seq_file *m);
 
 /*
  * evergreen
@@ -561,6 +565,8 @@ u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
 void sumo_dpm_print_power_state(struct radeon_device *rdev,
                                struct radeon_ps *ps);
+void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                     struct seq_file *m);
 
 /*
  * cayman
@@ -607,6 +613,8 @@ u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
 void ni_dpm_print_power_state(struct radeon_device *rdev,
                              struct radeon_ps *ps);
+void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                   struct seq_file *m);
 int trinity_dpm_init(struct radeon_device *rdev);
 int trinity_dpm_enable(struct radeon_device *rdev);
 void trinity_dpm_disable(struct radeon_device *rdev);
@@ -620,6 +628,8 @@ u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
 void trinity_dpm_print_power_state(struct radeon_device *rdev,
                                   struct radeon_ps *ps);
+void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                        struct seq_file *m);
 
 /* DCE6 - SI */
 void dce6_bandwidth_update(struct radeon_device *rdev);
@@ -667,6 +677,8 @@ int si_dpm_set_power_state(struct radeon_device *rdev);
 void si_dpm_post_set_power_state(struct radeon_device *rdev);
 void si_dpm_fini(struct radeon_device *rdev);
 void si_dpm_display_configuration_changed(struct radeon_device *rdev);
+void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                   struct seq_file *m);
 
 /* DCE8 - CIK */
 void dce8_bandwidth_update(struct radeon_device *rdev);
index a8296e0f8543b3957ae1ac346afabaf3f50f37d3..70d8687e60e0efb220528833e222dad64ae152ba 100644 (file)
@@ -3732,7 +3732,8 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
                                                        }
                                                        num_ranges++;
                                                }
-                                               reg_data += reg_block->usRegDataBlkSize;
+                                               reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
+                                                       ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
                                        }
                                        if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK)
                                                return -EINVAL;
index 9737baeb711dae5f83b017bb42cb423d7abec01f..075f2fa568976a173e60ab3684b946a2273c8b63 100644 (file)
@@ -1062,6 +1062,11 @@ static int radeon_pm_init_dpm(struct radeon_device *rdev)
                ret = device_create_file(rdev->dev, &dev_attr_power_method);
                if (ret)
                        DRM_ERROR("failed to create device file for power method\n");
+
+               if (radeon_debugfs_pm_init(rdev)) {
+                       DRM_ERROR("Failed to register debugfs file for dpm!\n");
+               }
+
                DRM_INFO("radeon: dpm initialized\n");
        }
 
@@ -1389,19 +1394,28 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
        struct drm_device *dev = node->minor->dev;
        struct radeon_device *rdev = dev->dev_private;
 
-       seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
-       /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
-       if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
-               seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
-       else
-               seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
-       seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
-       if (rdev->asic->pm.get_memory_clock)
-               seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
-       if (rdev->pm.current_vddc)
-               seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
-       if (rdev->asic->pm.get_pcie_lanes)
-               seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
+       if (rdev->pm.dpm_enabled) {
+               mutex_lock(&rdev->pm.mutex);
+               if (rdev->asic->dpm.debugfs_print_current_performance_level)
+                       radeon_dpm_debugfs_print_current_performance_level(rdev, m);
+               else
+                       seq_printf(m, "Unsupported\n");
+               mutex_unlock(&rdev->pm.mutex);
+       } else {
+               seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
+               /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
+               if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
+                       seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
+               else
+                       seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
+               seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
+               if (rdev->asic->pm.get_memory_clock)
+                       seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
+               if (rdev->pm.current_vddc)
+                       seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
+               if (rdev->asic->pm.get_pcie_lanes)
+                       seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
+       }
 
        return 0;
 }
index 0e8b7d9b954b52878f70fcb6c9d810fefb675d18..33705c5c83690a1e888bd31f6eb45905b2a9cdad 100644 (file)
@@ -2027,6 +2027,31 @@ void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
        r600_dpm_print_ps_status(rdev, rps);
 }
 
+void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                      struct seq_file *m)
+{
+       struct radeon_ps *rps = rdev->pm.dpm.current_ps;
+       struct rv6xx_ps *ps = rv6xx_get_ps(rps);
+       struct rv6xx_pl *pl;
+       u32 current_index =
+               (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
+               CURRENT_PROFILE_INDEX_SHIFT;
+
+       if (current_index > 2) {
+               seq_printf(m, "invalid dpm profile %d\n", current_index);
+       } else {
+               if (current_index == 0)
+                       pl = &ps->low;
+               else if (current_index == 1)
+                       pl = &ps->medium;
+               else /* current_index == 2 */
+                       pl = &ps->high;
+               seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+               seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u\n",
+                          current_index, pl->sclk, pl->mclk, pl->vddc);
+       }
+}
+
 void rv6xx_dpm_fini(struct radeon_device *rdev)
 {
        int i;
index 7f6fa6221234c60b3085933bddaedc74f38211db..2436b5c7e66ece198343c37ee628b90df25773c0 100644 (file)
@@ -2430,6 +2430,36 @@ void rv770_dpm_print_power_state(struct radeon_device *rdev,
        r600_dpm_print_ps_status(rdev, rps);
 }
 
+void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                      struct seq_file *m)
+{
+       struct radeon_ps *rps = rdev->pm.dpm.current_ps;
+       struct rv7xx_ps *ps = rv770_get_ps(rps);
+       struct rv7xx_pl *pl;
+       u32 current_index =
+               (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
+               CURRENT_PROFILE_INDEX_SHIFT;
+
+       if (current_index > 2) {
+               seq_printf(m, "invalid dpm profile %d\n", current_index);
+       } else {
+               if (current_index == 0)
+                       pl = &ps->low;
+               else if (current_index == 1)
+                       pl = &ps->medium;
+               else /* current_index == 2 */
+                       pl = &ps->high;
+               seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+               if (rdev->family >= CHIP_CEDAR) {
+                       seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
+                                  current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
+               } else {
+                       seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u\n",
+                                  current_index, pl->sclk, pl->mclk, pl->vddc);
+               }
+       }
+}
+
 void rv770_dpm_fini(struct radeon_device *rdev)
 {
        int i;
index 784eeaf315c3c5fc027638e17a553db519bc2744..6bef2b7d601b9f6ac9b336cafc3a705b65202f84 100644 (file)
 #       define MUX_TCLK_TO_XCLK                           (1 << 8)
 #       define XTALIN_DIVIDE                              (1 << 9)
 
+#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x66c
+#       define CURRENT_PROFILE_INDEX_MASK                 (0xf << 4)
+#       define CURRENT_PROFILE_INDEX_SHIFT                4
+
 #define S0_VID_LOWER_SMIO_CNTL                            0x678
 #define S1_VID_LOWER_SMIO_CNTL                            0x67c
 #define S2_VID_LOWER_SMIO_CNTL                            0x680
index 6918f070eb52e9912b399e87790350ef545a0a98..46e9fc56cee7826bdf4446cc184e54519ce242d8 100644 (file)
@@ -6385,3 +6385,22 @@ void si_dpm_fini(struct radeon_device *rdev)
        r600_free_extended_power_table(rdev);
 }
 
+void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                   struct seq_file *m)
+{
+       struct radeon_ps *rps = rdev->pm.dpm.current_ps;
+       struct ni_ps *ps = ni_get_ps(rps);
+       struct rv7xx_pl *pl;
+       u32 current_index =
+               (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
+               CURRENT_STATE_INDEX_SHIFT;
+
+       if (current_index >= ps->performance_level_count) {
+               seq_printf(m, "invalid dpm profile %d\n", current_index);
+       } else {
+               pl = &ps->performance_levels[current_index];
+               seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+               seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
+                          current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
+       }
+}
index 299d657d0168cdc5ede4396dee4fed1f5c45179d..12a20eb77d0c533b201b2bdb10beb5cc2adcd61c 100644 (file)
 #       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)
 #       define DYN_LIGHT_SLEEP_EN                         (1 << 14)
 
+#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x798
+#       define CURRENT_STATE_INDEX_MASK                   (0xf << 4)
+#       define CURRENT_STATE_INDEX_SHIFT                  4
+
 #define CG_FTV                                            0x7bc
 
 #define CG_FFCT_0                                         0x7c0
index dbad293bfed585ff15dcce5f561dbb9a4664ec82..68fefb916582aa729049e5f68c0639718fb563a5 100644 (file)
@@ -1133,22 +1133,6 @@ static void sumo_cleanup_asic(struct radeon_device *rdev)
        sumo_take_smu_control(rdev, false);
 }
 
-static void sumo_uvd_init(struct radeon_device *rdev)
-{
-       u32 tmp;
-
-       tmp = RREG32(CG_VCLK_CNTL);
-       tmp &= ~VCLK_DIR_CNTL_EN;
-       WREG32(CG_VCLK_CNTL, tmp);
-
-       tmp = RREG32(CG_DCLK_CNTL);
-       tmp &= ~DCLK_DIR_CNTL_EN;
-       WREG32(CG_DCLK_CNTL, tmp);
-
-       /* 100 Mhz */
-       radeon_set_uvd_clocks(rdev, 10000, 10000);
-}
-
 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
                                              int min_temp, int max_temp)
 {
@@ -1348,7 +1332,6 @@ void sumo_dpm_setup_asic(struct radeon_device *rdev)
        sumo_program_acpi_power_level(rdev);
        sumo_enable_acpi_pm(rdev);
        sumo_take_smu_control(rdev, true);
-       sumo_uvd_init(rdev);
 }
 
 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
@@ -1769,6 +1752,34 @@ void sumo_dpm_print_power_state(struct radeon_device *rdev,
        r600_dpm_print_ps_status(rdev, rps);
 }
 
+void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                     struct seq_file *m)
+{
+       struct sumo_power_info *pi = sumo_get_pi(rdev);
+       struct radeon_ps *rps = rdev->pm.dpm.current_ps;
+       struct sumo_ps *ps = sumo_get_ps(rps);
+       struct sumo_pl *pl;
+       u32 current_index =
+               (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
+               CURR_INDEX_SHIFT;
+
+       if (current_index == BOOST_DPM_LEVEL) {
+               pl = &pi->boost_pl;
+               seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+               seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
+                          current_index, pl->sclk,
+                          sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
+       } else if (current_index >= ps->num_levels) {
+               seq_printf(m, "invalid dpm profile %d\n", current_index);
+       } else {
+               pl = &ps->levels[current_index];
+               seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+               seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
+                          current_index, pl->sclk,
+                          sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
+       }
+}
+
 void sumo_dpm_fini(struct radeon_device *rdev)
 {
        int i;
index fce825e112fff1d9866a4915a605600c6453538e..502d9153c4d58bd3151aed993f56b950ba2bf061 100644 (file)
@@ -1855,6 +1855,27 @@ void trinity_dpm_print_power_state(struct radeon_device *rdev,
        r600_dpm_print_ps_status(rdev, rps);
 }
 
+void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                        struct seq_file *m)
+{
+       struct radeon_ps *rps = rdev->pm.dpm.current_ps;
+       struct trinity_ps *ps = trinity_get_ps(rps);
+       struct trinity_pl *pl;
+       u32 current_index =
+               (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>
+               CURRENT_STATE_SHIFT;
+
+       if (current_index >= ps->num_levels) {
+               seq_printf(m, "invalid dpm profile %d\n", current_index);
+       } else {
+               pl = &ps->levels[current_index];
+               seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+               seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
+                          current_index, pl->sclk,
+                          trinity_convert_voltage_index_to_value(rdev, pl->vddc_index));
+       }
+}
+
 void trinity_dpm_fini(struct radeon_device *rdev)
 {
        int i;