iomux_set(GPIO0_C0);
gpio_set_value(RK30_PIN1_PA4,0);
gpio_set_value(RK30_PIN1_PA5,0);
- gpio_set_value(RK30_PIN1_PA6,0); //Vincent_Liu@asus.com for clk 24M
+ gpio_set_value(RK30_PIN1_PA6,0); // for clk 24M
gpio_set_value(RK30_PIN1_PA7,0);
gpio_set_value(RK30_PIN3_PB6,0);
gpio_set_value(RK30_PIN3_PB7,0);
iomux_set(GPIO0_C0);
gpio_set_value(RK30_PIN1_PA4,0);
gpio_set_value(RK30_PIN1_PA5,0);
- gpio_set_value(RK30_PIN1_PA6,0); //Vincent_Liu@asus.com for clk 24M
+ gpio_set_value(RK30_PIN1_PA6,0); // for clk 24M
gpio_set_value(RK30_PIN1_PA7,0);
gpio_set_value(RK30_PIN3_PB6,0);
gpio_set_value(RK30_PIN3_PB7,0);
//msleep(500);
}else{
//power ON
- gpio_set_value(RK30_PIN1_PA6,1); //Vincent_Liu@asus.com for clk 24M
+ gpio_set_value(RK30_PIN1_PA6,1); // for clk 24M
if(icl->power)
icl->power(icd->pdev,1);
icatch_sensor_power_ctr(icd,0,0);
icatch_sensor_power_ctr(icd,1,0);
- gpio_set_value(RK30_PIN1_PA6,0); //Vincent_Liu@asus.com for clk 24M
+ gpio_set_value(RK30_PIN1_PA6,0); // for clk 24M
#endif
}
// msleep(100);
}
ret = soc_camera_bus_param_compatible(camera_flags, bus_flags) ;
- /*nelson_yang@asus.com fix: rock-chip coding bug*/
/* rockchip BUGBUG
if (ret < 0)
dev_warn(icd->dev.parent,
else{
ret = 0;
}
- /*nelson_yang@asus.com fix: rock-chip coding bug end*/
return ret;
}
#define V4L2_CID_FOCUSZONE (V4L2_CID_CAMERA_CLASS_BASE_ROCK+5)
#define V4L2_CID_FACEDETECT (V4L2_CID_CAMERA_CLASS_BASE_ROCK+6)
#define V4L2_CID_HDR (V4L2_CID_CAMERA_CLASS_BASE_ROCK+7)
-
-/* nelson_yang@asus.com : Add ioctrl - V4L2_CID_ISO for camera ISO control */
-#define V4L2_CID_CAMERA_CLASS_BASE_ASUS (V4L2_CID_CAMERA_CLASS_BASE + 50)
-#define V4L2_CID_ISO (V4L2_CID_CAMERA_CLASS_BASE_ASUS + 1)
-#define V4L2_CID_ANTIBANDING (V4L2_CID_CAMERA_CLASS_BASE_ASUS + 2)
-#define V4L2_CID_WHITEBALANCE_LOCK (V4L2_CID_CAMERA_CLASS_BASE_ASUS + 3)
-#define V4L2_CID_EXPOSURE_LOCK (V4L2_CID_CAMERA_CLASS_BASE_ASUS + 4)
-#define V4L2_CID_METERING_AREAS (V4L2_CID_CAMERA_CLASS_BASE_ASUS + 5)
-#define V4L2_CID_WDR (V4L2_CID_CAMERA_CLASS_BASE_ASUS + 6)
-#define V4L2_CID_EDGE (V4L2_CID_CAMERA_CLASS_BASE_ASUS + 7)
-#define V4L2_CID_JPEG_EXIF (V4L2_CID_CAMERA_CLASS_BASE_ASUS + 8)
+#define V4L2_CID_ISO (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 8)
+#define V4L2_CID_ANTIBANDING (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 9)
+#define V4L2_CID_WHITEBALANCE_LOCK (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 10)
+#define V4L2_CID_EXPOSURE_LOCK (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 11)
+#define V4L2_CID_METERING_AREAS (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 12)
+#define V4L2_CID_WDR (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 13)
+#define V4L2_CID_EDGE (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 14)
+#define V4L2_CID_JPEG_EXIF (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 15)
/* FM Modulator class control IDs */
#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900)