arm64: dts: rockchip: add reset control registers for rk3399 dp driver.

Change-Id: Ibbad2bd5ab49c71385045ca743740cbba8ed6bf0
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
index 06393a2f4000e59d16c8ce7a70c089ca543068b0..83ed035d4b4111cc1b32d8be99c8acffea6b6115 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
@@ -167,14 +167,15 @@
                reg = <0x0 0xfec00000 0x0 0x100000>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
-                        <&cru SCLK_SPDIF_REC_DPTX>;
-               clock-names = "core-clk", "pclk", "spdif";
+                        <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+               clock-names = "core-clk", "pclk", "spdif", "grf";
                assigned-clocks = <&cru SCLK_DP_CORE>;
                assigned-clock-rates = <100000000>;
                power-domains = <&power RK3399_PD_HDCP>;
                phys = <&tcphy0_dp>, <&tcphy1_dp>;
-               resets = <&cru SRST_DPTX_SPDIF_REC>;
-               reset-names = "spdif";
+               resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+                        <&cru SRST_P_UPHY0_APB>;
+               reset-names = "spdif", "dptx", "apb";
                rockchip,grf = <&grf>;
                #address-cells = <1>;
                #size-cells = <0>;