return false;
bool SrcIsKill = hasTrivialKill(Op);
- // If we're truncating from i64/i32 to a smaller non-legal type then generate
- // an AND.
- uint64_t Mask = 0;
- switch (DestVT.SimpleTy) {
- default:
- // Trunc i64 to i32 is handled by the target-independent fast-isel.
- return false;
- case MVT::i1:
- Mask = 0x1;
- break;
- case MVT::i8:
- Mask = 0xff;
- break;
- case MVT::i16:
- Mask = 0xffff;
- break;
- }
+ // If we're truncating from i64 to a smaller non-legal type then generate an
+ // AND. Otherwise, we know the high bits are undefined and a truncate only
+ // generate a COPY. We cannot mark the source register also as result
+ // register, because this can incorrectly transfer the kill flag onto the
+ // source register.
+ unsigned ResultReg;
if (SrcVT == MVT::i64) {
+ uint64_t Mask = 0;
+ switch (DestVT.SimpleTy) {
+ default:
+ // Trunc i64 to i32 is handled by the target-independent fast-isel.
+ return false;
+ case MVT::i1:
+ Mask = 0x1;
+ break;
+ case MVT::i8:
+ Mask = 0xff;
+ break;
+ case MVT::i16:
+ Mask = 0xffff;
+ break;
+ }
// Issue an extract_subreg to get the lower 32-bits.
- SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
- AArch64::sub_32);
- SrcIsKill = true;
+ unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
+ AArch64::sub_32);
+ // Create the AND instruction which performs the actual truncation.
+ ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
+ assert(ResultReg && "Unexpected AND instruction emission failure.");
+ } else {
+ ResultReg = createResultReg(&AArch64::GPR32RegClass);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(SrcReg, getKillRegState(SrcIsKill));
}
- // Create the AND instruction which performs the actual truncation.
- unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, SrcIsKill, Mask);
- assert(ResultReg && "Unexpected AND instruction emission failure.");
-
updateValueMap(I, ResultReg);
return true;
}
define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i32
-; CHECK: mov [[REG:x[0-9]+]], x0
-; CHECK-NEXT: mov x0, [[REG]]
+; CHECK: mov x1, x0
%conv = trunc i64 %a to i32
ret i32 %conv
}
define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i16
-; CHECK: mov x[[REG:[0-9]+]], x0
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
-; CHECK-NEXT: uxth w0, [[REG2]]
+; CHECK: mov x[[REG:[0-9]+]], x0
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
+; CHECK: uxth w0, [[REG2]]
%conv = trunc i64 %a to i16
ret i16 %conv
}
define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i8
-; CHECK: mov x[[REG:[0-9]+]], x0
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xff
-; CHECK-NEXT: uxtb w0, [[REG2]]
+; CHECK: mov x[[REG:[0-9]+]], x0
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
+; CHECK: uxtb w0, [[REG2]]
%conv = trunc i64 %a to i8
ret i8 %conv
}
define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i1
-; CHECK: mov x[[REG:[0-9]+]], x0
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0x1
-; CHECK-NEXT: and w0, [[REG2]], #0x1
+; CHECK: mov x[[REG:[0-9]+]], x0
+; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
+; CHECK: and w0, [[REG2]], #0x1
%conv = trunc i64 %a to i1
ret i1 %conv
}
-define zeroext i16 @i32_trunc_i16(i32 %a) nounwind ssp {
-entry:
-; CHECK-LABEL: i32_trunc_i16
-; CHECK: and [[REG:w[0-9]+]], w0, #0xffff
-; CHECK-NEXT: uxth w0, [[REG]]
- %conv = trunc i32 %a to i16
- ret i16 %conv
-}
-
-define zeroext i8 @i32_trunc_i8(i32 %a) nounwind ssp {
-entry:
-; CHECK-LABEL: i32_trunc_i8
-; CHECK: and [[REG:w[0-9]+]], w0, #0xff
-; CHECK-NEXT: uxtb w0, [[REG]]
- %conv = trunc i32 %a to i8
- ret i8 %conv
-}
-
-define zeroext i1 @i32_trunc_i1(i32 %a) nounwind ssp {
-entry:
-; CHECK-LABEL: i32_trunc_i1
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1
-; CHECK-NEXT: and w0, [[REG]], #0x1
- %conv = trunc i32 %a to i1
- ret i1 %conv
-}
-
-define zeroext i8 @i16_trunc_i8(i16 zeroext %a) nounwind ssp {
-entry:
-; CHECK-LABEL: i16_trunc_i8
-; CHECK: and [[REG:w[0-9]+]], w0, #0xff
-; CHECK-NEXT: uxtb w0, [[REG]]
- %conv = trunc i16 %a to i8
- ret i8 %conv
-}
-
-define zeroext i1 @i16_trunc_i1(i16 zeroext %a) nounwind ssp {
-entry:
-; CHECK-LABEL: i16_trunc_i1
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1
-; CHECK-NEXT: and w0, [[REG]], #0x1
- %conv = trunc i16 %a to i1
- ret i1 %conv
-}
-
-define zeroext i1 @i8_trunc_i1(i8 zeroext %a) nounwind ssp {
-entry:
-; CHECK-LABEL: i8_trunc_i1
-; CHECK: and [[REG:w[0-9]+]], w0, #0x1
-; CHECK-NEXT: and w0, [[REG]], #0x1
- %conv = trunc i8 %a to i1
- ret i1 %conv
-}
-
; rdar://15101939
define void @stack_trunc() nounwind {
; CHECK-LABEL: stack_trunc