Make sub- super- reg-class tables static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29190 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 1799ac49e3c58e151a939272b11a9a8ce5e5fb14..8ed9eefef1fcce1bc73dd7cb056b912aec33e32e 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -127,7 +127,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
     std::string Name = RC.TheDef->getName();
   
     // Emit the register list now.
-    OS << "  // " << Name << " Register Class...\n  const unsigned " << Name
+    OS << "  // " << Name << " Register Class...\n"
+       << "  static const unsigned " << Name
        << "[] = {\n    ";
     for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
       Record *Reg = RC.Elements[i];
@@ -180,7 +181,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
       }
 
       OS << "  // " << Name 
-         << " Register Class sub-classes...\n  const TargetRegisterClass* "
+         << " Register Class sub-classes...\n"
+         << "  static const TargetRegisterClass* "
          << Name << "Subclasses [] = {\n    ";
 
       bool Empty = true;
@@ -214,7 +216,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
       std::string Name = RC.TheDef->getName();
 
       OS << "  // " << Name 
-         << " Register Class super-classes...\n  const TargetRegisterClass* "
+         << " Register Class super-classes...\n"
+         << "  static const TargetRegisterClass* "
          << Name << "Superclasses [] = {\n    ";
 
       bool Empty = true;