Fix PR14212: For some strange reason I treated vectors differently from

integers in that the code to handle split alloca-wide integer loads or
stores doesn't come first. It should, for the same reasons as with
integers, and the PR attests to that. Also had to fix a busted assert in
that this test case also covers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167051 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Transforms/Scalar/SROA.cpp b/lib/Transforms/Scalar/SROA.cpp
index af3a880cb90250599f58efcd7ffc8d21c7e8ef11..1d0ba1c2c161e007e7be83f2705436ea557a5fe1 100644 (file)
--- a/lib/Transforms/Scalar/SROA.cpp
+++ b/lib/Transforms/Scalar/SROA.cpp
@@ -2490,9 +2490,6 @@ private:
     assert(OldOp == OldPtr);
     IRBuilder<> IRB(&LI);
 
-    if (VecTy)
-      return rewriteVectorizedLoadInst(IRB, LI, OldOp);
-
     uint64_t Size = EndOffset - BeginOffset;
     if (Size < TD.getTypeStoreSize(LI.getType())) {
       assert(!LI.isVolatile());
@@ -2502,7 +2499,7 @@ private:
              TD.getTypeStoreSizeInBits(LI.getType()) &&
              "Non-byte-multiple bit width");
       assert(LI.getType()->getIntegerBitWidth() ==
-             TD.getTypeSizeInBits(OldAI.getAllocatedType()) &&
+             TD.getTypeAllocSizeInBits(OldAI.getAllocatedType()) &&
              "Only alloca-wide loads can be split and recomposed");
       IntegerType *NarrowTy = Type::getIntNTy(LI.getContext(), Size * 8);
       bool IsConvertable = (BeginOffset - NewAllocaBeginOffset == 0) &&
@@ -2536,6 +2533,8 @@ private:
       return IsConvertable;
     }
 
+    if (VecTy)
+      return rewriteVectorizedLoadInst(IRB, LI, OldOp);
     if (IntTy && LI.getType()->isIntegerTy())
       return rewriteIntegerLoad(IRB, LI);
 

diff --git a/test/Transforms/SROA/vector-promotion.ll b/test/Transforms/SROA/vector-promotion.ll
index 92051c62a7c6d24c4b09f292c7293a85f33e6a4a..02e084bf1129bb0403677c4596cee130a8683fa4 100644 (file)
--- a/test/Transforms/SROA/vector-promotion.ll
+++ b/test/Transforms/SROA/vector-promotion.ll
@@ -205,3 +205,18 @@ define i64 @test6(<4 x i64> %x, <4 x i64> %y, i64 %n) {
   %res = load i64* %addr, align 4
   ret i64 %res
 }
+
+define i32 @PR14212() {
+; CHECK: @PR14212
+; This caused a crash when "splitting" the load of the i32 in order to promote
+; the store of <3 x i8> properly. Heavily reduced from an OpenCL test case.
+entry:
+  %retval = alloca <3 x i8>, align 4
+; CHECK-NOT: alloca
+
+  store <3 x i8> undef, <3 x i8>* %retval, align 4
+  %cast = bitcast <3 x i8>* %retval to i32*
+  %load = load i32* %cast, align 4
+  ret i32 %load
+; CHECK: ret i32
+}