Tweak ADDrr fix. Bad check for explicit .w

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index c1a745216e83f9e1947387068307f54cc1308a85..07679a60ffdfd67d151777969027f92fcc75931b 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5245,8 +5245,8 @@ processInstruction(MCInst &Inst,
     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
         Inst.getOperand(5).getReg() != 0 ||
-        (static_cast<ARMOperand*>(Operands[2])->isToken() &&
-         static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
+        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
+         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
       break;
     MCInst TmpInst;
     TmpInst.setOpcode(ARM::tADDhirr);

diff --git a/test/MC/ARM/mode-switch.s b/test/MC/ARM/mode-switch.s
index 99bd4b531081e312f8a0e76f031a4fe3646a9ba7..9d4995439e82a1336505ec90944f50ba01fea304 100644 (file)
--- a/test/MC/ARM/mode-switch.s
+++ b/test/MC/ARM/mode-switch.s
@@ -4,7 +4,7 @@
 
 .code 16
        add.w   r0, r0, r1
-@ CHECK: add  r0, r1                  @ encoding: [0x08,0x44]
+@ CHECK: add.w r0, r0, r1              @ encoding: [0x00,0xeb,0x01,0x00]
 
 .code 32
        add     r0, r0, r1