#include <linux/io.h>\r
#include <linux/hrtimer.h>\r
\r
+#if 1\r
#define DVFS_DBG(fmt, args...) {while(0);}\r
-#define DVFS_ERR(fmt, args...) printk("DVFS ERR:\t"fmt, ##args)\r
-#define DVFS_LOG(fmt, args...) printk("DVFS LOG:\t"fmt, ##args)\r
+#else\r
+#define DVFS_DBG(fmt, args...) printk(KERN_DEBUG "DVFS DBG:\t"fmt, ##args)\r
+#endif\r
+#define DVFS_ERR(fmt, args...) printk(KERN_ERR "DVFS ERR:\t"fmt, ##args)\r
+#define DVFS_LOG(fmt, args...) printk(KERN_DEBUG "DVFS LOG:\t"fmt, ##args)\r
\r
#define dvfs_regulator_get(dev,id) regulator_get((dev),(id))\r
#define dvfs_regulator_put(regu) regulator_put((regu))\r
#define DVFS_V (1000*1000)\r
#define DVFS_MV (1000)\r
\r
-\r
static LIST_HEAD(rk_dvfs_tree);\r
static DEFINE_MUTEX(mutex);\r
static DEFINE_MUTEX(rk_dvfs_mutex);\r
#define PD_ON 1\r
#define PD_OFF 0\r
\r
+#define get_volt_up_delay(new_volt, old_volt) \\r
+ ((new_volt) > (old_volt) ? (((new_volt) - (old_volt)) >> 9) : 0)\r
+\r
int dvfs_regulator_set_voltage_readback(struct regulator *regulator, int min_uV, int max_uV)\r
{\r
int ret = 0, read_back = 0;\r
- int retry = 3;\r
ret = dvfs_regulator_set_voltage(regulator, max_uV, max_uV);\r
if (ret < 0) {\r
- while (ret != 0 && retry > 0) {\r
- DVFS_ERR("%s retrying...left %d times! regu=%p, volt=%d\n", __func__, retry, regulator, max_uV);\r
- mdelay(1);\r
- ret = dvfs_regulator_set_voltage(regulator, max_uV, max_uV);\r
- if (ret == 0)\r
- return ret;\r
- retry--;\r
- }\r
DVFS_ERR("%s now read back to check voltage\n", __func__);\r
\r
/* read back to judge if it is already effect */\r
\r
int clk_enable_dvfs(struct clk *clk)\r
{\r
- struct regulator *regulator;\r
struct clk_node *dvfs_clk;\r
struct cpufreq_frequency_table clk_fv;\r
if (!clk) {\r
}\r
if (dvfs_clk->enable_dvfs == 0) {\r
\r
- if (!dvfs_clk->vd->regulator) {\r
- regulator = NULL;\r
+ if (IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
+ //regulator = NULL;\r
if (dvfs_clk->vd->regulator_name)\r
- regulator = dvfs_regulator_get(NULL, dvfs_clk->vd->regulator_name);\r
- if (!IS_ERR(regulator)) {\r
+ dvfs_clk->vd->regulator = dvfs_regulator_get(NULL, dvfs_clk->vd->regulator_name);\r
+ if (!IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
// DVFS_DBG("dvfs_regulator_get(%s)\n",dvfs_clk->vd->regulator_name);\r
- dvfs_clk->vd->regulator = regulator;\r
dvfs_clk->vd->cur_volt = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
} else {\r
- dvfs_clk->vd->regulator = NULL;\r
+ //dvfs_clk->vd->regulator = NULL;\r
dvfs_clk->enable_dvfs = 0;\r
DVFS_ERR("%s can't get regulator in %s\n", dvfs_clk->name, __func__);\r
return -1;\r
}\r
} else {\r
- if (!IS_ERR(dvfs_clk->vd->regulator))\r
- dvfs_clk->vd->cur_volt = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
- else {\r
- DVFS_ERR("%s regulator not NULL but error\n", __func__);\r
- return -1;\r
- }\r
+ dvfs_clk->vd->cur_volt = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
// DVFS_DBG("%s(%s) vd volt=%u\n",__func__,dvfs_clk->name,dvfs_clk->vd->cur_volt);\r
}\r
\r
mutex_unlock(&mutex);\r
return 0;\r
}\r
-\r
-#define get_volt_up_delay(new_volt, old_volt) \\r
- ((new_volt) > (old_volt) ? (((new_volt) - (old_volt)) >> 10) : 0)\r
-\r
+#if 0\r
static int dvfs_set_depend_pre(struct clk_node *dvfs_clk, unsigned long rate_old, unsigned long rate_new)\r
{\r
struct depend_list *depend;\r
\r
depend->dep_vd->regulator = regulator;\r
}\r
- if (IS_ERR(depend->dep_vd->regulator)) {\r
+ if (IS_ERR_OR_NULL(depend->dep_vd->regulator)) {\r
DVFS_ERR("%s vd's(%s) regulator not NULL but error\n", __func__, depend->dep_vd->name);\r
return -1;\r
}\r
\r
depend->dep_vd->regulator = regulator;\r
}\r
- if (IS_ERR(depend->dep_vd->regulator)) {\r
+ if (IS_ERR_OR_NULL(depend->dep_vd->regulator)) {\r
DVFS_ERR("%s vd's(%s) regulator not NULL but error\n", __func__, depend->dep_vd->name);\r
return -1;\r
}\r
\r
return 0;\r
}\r
+#endif\r
+#define DVFS_SET_VOLT_FAILURE 1\r
+#define DVFS_SET_VOLT_SUCCESS 0\r
+#define ARM_HIGHER_LOGIC (150 * 1000)\r
+#define LOGIC_HIGHER_ARM (100 * 1000)\r
\r
-static int flag_core_set_volt_err = 0;\r
-int dvfs_target_core(struct clk *clk, unsigned long rate_hz)\r
+int check_volt_correct(int volt_old, int *volt_new, int volt_dep_old, int *volt_dep_new, \r
+ int clk_biger_than_dep, int dep_biger_than_clk)\r
{\r
- struct clk_node *dvfs_clk;\r
- unsigned int volt_new = 0, volt_old = 0, volt_clk_old = 0;\r
- struct cpufreq_frequency_table clk_fv = {0, 0};\r
- int ret = 0;\r
- int flag_set_volt_correct = 0;\r
- unsigned long rate_new, rate_old;\r
-\r
- if (!clk) {\r
- DVFS_ERR("%s is not clk\n", __func__);\r
- return -1;\r
- }\r
- dvfs_clk = clk_get_dvfs_info(clk);\r
-\r
- if (!dvfs_clk || dvfs_clk->vd->regulator == NULL) {\r
- DVFS_ERR("%s can't get dvfs regulater\n", clk->name);\r
+ int up_boundary = 0, low_boundary = 0;\r
+ DVFS_DBG("%d %d\n", clk_biger_than_dep, dep_biger_than_clk);\r
+ up_boundary = volt_old + dep_biger_than_clk;\r
+ low_boundary = volt_old - clk_biger_than_dep;\r
+ \r
+ if (volt_dep_old < low_boundary || volt_dep_old > up_boundary) {\r
+ DVFS_ERR("%s current volt out of bondary volt=%d(old=%d), volt_dep=%d(dep_old=%d), up_bnd=%d(dn=%d)\n",\r
+ __func__, *volt_new, volt_old, *volt_dep_new, volt_dep_old, up_boundary, low_boundary);\r
return -1;\r
}\r
\r
- /* Check limit rate */\r
- if (dvfs_clk->freq_limit_en) {\r
- if (rate_hz < dvfs_clk->min_rate) {\r
- rate_hz = dvfs_clk->min_rate;\r
- } else if (rate_hz > dvfs_clk->max_rate) {\r
- rate_hz = dvfs_clk->max_rate;\r
- }\r
- }\r
+ up_boundary = *volt_new + dep_biger_than_clk;\r
+ low_boundary = *volt_new - clk_biger_than_dep;\r
\r
- rate_new = rate_hz;\r
- rate_old = clk_get_rate(clk);\r
- if(!is_suport_round_rate(clk)) {\r
- rate_new=clk_round_rate_nolock(clk, rate_hz);\r
- }\r
- if(rate_new==rate_old)\r
+ if (*volt_dep_new < low_boundary || *volt_dep_new > up_boundary) {\r
+\r
+ if (*volt_dep_new < low_boundary) {\r
+ *volt_dep_new = low_boundary;\r
+ \r
+ } else if (*volt_dep_new > up_boundary) {\r
+ *volt_new = *volt_dep_new - dep_biger_than_clk;\r
+ }\r
+ DVFS_LOG("%s target volt out of bondary volt=%d(old=%d), volt_dep=%d(dep_old=%d), up_bnd=%d(dn=%d)\n",\r
+ __func__, *volt_new, volt_old, *volt_dep_new, volt_dep_old, up_boundary, low_boundary); \r
return 0;\r
+ }\r
+ return 0;\r
\r
+}\r
+int dvfs_scale_volt(struct vd_node *vd_clk, struct vd_node *vd_dep, \r
+ int volt_old, int volt_new, int volt_dep_old, int volt_dep_new, int clk_biger_than_dep, int dep_biger_than_clk)\r
+{\r
+ struct regulator *regulator, *regulator_dep;\r
+ int volt = 0, volt_dep = 0, step = 0, step_dep = 0;\r
+ int volt_pre = 0, volt_dep_pre = 0;\r
+ int ret = 0;\r
\r
- // DVFS_DBG("dvfs(%s) round rate(%lu)(rount %lu)\n",dvfs_clk->name,rate_hz,rate_new);\r
+ DVFS_DBG("ENTER %s, volt=%d(old=%d), volt_dep=%d(dep_old=%d)\n", __func__, volt_new, volt_old, volt_dep_new, volt_dep_old);\r
+ regulator = vd_clk->regulator;\r
+ regulator_dep = vd_dep->regulator;\r
\r
- /* find the clk corresponding voltage */\r
- if (dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
- DVFS_ERR("%s--%s:rate%lu,Get corresponding voltage error!\n", \r
- __func__, dvfs_clk->name, rate_new);\r
+ if (IS_ERR_OR_NULL(regulator) || IS_ERR(regulator_dep)) { \r
+ DVFS_ERR("%s dvfs_clk->vd->regulator or depend->dep_vd->regulator == NULL\n", __func__);\r
return -1;\r
}\r
- volt_old = dvfs_clk->vd->cur_volt;\r
- volt_clk_old = dvfs_clk->set_volt;\r
- dvfs_clk->set_volt = clk_fv.index;\r
- volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
\r
- DVFS_DBG("dvfs--(%s),volt=%d(was %dmV),rate=%lu(was %lu),vd%u=(was%u)\n",\r
- dvfs_clk->name, clk_fv.index, dvfs_clk->set_volt, rate_new, rate_old\r
- , volt_new, volt_old);\r
+ volt = volt_old;\r
+ volt_dep = volt_dep_old;\r
\r
- if (flag_core_set_volt_err) {\r
- /* It means the last time set voltage error */ \r
- if (!IS_ERR(dvfs_clk->vd->regulator))\r
- flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
- else {\r
- DVFS_ERR("dvfs regulator is ERROR\n");\r
- }\r
+ step = volt_new - volt_old > 0 ? 1 : (-1);\r
+ step_dep = volt_dep_new - volt_dep_old > 0 ? 1 : (-1);\r
\r
- flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
- if (flag_set_volt_correct <= 0) {\r
- DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt error %d!!! stop scaling\n", \r
- __func__, dvfs_clk->name, volt_new, volt_old, \r
- rate_new, rate_old, flag_set_volt_correct);\r
- return -1;\r
- }\r
+ DVFS_DBG("step=%d step_dep=%d %d\n", step, step_dep, step * step_dep);\r
+\r
+ DVFS_DBG("Volt_new=%d(old=%d), volt_dep_new=%d(dep_old=%d)\n",\r
+ volt_new, volt_old, volt_dep_new, volt_dep_old);\r
+ do {\r
+ volt_pre = volt;\r
+ volt_dep_pre = volt_dep;\r
+ if (step * step_dep < 0) {\r
+ // target is between volt_old and volt_dep_old, just\r
+ // need one step\r
+ DVFS_DBG("step * step_dep < 0\n");\r
+ volt = volt_new;\r
+ volt_dep = volt_dep_new;\r
+ \r
+ } else if (step > 0) {\r
+ // up voltage\r
+ DVFS_DBG("step > 0\n");\r
+\r
+ if (volt > volt_dep) {\r
+ if (volt_dep == volt_dep_new) {\r
+ volt = volt_dep + clk_biger_than_dep;\r
+ } else {\r
+ volt_dep = volt + dep_biger_than_clk;\r
+ }\r
+ } else {\r
+ if (volt == volt_new) {\r
+ volt_dep = volt + dep_biger_than_clk;\r
+ } else {\r
+ volt = volt_dep + clk_biger_than_dep;\r
+ }\r
+ }\r
+ volt = volt > volt_new ? volt_new : volt;\r
+ volt_dep = volt_dep > volt_dep_new ? volt_dep_new : volt_dep;\r
+\r
+ } else if (step < 0) {\r
+ // down voltage\r
+ DVFS_DBG("step < 0\n");\r
+ if (volt > volt_dep) {\r
+ if (volt == volt_new) {\r
+ volt_dep = volt - clk_biger_than_dep;\r
+ } else {\r
+ volt = volt_dep - dep_biger_than_clk;\r
+ }\r
+ } else {\r
+ if (volt_dep == volt_dep_new) {\r
+ volt = volt_dep - dep_biger_than_clk;\r
+ } else {\r
+ volt_dep = volt - clk_biger_than_dep;\r
+ }\r
+ }\r
+ volt = volt < volt_new ? volt_new : volt;\r
+ volt_dep = volt_dep < volt_dep_new ? volt_dep_new : volt_dep;\r
\r
- flag_core_set_volt_err = 0;\r
- DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt! core_volt_correct = %d\n", \r
- __func__, dvfs_clk->name, volt_new, volt_old, \r
- rate_new, rate_old, flag_set_volt_correct);\r
+ } else {\r
+ DVFS_ERR("Oops, some bugs here:Volt_new=%d(old=%d), volt_dep_new=%d(dep_old=%d)\n", \r
+ volt_new, volt_old, volt_dep_new, volt_dep_old);\r
+ goto fail;\r
+ }\r
\r
- /* Reset vd's voltage */\r
- dvfs_clk->vd->cur_volt = flag_set_volt_correct;\r
- volt_old = dvfs_clk->vd->cur_volt;\r
- }\r
+ DVFS_DBG("\t\tNOW:Volt=%d, volt_dep=%d\n", volt, volt_dep);\r
\r
- /* if up the voltage */\r
- if (volt_old < volt_new) {\r
- if (!IS_ERR(dvfs_clk->vd->regulator)) {\r
- ret = dvfs_regulator_set_voltage_readback(dvfs_clk->vd->regulator, volt_new, volt_new);\r
+ if (vd_clk->cur_volt != volt) {\r
+ ret = dvfs_regulator_set_voltage_readback(regulator, volt, volt);\r
+ udelay(get_volt_up_delay(volt, volt_pre));\r
if (ret < 0) {\r
- flag_core_set_volt_err = 1;\r
- DVFS_ERR("%s %s set voltage up err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n", \r
- __func__, dvfs_clk->name, ret, \r
- rate_new, rate_old, volt_new, volt_old);\r
- return -1;\r
+ DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n", \r
+ __func__, vd_clk->name, ret, volt_new, volt_old);\r
+ goto fail;\r
}\r
+ vd_clk->cur_volt = volt;\r
+ }\r
\r
- } else {\r
- DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
- return -1;\r
+ if (vd_dep->cur_volt != volt_dep) {\r
+ ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep, volt_dep);\r
+ udelay(get_volt_up_delay(volt_dep, volt_dep_pre));\r
+ if (ret < 0) {\r
+ DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n", \r
+ __func__, vd_dep->name, ret, volt_dep_new, volt_dep_old);\r
+ goto fail;\r
+ }\r
+ vd_dep->cur_volt = volt_dep;\r
}\r
\r
- dvfs_clk->vd->cur_volt = volt_new;\r
- udelay(get_volt_up_delay(volt_new, volt_old));\r
- DVFS_DBG("%s %s set voltage OK up ret = %d, Vnew = %d(was %d), Rnew = %lu(was %lu)\n", \r
- __func__, dvfs_clk->name, ret, volt_new, volt_old, rate_new, rate_old);\r
+ } while (volt != volt_new || volt_dep!= volt_dep_new);\r
+ \r
+ vd_clk->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
+ vd_clk->cur_volt = volt_new;\r
+ \r
+ return 0;\r
+fail:\r
+ DVFS_ERR("+++++++++++++++++FAIL AREA\n"); \r
+ vd_clk->cur_volt = volt_old;\r
+ vd_dep->cur_volt = volt_dep_old;\r
+ vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
+ ret = dvfs_regulator_set_voltage_readback(regulator, volt_old, volt_old);\r
+ if (ret < 0) {\r
+ vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
+ DVFS_ERR("%s %s set callback voltage err ret = %d, Vnew = %d(was %d)mV\n", \r
+ __func__, vd_clk->name, ret, volt_new, volt_old);\r
+ }\r
+ \r
+ ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep_old, volt_dep_old);\r
+ if (ret < 0) {\r
+ vd_dep->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
+ DVFS_ERR("%s %s set callback voltage err ret = %d, Vnew = %d(was %d)mV\n", \r
+ __func__, vd_dep->name, ret, volt_dep_new, volt_dep_old);\r
}\r
\r
- if (dvfs_clk->clk_dvfs_target) {\r
- ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
+ return -1;\r
+}\r
+\r
+int dvfs_scale_volt_direct(struct vd_node *vd_clk, int volt_new)\r
+{\r
+ int ret = 0;\r
+ DVFS_DBG("ENTER %s, volt=%d(old=%d)\n", __func__, volt_new, vd_clk->cur_volt);\r
+ if (IS_ERR_OR_NULL(vd_clk)) {\r
+ DVFS_ERR("%s vd_node error\n", __func__);\r
+ return -1;\r
+ }\r
+\r
+ DVFS_DBG("ENTER %s, volt=%d(old=%d)\n", __func__, volt_new, vd_clk->cur_volt);\r
+ if (!IS_ERR_OR_NULL(vd_clk->regulator)) {\r
+ ret = dvfs_regulator_set_voltage_readback(vd_clk->regulator, volt_new, volt_new);\r
+ if (ret < 0) {\r
+ vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
+ DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n", \r
+ __func__, vd_clk->name, ret, volt_new, vd_clk->cur_volt);\r
+ return -1;\r
+ }\r
+\r
} else {\r
- ret = clk_set_rate_locked(clk, rate_new);\r
+ DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
+ return -1;\r
}\r
\r
+ vd_clk->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
+ vd_clk->cur_volt = volt_new;\r
+\r
+ return 0;\r
+\r
+}\r
+\r
+int dvfs_scale_volt_bystep(struct vd_node *vd_clk, struct vd_node *vd_dep, int volt_new, int volt_dep_new, \r
+ int clk_biger_than_dep, int dep_biger_than_clk)\r
+\r
+{\r
+ int ret = 0;\r
+ int volt_old = 0, volt_dep_old = 0;\r
+\r
+ volt_old = vd_clk->cur_volt;\r
+ volt_dep_old = vd_dep->cur_volt;\r
+\r
+ DVFS_DBG("ENTER %s, volt=%d(old=%d) vd_dep=%d(dep_old=%d)\n", __func__, \r
+ volt_new, volt_old, volt_dep_new, volt_dep_old);\r
+\r
+ if (check_volt_correct(volt_old, &volt_new, volt_dep_old, &volt_dep_new, \r
+ clk_biger_than_dep, dep_biger_than_clk) < 0) {\r
+ DVFS_ERR("CURRENT VOLT INCORRECT\n");\r
+ return -1;\r
+ }\r
+ DVFS_DBG("ENTER %s, volt=%d(old=%d), volt_dep=%d(dep_old=%d)\n", __func__, \r
+ volt_new, volt_old, volt_dep_new, volt_dep_old);\r
+ ret = dvfs_scale_volt(vd_clk, vd_dep, volt_old, volt_new, volt_dep_old, volt_dep_new, \r
+ clk_biger_than_dep, dep_biger_than_clk);\r
if (ret < 0) {\r
+ vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
+ DVFS_ERR("set volt error\n");\r
+ return -1;\r
+ }\r
\r
- dvfs_clk->set_volt = volt_old;\r
- dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
- DVFS_ERR("set rate err\n");\r
+ return 0;\r
+}\r
+\r
+int dvfs_reset_volt(struct vd_node *dvfs_vd)\r
+{ \r
+ int flag_set_volt_correct = 0;\r
+ if (!IS_ERR_OR_NULL(dvfs_vd->regulator))\r
+ flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_vd->regulator);\r
+ else {\r
+ DVFS_ERR("dvfs regulator is ERROR\n");\r
return -1;\r
}\r
- dvfs_clk->set_freq = rate_new / 1000;\r
+ if (flag_set_volt_correct <= 0) {\r
+ DVFS_ERR("%s (clk:%s), try to reload arm_volt error %d!!! stop scaling\n", \r
+ __func__, dvfs_vd->name, flag_set_volt_correct);\r
+ return -1;\r
+ }\r
+ dvfs_vd->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
+ DVFS_ERR("%s (clk:%s), try to reload arm_volt! arm_volt_correct = %d\n", \r
+ __func__, dvfs_vd->name, flag_set_volt_correct);\r
\r
- /* if down the voltage */\r
- if (volt_old > volt_new) {\r
- if (!IS_ERR(dvfs_clk->vd->regulator)) {\r
- ret = dvfs_regulator_set_voltage_readback(dvfs_clk->vd->regulator, volt_new, volt_new);\r
+ /* Reset vd's voltage */\r
+ dvfs_vd->cur_volt = flag_set_volt_correct;\r
+\r
+ return dvfs_vd->cur_volt;\r
+}\r
+\r
+int dvfs_get_depend_volt(struct clk_node *dvfs_clk, struct vd_node *dvfs_vd_dep, int rate_new)\r
+{\r
+ struct depend_list *depend;\r
+ struct cpufreq_frequency_table clk_fv_dep;\r
+ int ret = 0;\r
+\r
+ DVFS_DBG("ENTER %s, rate_new=%d\n", __func__, rate_new);\r
+ list_for_each_entry(depend, &dvfs_clk->depend_list, node2clk) {\r
+ DVFS_DBG("--round depend clk:%s(depend:%s)\n", depend->dvfs_clk->name, depend->dep_vd->name);\r
+ // this place just consider ONE depend voltage domain,\r
+ // multi-depends must have some differece\r
+ clk_fv_dep.index = 0;\r
+ if (depend->dep_vd == dvfs_vd_dep) {\r
+ ret = dvfs_clk_get_ref_volt_depend(depend, rate_new / 1000, &clk_fv_dep);\r
if (ret < 0) {\r
- flag_core_set_volt_err = 1;\r
- DVFS_ERR("%s %s set voltage down err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n", \r
- __func__, dvfs_clk->name, ret, rate_new, rate_old, \r
- volt_new, volt_old);\r
+ DVFS_ERR("%s get dvfs_ref_volt_depend error\n", __func__);\r
return -1;\r
}\r
-\r
- } else {\r
- DVFS_ERR("%s down volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
- return -1;\r
+ depend->req_volt = clk_fv_dep.index;\r
+ return depend->req_volt;\r
}\r
-\r
- dvfs_clk->vd->cur_volt = volt_new;\r
- DVFS_DBG("dvfs %s set volt ok dn\n", dvfs_clk->name);\r
-\r
}\r
\r
- return 0;\r
+ DVFS_ERR("%s can not find vd node %s\n", __func__, dvfs_vd_dep->name);\r
+ return -1;\r
}\r
-\r
-static int flag_arm_set_volt_err = 0;\r
+struct clk_node *clk_cpu;\r
+static struct vd_node vd_core;\r
int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)\r
{\r
struct clk_node *dvfs_clk;\r
- int volt_new = 0, volt_old = 0;\r
+ int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
struct cpufreq_frequency_table clk_fv;\r
int ret = 0;\r
- int flag_set_volt_correct = 0;\r
unsigned long rate_new, rate_old;\r
-\r
-\r
+ \r
if (!clk) {\r
- DVFS_ERR("%s is not clk\n", __func__);\r
+ DVFS_ERR("%s is not a clk\n", __func__);\r
return -1;\r
}\r
dvfs_clk = clk_get_dvfs_info(clk);\r
+ DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
\r
- if (!dvfs_clk || dvfs_clk->vd->regulator == NULL) {\r
+ if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
return -1;\r
}\r
\r
+ if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
+ /* It means the last time set voltage error */\r
+ ret = dvfs_reset_volt(dvfs_clk->vd);\r
+ if (ret < 0) {\r
+ return -1;\r
+ }\r
+ }\r
+\r
/* Check limit rate */\r
if (dvfs_clk->freq_limit_en) {\r
if (rate_hz < dvfs_clk->min_rate) {\r
}\r
\r
/* need round rate */\r
+ rate_old = clk_get_rate(clk);\r
rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu)\n", dvfs_clk->name, rate_hz, rate_new);\r
+ DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n", \r
+ dvfs_clk->name, rate_hz, rate_new, rate_old);\r
\r
- rate_old = clk_get_rate(clk);\r
/* find the clk corresponding voltage */\r
if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
return -1;\r
}\r
+ clk_volt_store = dvfs_clk->set_volt;\r
+ dvfs_clk->set_volt = clk_fv.index;\r
+ volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
\r
- volt_old = dvfs_clk->vd->cur_volt;\r
- volt_new = clk_fv.index;\r
- if (flag_arm_set_volt_err) {\r
- /* It means the last time set voltage error */\r
- if (!IS_ERR(dvfs_clk->vd->regulator))\r
- flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
- else {\r
- DVFS_ERR("dvfs regulator is ERROR\n");\r
- }\r
- if (flag_set_volt_correct <= 0) {\r
- DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload arm_volt error %d!!! stop scaling\n", \r
- __func__, dvfs_clk->name, volt_new, volt_old, \r
- rate_new, rate_old, flag_set_volt_correct);\r
- return -1;\r
+ /* if up the rate */\r
+ if (rate_new > rate_old) {\r
+ if (!list_empty(&dvfs_clk->depend_list)) {\r
+ // update depend's req_volt\r
+ ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
+ if (ret <= 0)\r
+ goto fail_roll_back;\r
+ \r
+ volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
+ if (volt_dep_new <= 0) \r
+ goto fail_roll_back;\r
+\r
+ ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new, \r
+ ARM_HIGHER_LOGIC, LOGIC_HIGHER_ARM); \r
+ if (ret < 0) \r
+ goto fail_roll_back;\r
+ } else {\r
+ ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
+ if (ret < 0) \r
+ goto fail_roll_back;\r
}\r
+ }\r
\r
- flag_arm_set_volt_err = 0;\r
- DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload arm_volt! arm_volt_correct = %d\n", \r
- __func__, dvfs_clk->name, volt_new, volt_old, \r
- rate_new, rate_old, flag_set_volt_correct);\r
+ /* scale rate */\r
+ if (dvfs_clk->clk_dvfs_target) {\r
+ ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
+ } else {\r
+ ret = clk_set_rate_locked(clk, rate_new);\r
+ }\r
\r
- /* Reset vd's voltage */\r
- dvfs_clk->vd->cur_volt = flag_set_volt_correct;\r
- volt_old = dvfs_clk->vd->cur_volt;\r
+ if (ret < 0) {\r
+ DVFS_ERR("%s set rate err\n", __func__);\r
+ goto fail_roll_back;\r
}\r
+ dvfs_clk->set_freq = rate_new / 1000;\r
\r
- /* if up the voltage */\r
- if (volt_old < volt_new) {\r
- if (!IS_ERR(dvfs_clk->vd->regulator)) {\r
- ret = dvfs_regulator_set_voltage_readback(dvfs_clk->vd->regulator, volt_new, volt_new);\r
- if (ret < 0) {\r
- flag_arm_set_volt_err = 1;\r
- DVFS_ERR("%s %s set voltage up err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n", \r
- __func__, dvfs_clk->name, ret, rate_new, rate_old, \r
- volt_new, volt_old);\r
- return -1;\r
- }\r
+ DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
\r
+ /* if down the rate */\r
+ if (rate_new < rate_old) {\r
+ if (!list_empty(&dvfs_clk->depend_list)) {\r
+ // update depend's req_volt\r
+ ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
+ if (ret <= 0)\r
+ goto out;\r
+ \r
+ volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
+ if (volt_dep_new <= 0) \r
+ goto out;\r
+\r
+ ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new, \r
+ ARM_HIGHER_LOGIC, LOGIC_HIGHER_ARM); \r
+ if (ret < 0) \r
+ goto out;\r
} else {\r
- DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
- return -1;\r
+ ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
+ if (ret < 0) \r
+ goto out;\r
}\r
+ }\r
\r
- dvfs_clk->vd->cur_volt = volt_new;\r
- udelay(get_volt_up_delay(volt_new, volt_old));\r
- DVFS_DBG("%s %s set voltage OK up ret = %d, Vnew = %d(was %d), Rnew = %lu(was %lu)\n", \r
- __func__, dvfs_clk->name, ret, volt_new, volt_old, rate_new, rate_old);\r
+ return ret;\r
+fail_roll_back:\r
+ dvfs_clk->set_volt = clk_volt_store;\r
+ ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
+ if (ret <= 0) {\r
+ DVFS_ERR("%s dvfs_get_depend_volt error when roll back!\n", __func__);\r
}\r
+out:\r
+ return -1;\r
+}\r
+\r
+int dvfs_target_core(struct clk *clk, unsigned long rate_hz)\r
+{\r
+ struct clk_node *dvfs_clk;\r
+ int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
\r
- /* depend voltage domain set up*/\r
- if (0 != dvfs_set_depend_pre(dvfs_clk, rate_old, rate_new)) {\r
- DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), set depend pre voltage err, stop scaling\n", \r
- __func__, dvfs_clk->name, volt_new, volt_old, \r
- rate_new, rate_old);\r
+ struct cpufreq_frequency_table clk_fv;\r
+ \r
+ int ret = 0;\r
+ unsigned long rate_new, rate_old;\r
+ \r
+ if (!clk) {\r
+ DVFS_ERR("%s is not a clk\n", __func__);\r
+ return -1;\r
+ }\r
+ dvfs_clk = clk_get_dvfs_info(clk);\r
+ DVFS_DBG("enter %s: clk(%s) rate = %lu Hz\n", __func__, dvfs_clk->name, rate_hz);\r
+\r
+ if (!dvfs_clk || dvfs_clk->vd == NULL || IS_ERR_OR_NULL(dvfs_clk->vd->regulator)) {\r
+ DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);\r
return -1;\r
}\r
\r
+ if (dvfs_clk->vd->volt_set_flag == DVFS_SET_VOLT_FAILURE) {\r
+ /* It means the last time set voltage error */\r
+ ret = dvfs_reset_volt(dvfs_clk->vd);\r
+ if (ret < 0) {\r
+ return -1;\r
+ }\r
+ }\r
+\r
+ /* Check limit rate */\r
+ if (dvfs_clk->freq_limit_en) {\r
+ if (rate_hz < dvfs_clk->min_rate) {\r
+ rate_hz = dvfs_clk->min_rate;\r
+ } else if (rate_hz > dvfs_clk->max_rate) {\r
+ rate_hz = dvfs_clk->max_rate;\r
+ }\r
+ }\r
+ \r
+ /* need round rate */\r
+ rate_old = clk_get_rate(clk);\r
+ rate_new = clk_round_rate_nolock(clk, rate_hz);\r
+ DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n", \r
+ dvfs_clk->name, rate_hz, rate_new, rate_old);\r
+\r
+ /* find the clk corresponding voltage */\r
+ if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {\r
+ DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);\r
+ return -1;\r
+ }\r
+ clk_volt_store = dvfs_clk->set_volt;\r
+ dvfs_clk->set_volt = clk_fv.index;\r
+ volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
+\r
+ /* if up the rate */\r
+ if (rate_new > rate_old) {\r
+ DVFS_DBG("-----------------------------rate_new > rate_old\n");\r
+ volt_dep_new = dvfs_vd_get_newvolt_byclk(clk_cpu);\r
+\r
+ if (volt_dep_new < 0) \r
+ goto fail_roll_back;\r
+\r
+ ret = dvfs_scale_volt_bystep(dvfs_clk->vd, clk_cpu->vd, volt_new, volt_dep_new, \r
+ LOGIC_HIGHER_ARM, ARM_HIGHER_LOGIC); \r
+ if (ret < 0) \r
+ goto fail_roll_back;\r
+ }\r
+\r
+ /* scale rate */\r
if (dvfs_clk->clk_dvfs_target) {\r
ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
} else {\r
+ \r
ret = clk_set_rate_locked(clk, rate_new);\r
}\r
\r
if (ret < 0) {\r
- DVFS_ERR("set rate err\n");\r
- return -1;\r
+ DVFS_ERR("%s set rate err\n", __func__);\r
+ goto fail_roll_back;\r
}\r
dvfs_clk->set_freq = rate_new / 1000;\r
\r
DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));\r
\r
- /* depend voltage domain set down*/\r
- if (0 != dvfs_set_depend_post(dvfs_clk, rate_old, rate_new)) {\r
- DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), set depend post voltage err, stop scaling\n", \r
- __func__, dvfs_clk->name, volt_new, volt_old, \r
- rate_new, rate_old);\r
- return -1;\r
- }\r
-\r
- /* if down the voltage */\r
- if (volt_old > volt_new) {\r
- if (!IS_ERR(dvfs_clk->vd->regulator)) {\r
- ret = dvfs_regulator_set_voltage_readback(dvfs_clk->vd->regulator, volt_new, volt_new);\r
- if (ret < 0) {\r
- flag_arm_set_volt_err = 1;\r
- DVFS_ERR("%s %s set voltage down err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n", \r
- __func__, dvfs_clk->name, ret, rate_new, rate_old, \r
- volt_new, volt_old);\r
- return -1;\r
- }\r
-\r
- } else {\r
- DVFS_ERR("%s down volt dvfs_clk->vd->regulator == NULL\n", __func__);\r
- return -1;\r
- }\r
+ /* if down the rate */\r
+ if (rate_new < rate_old) {\r
+ DVFS_DBG("-----------------------------rate_new < rate_old\n");\r
+ volt_dep_new = dvfs_vd_get_newvolt_byclk(clk_cpu);\r
\r
- dvfs_clk->vd->cur_volt = volt_new;\r
- DVFS_DBG("dvfs %s set volt ok dn\n", dvfs_clk->name);\r
+ if (volt_dep_new < 0) \r
+ goto out;\r
\r
+ ret = dvfs_scale_volt_bystep(dvfs_clk->vd, clk_cpu->vd, volt_new, volt_dep_new, \r
+ LOGIC_HIGHER_ARM, ARM_HIGHER_LOGIC); \r
+ if (ret < 0) \r
+ goto out;\r
}\r
\r
return ret;\r
-}\r
-\r
+fail_roll_back: \r
+ dvfs_clk->set_volt = clk_volt_store;\r
+ ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
+ if (ret <= 0) {\r
+ DVFS_ERR("%s dvfs_get_depend_volt error when roll back!\n", __func__);\r
+ }\r
\r
+out:\r
+ return -1;\r
+}\r
\r
/*****************************init**************************/\r
/**\r
\r
static struct depend_lookup rk30_depends[] = {\r
RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),\r
+ //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
+ //RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
};\r
\r
int rk30_dvfs_init(void)\r
for (i = 0; i < ARRAY_SIZE(rk30_depends); i++) {\r
rk_regist_depends(&rk30_depends[i]);\r
}\r
+ clk_cpu = dvfs_get_dvfs_clk_byname("cpu");\r
return 0;\r
}\r
\r
} else {\r
list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
if (0 == strcmp(vd->name, depend_vd_name)) {\r
- DVFS_DBG("%S FOUND A MATCH vd\n", __func__);\r
+ DVFS_DBG("%s FOUND A MATCH vd\n", __func__);\r
mutex_lock(&mutex);\r
list_for_each_entry(depend, &info->depend_list, node2clk) {\r
if (vd == depend->dep_vd && info == depend->dvfs_clk) {\r
- DVFS_DBG("%S FOUND A MATCH table\n", __func__);\r
+ DVFS_DBG("%s FOUND A MATCH table\n", __func__);\r
table = depend->dep_table;\r
break;\r
}\r
return -1;\r
}\r
if (avs_scale_volt != 0) {\r
- DVFS_LOG("AVS scale %s, depend name = %s, voltage = %d\n",\r
+ DVFS_DBG("AVS scale %s, depend name = %s, voltage = %d\n",\r
info->name, depend_vd_name, avs_scale_volt);\r
for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
table[i].index = avs_get_scal_val(table[i].index);\r
s8 step = 0;\r
\r
if (avs_base < avs_test) {\r
- DVFS_LOG("AVS down voltage, ignore\n");\r
+ DVFS_DBG("AVS down voltage, ignore\n");\r
return 0;\r
}\r
step = (avs_base - avs_test) / AVS_VAL_PER_STEP;\r
step += 1;\r
avs_scale_volt = (step) * (VOL_DYN_STEP);\r
\r
- DVFS_LOG("avs_set_scal_val test=%d,base=%d,step=%d,scale_vol=%d\n",\r
+ DVFS_DBG("avs_set_scal_val test=%d,base=%d,step=%d,scale_vol=%d\n",\r
avs_test, avs_base, step, avs_scale_volt);\r
return 0;\r
}\r
avs_dyn_start = 1;\r
}\r
//sscanf(pbuf, "%d %d", &number, &voltage);\r
- //DVFS_LOG("---------ldo %d %d\n", number, voltage);\r
+ //DVFS_DBG("---------ldo %d %d\n", number, voltage);\r
\r
} else if((strncmp(buf, "stop", strlen("stop")) == 0)) {\r
pbuf = &buf[strlen("stop")];\r
avs_dyn_start = 0;\r
show_line_cnt = 0;\r
//sscanf(pbuf, "%d %d", &number, &voltage);\r
- //DVFS_LOG("---------dcdc %d %d\n", number, voltage);\r
+ //DVFS_DBG("---------dcdc %d %d\n", number, voltage);\r
}\r
\r
\r
for (i = 0; (depend->dep_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
s += sprintf(s, "| | | | |- freq = %d, req_volt = %d\n", \r
depend->dep_table[i].frequency, \r
- depend->dep_table[i].index);\r
\r
+ depend->dep_table[i].index);\r
}\r
}\r
}\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff