rk30_pm_set_power_domain(pmu_pwrdn_st, false);
sram_printch('1');
+ local_fiq_disable();
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
board_gpio_suspend();
- local_fiq_disable();
-
flush_tlb_all();
interface_ctr_reg_pread();
rk30_suspend();
sram_printch('4');
- local_fiq_enable();
-
board_gpio_resume();
sram_printch('3');
cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
}
+ local_fiq_enable();
sram_printch('1');
rk30_pm_set_power_domain(pmu_pwrdn_st, true);