CONFIG_SND_SOC=y
CONFIG_SND_RK29_SOC=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
-CONFIG_SND_RK29_SOC_RT5631=y
+CONFIG_SND_RK29_SOC_RT5623=y
+CONFIG_SND_RK29_SOC_RT3261=y
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
.flags = 0,
},
#endif
+
+#if defined (CONFIG_SND_SOC_RT5623)
+ {
+ .type = "rt5623",
+ .addr = 0x1a,
+ .flags = 0,
+ },
+#endif
#if defined (CONFIG_SND_SOC_RT5631)
{
.type = "rt5631",
.flags = 0,
},
#endif
+#if defined (CONFIG_SND_SOC_RT3261)
+ {
+ .type = "rt3261",
+ .addr = 0x1c,
+ .flags = 0,
+ },
+#endif
#ifdef CONFIG_MFD_RK610
{
select SND_SOC_RT5621 if I2C
select SND_SOC_RT5631 if I2C
select SND_SOC_RT5625 if I2C
+ select SND_SOC_RT3261 if I2C
+ select SND_SOC_RT5623 if I2C
select SND_SOC_RK610 if I2C
select SND_SOC_WM8903 if I2C
select SND_SOC_WM8904 if I2C
config SND_SOC_RT5621
tristate
+config SND_SOC_RT5623
+ tristate
+
config SND_SOC_RT5631
tristate
config SND_SOC_RT5625
tristate
+config SND_SOC_RT3261
+ tristate
+
config SND_SOC_WM8903
tristate
snd-soc-wm8804-objs := wm8804.o
snd-soc-wm8900-objs := wm8900.o
snd-soc-rt5621-objs := rt5621.o
+snd-soc-rt5623-objs := rt5623.o
snd-soc-rt5631-objs := rt5631.o
snd-soc-rt5625-objs := rt5625.o
snd-soc-cs42l52-objs := cs42l52.o
snd-soc-rk1000-objs := rk1000_codec.o
snd-soc-jz4740-codec-objs := jz4740.o
snd-soc-rk610-objs := rk610_codec.o
+snd-soc-rt3261-objs := rt3261.o rt3261-dsp.o rt3261_ioctl.o rt_codec_ioctl.o
# Amp
snd-soc-lm4857-objs := lm4857.o
snd-soc-tpa6130a2-objs := tpa6130a2.o
snd-soc-wm2000-objs := wm2000.o
snd-soc-wm9090-objs := wm9090.o
-
+obj-$(CONFIG_SND_SOC_RT3261) += snd-soc-rt3261.o
obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o
obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o
obj-$(CONFIG_SND_SOC_AD1836) += snd-soc-ad1836.o
obj-$(CONFIG_SND_SOC_WM8804) += snd-soc-wm8804.o
obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o
obj-$(CONFIG_SND_SOC_RT5621) += snd-soc-rt5621.o
+obj-$(CONFIG_SND_SOC_RT5623) += snd-soc-rt5623.o
obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
obj-$(CONFIG_SND_SOC_RT5625) += snd-soc-rt5625.o
obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
--- /dev/null
+/*
+ * rt3261.c -- RT3261 ALSA SoC DSP driver
+ *
+ * Copyright 2011 Realtek Semiconductor Corp.
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+#define RTK_IOCTL
+#ifdef RTK_IOCTL
+#include <linux/spi/spi.h>
+#include "rt_codec_ioctl.h"
+#endif
+
+#include "rt3261.h"
+#include "rt3261-dsp.h"
+
+static const u16 rt3261_dsp_init[][2] = {
+ {0x3fd2, 0x0038}, {0x229C, 0x0fa0}, {0x22d2, 0x8400}, {0x22ee, 0x0001},
+ {0x22f2, 0x0040}, {0x22f5, 0x8000}, {0x22f6, 0x0000}, {0x22f9, 0x007f},
+ {0x2310, 0x0880},
+};
+#define RT3261_DSP_INIT_NUM \
+ (sizeof(rt3261_dsp_init) / sizeof(rt3261_dsp_init[0]))
+
+static const u16 rt3261_dsp_48[][2] = {
+ {0x22c8, 0x0026}, {0x22fe, 0x0fa0}, {0x22ff, 0x3893}, {0x22fa, 0x2487},
+ {0x2301, 0x0002},
+};
+#define RT3261_DSP_48_NUM (sizeof(rt3261_dsp_48) / sizeof(rt3261_dsp_48[0]))
+
+static const u16 rt3261_dsp_441[][2] = {
+ {0x22c6, 0x0031}, {0x22c7, 0x0050}, {0x22c8, 0x0009}, {0x22fe, 0x0e5b},
+ {0x22ff, 0x3c83}, {0x22fa, 0x2484}, {0x2301, 0x0001},
+};
+#define RT3261_DSP_441_NUM (sizeof(rt3261_dsp_441) / sizeof(rt3261_dsp_441[0]))
+
+static const u16 rt3261_dsp_16[][2] = {
+ {0x22c8, 0x0026}, {0x22fa, 0x2484}, {0x2301, 0x0002},
+};
+#define RT3261_DSP_16_NUM (sizeof(rt3261_dsp_16) / sizeof(rt3261_dsp_16[0]))
+
+static const u16 rt3261_dsp_aec_ns_fens[][2] = {
+ {0x22f8, 0x8005}, {0x2303, 0x0971}, {0x2304, 0x0312}, {0x2305, 0x0005},
+ {0x2309, 0x0400}, {0x230a, 0x1b00}, {0x230c, 0x0200}, {0x230d, 0x0300},
+ {0x2310, 0x0824}, {0x2325, 0x5000}, {0x2326, 0x0040}, {0x232f, 0x0080},
+ {0x2332, 0x0080}, {0x2333, 0x0008}, {0x2337, 0x0002}, {0x2339, 0x0010},
+ {0x2348, 0x1000}, {0x2349, 0x1000}, {0x2360, 0x0180}, {0x2361, 0x1800},
+ {0x2362, 0x0180}, {0x2363, 0x0100}, {0x2364, 0x0078}, {0x2365, 0x2000},
+ {0x236e, 0x1800}, {0x236f, 0x0a0a}, {0x2370, 0x0f00}, {0x2372, 0x1a00},
+ {0x2373, 0x3000}, {0x2374, 0x2400}, {0x2375, 0x1800}, {0x2380, 0x7fff},
+ {0x2381, 0x4000}, {0x2382, 0x0400}, {0x2383, 0x0400}, {0x2384, 0x0005},
+ {0x2385, 0x0005}, {0x238c, 0x0400}, {0x238e, 0x7000}, {0x2393, 0x4444},
+ {0x2394, 0x4444}, {0x2395, 0x4444}, {0x2396, 0x2000}, {0x2396, 0x3000},
+ {0x2398, 0x0020}, {0x23a5, 0x0006}, {0x23a6, 0x7fff}, {0x23b3, 0x000e},
+ {0x23b4, 0x000a}, {0x23b7, 0x0008}, {0x23bb, 0x1000}, {0x23bc, 0x0130},
+ {0x23bd, 0x0100}, {0x23be, 0x2400}, {0x23cf, 0x0800}, {0x23d0, 0x0400},
+ {0x23d1, 0xff80}, {0x23d2, 0xff80}, {0x23d3, 0x0800}, {0x23d4, 0x3e00},
+ {0x23d5, 0x5000}, {0x23e7, 0x0800}, {0x23e8, 0x0e00}, {0x23e9, 0x7000},
+ {0x23ea, 0x7ff0}, {0x23ed, 0x0300}, {0x22fb, 0x0000},
+};
+#define RT3261_DSP_AEC_NUM \
+ (sizeof(rt3261_dsp_aec_ns_fens) / sizeof(rt3261_dsp_aec_ns_fens[0]))
+
+static const u16 rt3261_dsp_hfbf[][2] = {
+ {0x22f8, 0x8004}, {0x22a0, 0x1205}, {0x22a1, 0x0f00}, {0x22a2, 0x1000},
+ {0x22a3, 0x1000}, {0x22a4, 0x1000}, {0x22aa, 0x0006}, {0x22ad, 0x0060},
+ {0x22ae, 0x0080}, {0x22af, 0x0000}, {0x22b0, 0x000e}, {0x22b1, 0x0010},
+ {0x22b2, 0x0006}, {0x22b3, 0x0001}, {0x22b4, 0x0010}, {0x22b5, 0x0001},
+ {0x22b7, 0x0005}, {0x22d8, 0x0017}, {0x22f9, 0x007f}, {0x2303, 0x0971},
+ {0x2304, 0x0302}, {0x2303, 0x0971}, {0x2304, 0x4302}, {0x2305, 0x102d},
+ {0x2309, 0x0400}, {0x230c, 0x0400}, {0x230d, 0x0200}, {0x232f, 0x0020},
+ {0x2332, 0x0100}, {0x2333, 0x0020}, {0x2337, 0xffff}, {0x2339, 0x0010},
+ {0x2348, 0x1000}, {0x2349, 0x1000}, {0x236e, 0x1800}, {0x236f, 0x1006},
+ {0x2370, 0x1000}, {0x2372, 0x0200}, {0x237b, 0x001e}, {0x2380, 0x7fff},
+ {0x2381, 0x4000}, {0x2382, 0x0080}, {0x2383, 0x0200}, {0x2386, 0x7f80},
+ {0x2387, 0x0040}, {0x238a, 0x0280}, {0x238c, 0x6000}, {0x238e, 0x5000},
+ {0x2396, 0x6a00}, {0x2397, 0x6000}, {0x2398, 0x00e0}, {0x23a5, 0x0005},
+ {0x23b3, 0x000f}, {0x23b4, 0x0003}, {0x23bb, 0x2000}, {0x23bc, 0x00d0},
+ {0x23bd, 0x0140}, {0x23be, 0x1000}, {0x23cf, 0x0800}, {0x23d0, 0x0400},
+ {0x23d1, 0x0100}, {0x23d2, 0x0100}, {0x23d5, 0x7c00}, {0x23ed, 0x0300},
+ {0x23ee, 0x3000}, {0x23ef, 0x2800}, {0x22fb, 0x0000},
+};
+#define RT3261_DSP_HFBF_NUM \
+ (sizeof(rt3261_dsp_hfbf) / sizeof(rt3261_dsp_hfbf[0]))
+
+static const u16 rt3261_dsp_ffp[][2] = {
+ {0x22f8, 0x8005}, {0x2303, 0x1971}, {0x2304, 0x8312}, {0x2305, 0x0005},
+ {0x2309, 0x0200}, {0x230a, 0x1b00}, {0x230c, 0x0800}, {0x230d, 0x0400},
+ {0x2325, 0x5000}, {0x2326, 0x0040}, {0x232f, 0x0080}, {0x2332, 0x0100},
+ {0x2333, 0x0020}, {0x2337, 0x0001}, {0x2339, 0x0010}, {0x233c, 0x0040},
+ {0x2348, 0x1000}, {0x2349, 0x1000}, {0x2360, 0x0180}, {0x2361, 0x1800},
+ {0x2362, 0x0200}, {0x2363, 0x0200}, {0x2364, 0x0200}, {0x2365, 0x2000},
+ {0x236e, 0x1000}, {0x236f, 0x0a05}, {0x2370, 0x0f00}, {0x2372, 0x1a00},
+ {0x2373, 0x3000}, {0x2374, 0x2400}, {0x2375, 0x1800}, {0x2380, 0x7fff},
+ {0x2381, 0x4000}, {0x2382, 0x0400}, {0x2383, 0x0400}, {0x2384, 0x0005},
+ {0x2385, 0x0005}, {0x238e, 0x7000}, {0x2393, 0x4444}, {0x2394, 0x4444},
+ {0x2395, 0x4444}, {0x2396, 0x2000}, {0x2397, 0x3000}, {0x2398, 0x0020},
+ {0x23a5, 0x0006}, {0x23a6, 0x7fff}, {0x23b3, 0x000a}, {0x23b4, 0x0006},
+ {0x23b7, 0x0008}, {0x23bb, 0x1000}, {0x23bc, 0x0130}, {0x23bd, 0x0160},
+ {0x23be, 0x2400}, {0x23cf, 0x0800}, {0x23d0, 0x0400}, {0x23d1, 0xff80},
+ {0x23d2, 0xff80}, {0x23d3, 0x2000}, {0x23d4, 0x5000}, {0x23d5, 0x5000},
+ {0x23e7, 0x0c00}, {0x23e8, 0x1400}, {0x23e9, 0x6000}, {0x23ea, 0x7f00},
+ {0x23ed, 0x0300}, {0x23ee, 0x2800}, {0x22fb, 0x0000},
+};
+#define RT3261_DSP_FFP_NUM (sizeof(rt3261_dsp_ffp) / sizeof(rt3261_dsp_ffp[0]))
+
+static const u16 rt3261_dsp_p3_tab[][3] = {
+ {0x4af0, 0x1000, 0x822b}, {0x90f0, 0x1001, 0x8393},
+ {0x64f0, 0x1002, 0x822b}, {0x0ff0, 0x1003, 0x26e0},
+ {0x55f0, 0x1004, 0x2200}, {0xcff0, 0x1005, 0x1a7b},
+ {0x5af0, 0x1006, 0x823a}, {0x90f0, 0x1007, 0x8393},
+ {0x64f0, 0x1008, 0x822b}, {0x0ff0, 0x1009, 0x26e0},
+ {0x03f0, 0x100a, 0x2218}, {0x0ef0, 0x100b, 0x3400},
+ {0x4ff0, 0x100c, 0x195e}, {0x00f0, 0x100d, 0x0000},
+ {0xf0f0, 0x100e, 0x8143}, {0x1ff0, 0x100f, 0x2788},
+ {0x0ef0, 0x1010, 0x3400}, {0xe0f0, 0x1011, 0x1a26},
+ {0x2cf0, 0x1012, 0x8001}, {0x0ff0, 0x1013, 0x267c},
+ {0x82f0, 0x1014, 0x1a27}, {0x3cf0, 0x1015, 0x8001},
+ {0x0ff0, 0x1016, 0x267c}, {0x82f0, 0x1017, 0x1a27},
+ {0xeff0, 0x1018, 0x1a26}, {0x01f0, 0x1019, 0x4ff0},
+ {0x5cf0, 0x101a, 0x2b81}, {0xfaf0, 0x101b, 0x2a6a},
+ {0x05f0, 0x101c, 0x4011}, {0x0ff0, 0x101d, 0x278e},
+ {0x0ef0, 0x101e, 0x3400}, {0xe1f0, 0x101f, 0x1997},
+ {0x1ff0, 0x1020, 0x1997}, {0x03f0, 0x1021, 0x2279},
+ {0xb8f0, 0x1022, 0x8206}, {0xf8f0, 0x1023, 0x0f00},
+ {0xfff0, 0x1024, 0x279e}, {0x0ff0, 0x1025, 0x2272},
+ {0x0ef0, 0x1026, 0x3400}, {0x3ff0, 0x1027, 0x199a},
+ {0x0ff0, 0x1028, 0x2262}, {0x0ff0, 0x1029, 0x2272},
+ {0x0ef0, 0x102a, 0x3400}, {0xfff0, 0x102b, 0x199a},
+ {0x7ff0, 0x102c, 0x22e2}, {0x0ef0, 0x102d, 0x3400},
+ {0xfff0, 0x102e, 0x19cb}, {0xfff0, 0x102f, 0x47ff},
+ {0xb1f0, 0x1030, 0x80b1}, {0x5ff0, 0x1031, 0x2261},
+ {0x62f0, 0x1032, 0x1903}, {0x9af0, 0x1033, 0x0d00},
+ {0xcff0, 0x1034, 0x80b1}, {0x0ff0, 0x1035, 0x0e27},
+ {0x8ff0, 0x1036, 0x9229}, {0x0ef0, 0x1037, 0x3400},
+ {0xaff0, 0x1038, 0x19f5}, {0x81f0, 0x1039, 0x8229},
+ {0x0ef0, 0x103a, 0x3400}, {0xfff0, 0x103b, 0x19f6},
+ {0x5af0, 0x103c, 0x8234}, {0xeaf0, 0x103d, 0x9113},
+ {0x0ef0, 0x103e, 0x3400}, {0x7ff0, 0x103f, 0x19ea},
+ {0x8af0, 0x1040, 0x924d}, {0x08f0, 0x1041, 0x3400},
+ {0x3ff0, 0x1042, 0x1a74}, {0x00f0, 0x1043, 0x0000},
+ {0x00f0, 0x1044, 0x0000}, {0x00f0, 0x1045, 0x0c38},
+ {0x0ff0, 0x1046, 0x2618}, {0xb0f0, 0x1047, 0x8148},
+ {0x01f0, 0x1048, 0x3700}, {0x02f0, 0x1049, 0x3a70},
+ {0x03f0, 0x104a, 0x3a78}, {0x9af0, 0x104b, 0x8229},
+ {0xd6f0, 0x104c, 0x47c4}, {0x95f0, 0x104d, 0x4361},
+ {0x0ff0, 0x104e, 0x2082}, {0x76f0, 0x104f, 0x626b},
+ {0x0ff0, 0x1050, 0x208a}, {0x0ff0, 0x1051, 0x204a},
+ {0xc9f0, 0x1052, 0x7882}, {0x75f0, 0x1053, 0x626b},
+ {0x0ff0, 0x1054, 0x208a}, {0x0ff0, 0x1055, 0x204a},
+ {0xcdf0, 0x1056, 0x7882}, {0x0ff0, 0x1057, 0x2630},
+ {0x8af0, 0x1058, 0x2b30}, {0xf4f0, 0x1059, 0x1904},
+ {0x98f0, 0x105a, 0x9229}, {0x0ef0, 0x105b, 0x3400},
+ {0xeff0, 0x105c, 0x19fd}, {0xd7f0, 0x105d, 0x40cc},
+ {0x0ef0, 0x105e, 0x3400}, {0xdff0, 0x105f, 0x1a44},
+ {0x00f0, 0x1060, 0x0000}, {0xcef0, 0x1061, 0x1507},
+ {0x90f0, 0x1062, 0x1020}, {0x5ff0, 0x1063, 0x1006},
+ {0x89f0, 0x1064, 0x608f}, {0x0ff0, 0x1065, 0x0e64},
+ {0x49f0, 0x1066, 0x1044}, {0xcff0, 0x1067, 0x2b28},
+ {0x93f0, 0x1068, 0x2a62}, {0x5ff0, 0x1069, 0x266a},
+ {0x54f0, 0x106a, 0x22a8}, {0x0af0, 0x106b, 0x0f22},
+ {0xfbf0, 0x106c, 0x0f0c}, {0x5ff0, 0x106d, 0x0d00},
+ {0x90f0, 0x106e, 0x1020}, {0x4ff0, 0x106f, 0x1006},
+ {0x8df0, 0x1070, 0x6087}, {0x0ff0, 0x1071, 0x0e64},
+ {0xb9f0, 0x1072, 0x1044}, {0xcff0, 0x1073, 0x2a63},
+ {0x5ff0, 0x1074, 0x266a}, {0x54f0, 0x1075, 0x22a8},
+ {0x0af0, 0x1076, 0x0f22}, {0xfbf0, 0x1077, 0x0f0c},
+ {0x93f0, 0x1078, 0x2aef}, {0x0ff0, 0x1079, 0x227a},
+ {0xc2f0, 0x107a, 0x1907}, {0xf5f0, 0x107b, 0x0d00},
+ {0xfdf0, 0x107c, 0x7800}, {0x0ef0, 0x107d, 0x3400},
+ {0xaff0, 0x107e, 0x1899},
+};
+#define RT3261_DSP_PATCH3_NUM \
+ (sizeof(rt3261_dsp_p3_tab) / sizeof(rt3261_dsp_p3_tab[0]))
+
+static const u16 rt3261_dsp_p2_tab[][2] = {
+ {0x3fa1, 0xe7bb}, {0x3fb1, 0x5000}, {0x3fa2, 0xa26b}, {0x3fb2, 0x500e},
+ {0x3fa3, 0xa27c}, {0x3fb3, 0x2282}, {0x3fa4, 0x996e}, {0x3fb4, 0x5019},
+ {0x3fa5, 0x99a2}, {0x3fb5, 0x5021}, {0x3fa6, 0x99ae}, {0x3fb6, 0x5028},
+ {0x3fa7, 0x9cbb}, {0x3fb7, 0x502c}, {0x3fa8, 0x9900}, {0x3fb8, 0x1903},
+ {0x3fa9, 0x9f59}, {0x3fb9, 0x502f}, {0x3faa, 0x9f6e}, {0x3fba, 0x5039},
+ {0x3fab, 0x9ea2}, {0x3fbb, 0x503c}, {0x3fac, 0x9fc8}, {0x3fbc, 0x5045},
+ {0x3fad, 0xa44c}, {0x3fbd, 0x505d}, {0x3fae, 0x8983}, {0x3fbe, 0x5061},
+ {0x3faf, 0x95e3}, {0x3fbf, 0x5006}, {0x3fa0, 0xe742}, {0x3fb0, 0x5040},
+};
+#define RT3261_DSP_PATCH2_NUM \
+ (sizeof(rt3261_dsp_p2_tab) / sizeof(rt3261_dsp_p2_tab[0]))
+
+/**
+ * rt3261_dsp_done - Wait until DSP is ready.
+ * @codec: SoC Audio Codec device.
+ *
+ * To check voice DSP status and confirm it's ready for next work.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_dsp_done(struct snd_soc_codec *codec)
+{
+ unsigned int count = 0, dsp_val;
+
+ dsp_val = snd_soc_read(codec, RT3261_DSP_CTRL3);
+ while(dsp_val & RT3261_DSP_BUSY_MASK) {
+ if(count > 10)
+ return -EBUSY;
+ dsp_val = snd_soc_read(codec, RT3261_DSP_CTRL3);
+ count ++;
+ }
+
+ return 0;
+}
+
+/**
+ * rt3261_dsp_write - Write DSP register.
+ * @codec: SoC audio codec device.
+ * @param: DSP parameters.
+ *
+ * Modify voice DSP register for sound effect. The DSP can be controlled
+ * through DSP command format (0xfc), addr (0xc4), data (0xc5) and cmd (0xc6)
+ * register. It has to wait until the DSP is ready.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_dsp_write(struct snd_soc_codec *codec,
+ struct rt3261_dsp_param *param)
+{
+ unsigned int dsp_val = snd_soc_read(codec, RT3261_DSP_CTRL3);
+ int ret;
+
+ ret = rt3261_dsp_done(codec);
+ if (ret < 0) {
+ dev_err(codec->dev, "DSP is busy: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_write(codec, RT3261_GEN_CTRL3, param->cmd_fmt);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write cmd format: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL1, param->addr);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP addr reg: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL2, param->data);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP data reg: %d\n", ret);
+ goto err;
+ }
+ dsp_val &= ~(RT3261_DSP_R_EN | RT3261_DSP_CMD_MASK);
+ dsp_val |= RT3261_DSP_W_EN | param->cmd;
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL3, dsp_val);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP cmd reg: %d\n", ret);
+ goto err;
+ }
+ mdelay(10);
+ return 0;
+
+err:
+ return ret;
+}
+
+/**
+ * rt3261_dsp_read - Read DSP register.
+ * @codec: SoC audio codec device.
+ * @reg: DSP register index.
+ *
+ * Read DSP setting value from voice DSP. The DSP can be controlled
+ * through DSP addr (0xc4), data (0xc5) and cmd (0xc6) register. Each
+ * command has to wait until the DSP is ready.
+ *
+ * Returns DSP register value or negative error code.
+ */
+static unsigned int rt3261_dsp_read(
+ struct snd_soc_codec *codec, unsigned int reg)
+{
+ unsigned int val_h, val_l, value;
+ unsigned int dsp_val = snd_soc_read(codec, RT3261_DSP_CTRL3);
+ int ret = 0;
+
+ ret = rt3261_dsp_done(codec);
+ if (ret < 0) {
+ dev_err(codec->dev, "DSP is busy: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_write(codec, RT3261_GEN_CTRL3, 0);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write fc = 0: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL1, reg);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP addr reg: %d\n", ret);
+ goto err;
+ }
+ dsp_val &= ~(RT3261_DSP_W_EN | RT3261_DSP_CMD_MASK);
+ dsp_val |= RT3261_DSP_R_EN | RT3261_DSP_CMD_MR;
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL3, dsp_val);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP cmd reg: %d\n", ret);
+ goto err;
+ }
+
+ /* Read DSP high byte data */
+ ret = rt3261_dsp_done(codec);
+ if (ret < 0) {
+ dev_err(codec->dev, "DSP is busy: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL1, RT3261_DSP_REG_DATHI);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP addr reg: %d\n", ret);
+ goto err;
+ }
+ dsp_val &= ~(RT3261_DSP_W_EN | RT3261_DSP_CMD_MASK);
+ dsp_val |= RT3261_DSP_R_EN | RT3261_DSP_CMD_RR;
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL3, dsp_val);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP cmd reg: %d\n", ret);
+ goto err;
+ }
+ ret = rt3261_dsp_done(codec);
+ if (ret < 0) {
+ dev_err(codec->dev, "DSP is busy: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_read(codec, RT3261_DSP_CTRL2);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to read DSP data reg: %d\n", ret);
+ goto err;
+ }
+ val_h = ret;
+
+ /* Read DSP low byte data */
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL1, RT3261_DSP_REG_DATLO);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP addr reg: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_write(codec, RT3261_DSP_CTRL3, dsp_val);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to write DSP cmd reg: %d\n", ret);
+ goto err;
+ }
+ ret = rt3261_dsp_done(codec);
+ if (ret < 0) {
+ dev_err(codec->dev, "DSP is busy: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_read(codec, RT3261_DSP_CTRL2);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to read DSP data reg: %d\n", ret);
+ goto err;
+ }
+ val_l = ret;
+
+ value = ((val_h & 0xff) << 8) |(val_l & 0xff);
+ return value;
+
+err:
+ return ret;
+}
+
+static int rt3261_dsp_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = rt3261->dsp_sw;
+
+ return 0;
+}
+
+static int rt3261_dsp_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ if (rt3261->dsp_sw != ucontrol->value.integer.value[0])
+ rt3261->dsp_sw = ucontrol->value.integer.value[0];
+
+ return 0;
+}
+
+static int rt3261_dsp_play_bp_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = rt3261->dsp_play_pass;
+
+ return 0;
+}
+
+static int rt3261_dsp_play_bp_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ if (rt3261->dsp_play_pass == ucontrol->value.integer.value[0])
+ return 0;
+ rt3261->dsp_play_pass = ucontrol->value.integer.value[0];
+
+ rt3261_conn_mux_path(codec, "DAC L2 Mux",
+ rt3261->dsp_play_pass ? "IF2" : "TxDC");
+ rt3261_conn_mux_path(codec, "DAC R2 Mux",
+ rt3261->dsp_play_pass ? "IF2" : "TxDC");
+
+ return 0;
+}
+
+static int rt3261_dsp_rec_bp_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = rt3261->dsp_rec_pass;
+
+ return 0;
+}
+
+static int rt3261_dsp_rec_bp_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ if (rt3261->dsp_rec_pass == ucontrol->value.integer.value[0])
+ return 0;
+ rt3261->dsp_rec_pass = ucontrol->value.integer.value[0];
+
+ rt3261_conn_mux_path(codec, "IF2 ADC L Mux",
+ rt3261->dsp_rec_pass ? "Mono ADC MIXL" : "TxDP");
+ rt3261_conn_mux_path(codec, "IF2 ADC R Mux",
+ rt3261->dsp_rec_pass ? "Mono ADC MIXR" : "TxDP");
+
+ return 0;
+}
+
+static int rt3261_dac_active_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ struct snd_soc_dapm_widget *w;
+
+ list_for_each_entry(w, &dapm->card->widgets, list)
+ {
+ if (!w->sname || w->dapm != dapm)
+ continue;
+ if (strstr(w->sname, "Playback")) {
+ pr_info("widget %s %s\n", w->name, w->sname);
+ ucontrol->value.integer.value[0] = w->active;
+ break;
+ }
+ }
+ return 0;
+}
+
+static int rt3261_dac_active_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ struct snd_soc_dapm_widget *w;
+
+ list_for_each_entry(w, &dapm->card->widgets, list)
+ {
+ if (!w->sname || w->dapm != dapm)
+ continue;
+ if (strstr(w->sname, "Playback")) {
+ pr_info("widget %s %s\n", w->name, w->sname);
+ w->active = 1;
+ }
+ }
+ return 0;
+}
+
+static int rt3261_adc_active_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ struct snd_soc_dapm_widget *w;
+
+ list_for_each_entry(w, &dapm->card->widgets, list)
+ {
+ if (!w->sname || w->dapm != dapm)
+ continue;
+ if (strstr(w->sname, "Capture")) {
+ pr_info("widget %s %s\n", w->name, w->sname);
+ ucontrol->value.integer.value[0] = w->active;
+ break;
+ }
+ }
+ return 0;
+}
+
+static int rt3261_adc_active_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ struct snd_soc_dapm_widget *w;
+
+ list_for_each_entry(w, &dapm->card->widgets, list)
+ {
+ if (!w->sname || w->dapm != dapm)
+ continue;
+ if (strstr(w->sname, "Capture")) {
+ pr_info("widget %s %s\n", w->name, w->sname);
+ w->active = 1;
+ }
+ }
+ return 0;
+}
+
+/* DSP Path Control 1 */
+static const char *rt3261_src_rxdp_mode[] = {
+ "Normal", "Divided by 3"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_src_rxdp_enum, RT3261_DSP_PATH1,
+ RT3261_RXDP_SRC_SFT, rt3261_src_rxdp_mode);
+
+static const char *rt3261_src_txdp_mode[] = {
+ "Normal", "Multiplied by 3"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_src_txdp_enum, RT3261_DSP_PATH1,
+ RT3261_TXDP_SRC_SFT, rt3261_src_txdp_mode);
+
+/* DSP data select */
+static const char *rt3261_dsp_data_select[] = {
+ "Normal", "left copy to right", "right copy to left", "Swap"};
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_rxdc_data_enum, RT3261_DSP_PATH2,
+ RT3261_RXDC_SEL_SFT, rt3261_dsp_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp_data_enum, RT3261_DSP_PATH2,
+ RT3261_RXDP_SEL_SFT, rt3261_dsp_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_txdc_data_enum, RT3261_DSP_PATH2,
+ RT3261_TXDC_SEL_SFT, rt3261_dsp_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_txdp_data_enum, RT3261_DSP_PATH2,
+ RT3261_TXDP_SEL_SFT, rt3261_dsp_data_select);
+
+/* Sound Effect */
+static const char *rt3261_dsp_mode[] = {
+ "Disable", "AEC+NS+FENS", "HFBF", "Far Field Pick-up"};
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_dsp_enum, 0, 0, rt3261_dsp_mode);
+
+static const char *rt3261_rxdp2_src[] =
+ {"IF2_DAC", "Stereo_ADC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_rxdp2_enum, RT3261_GEN_CTRL2,
+ RT3261_RXDP2_SEL_SFT, rt3261_rxdp2_src);
+
+static const struct snd_kcontrol_new rt3261_rxdp2_mux =
+ SOC_DAPM_ENUM("RxDP2 sel", rt3261_rxdp2_enum);
+
+static const char *rt3261_rxdp_src[] =
+ {"RxDP2", "RxDP1"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_rxdp_enum, RT3261_DUMMY_PR3F,
+ 10, rt3261_rxdp_src);
+
+static const struct snd_kcontrol_new rt3261_rxdp_mux =
+ SOC_DAPM_ENUM("RxDP sel", rt3261_rxdp_enum);
+
+static const char *rt3261_rxdc_src[] =
+ {"Mono_ADC", "Stereo_ADC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_rxdc_enum, RT3261_GEN_CTRL2,
+ RT3261_RXDC_SRC_SFT, rt3261_rxdc_src);
+
+static const struct snd_kcontrol_new rt3261_rxdc_mux =
+ SOC_DAPM_ENUM("RxDC sel", rt3261_rxdc_enum);
+
+static const char *rt3261_rxdp1_src[] =
+ {"DAC1", "IF1_DAC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_rxdp1_enum, RT3261_DUMMY_PR3F,
+ 9, rt3261_rxdp1_src);
+
+static const struct snd_kcontrol_new rt3261_rxdp1_mux =
+ SOC_DAPM_ENUM("RxDP1 sel", rt3261_rxdp1_enum);
+
+static const struct snd_kcontrol_new rt3261_dsp_snd_controls[] = {
+ SOC_ENUM("RxDC input data", rt3261_rxdc_data_enum),
+ SOC_ENUM("RxDP input data", rt3261_rxdp_data_enum),
+ SOC_ENUM("TxDC input data", rt3261_txdc_data_enum),
+ SOC_ENUM("TxDP input data", rt3261_txdp_data_enum),
+ SOC_ENUM("SRC for RxDP", rt3261_src_rxdp_enum),
+ SOC_ENUM("SRC for TxDP", rt3261_src_txdp_enum),
+ /* AEC */
+ SOC_ENUM_EXT("DSP Function Switch", rt3261_dsp_enum,
+ rt3261_dsp_get, rt3261_dsp_put),
+ SOC_SINGLE_EXT("DSP Playback Bypass", 0, 0, 1, 0,
+ rt3261_dsp_play_bp_get, rt3261_dsp_play_bp_put),
+ SOC_SINGLE_EXT("DSP Record Bypass", 0, 0, 1, 0,
+ rt3261_dsp_rec_bp_get, rt3261_dsp_rec_bp_put),
+ SOC_SINGLE_EXT("DAC Switch", 0, 0, 1, 0,
+ rt3261_dac_active_get, rt3261_dac_active_put),
+ SOC_SINGLE_EXT("ADC Switch", 0, 0, 1, 0,
+ rt3261_adc_active_get, rt3261_adc_active_put),
+};
+
+static int rt3261_dsp_patch_3(struct snd_soc_codec *codec)
+{
+ struct rt3261_dsp_param param;
+ int ret, i;
+
+ param.cmd_fmt = 0x0090;
+ param.addr = 0x0064;
+ param.data = 0x0004;
+ param.cmd = RT3261_DSP_CMD_RW;
+ ret = rt3261_dsp_write(codec, ¶m);
+ if (ret < 0) {
+ dev_err(codec->dev,
+ "Fail to set DSP 3 bytes patch entrance: %d\n", ret);
+ goto patch_err;
+ }
+
+ param.cmd = RT3261_DSP_CMD_PE;
+ for(i = 0; i < RT3261_DSP_PATCH3_NUM; i++) {
+ param.cmd_fmt = rt3261_dsp_p3_tab[i][0];
+ param.addr = rt3261_dsp_p3_tab[i][1];
+ param.data = rt3261_dsp_p3_tab[i][2];
+ ret = rt3261_dsp_write(codec, ¶m);
+ if (ret < 0) {
+ dev_err(codec->dev, "Fail to patch Dsp: %d\n", ret);
+ goto patch_err;
+ }
+ }
+
+ return 0;
+
+patch_err:
+
+ return ret;
+}
+
+static int rt3261_dsp_patch_2(struct snd_soc_codec *codec)
+{
+ struct rt3261_dsp_param param;
+ int ret, i;
+
+ param.cmd_fmt = 0x0090;
+ param.addr = 0x0064;
+ param.data = 0x0000;
+ param.cmd = RT3261_DSP_CMD_RW;
+ ret = rt3261_dsp_write(codec, ¶m);
+ if (ret < 0) {
+ dev_err(codec->dev,
+ "Fail to set DSP 2 bytes patch entrance: %d\n", ret);
+ goto patch_err;
+ }
+
+ param.cmd_fmt = 0x00e0;
+ param.cmd = RT3261_DSP_CMD_MW;
+ for(i = 0; i < RT3261_DSP_PATCH2_NUM; i++) {
+ param.addr = rt3261_dsp_p2_tab[i][0];
+ param.data = rt3261_dsp_p2_tab[i][1];
+ ret = rt3261_dsp_write(codec, ¶m);
+ if (ret < 0) {
+ dev_err(codec->dev, "Fail to patch Dsp: %d\n", ret);
+ goto patch_err;
+ }
+ }
+
+ return 0;
+
+patch_err:
+
+ return ret;
+}
+
+/**
+ * rt3261_dsp_patch - Write DSP patch code.
+ *
+ * @codec: SoC audio codec device.
+ *
+ * Write patch codes to DSP including 3 and 2 bytes data.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_dsp_patch(struct snd_soc_codec *codec)
+{
+ int ret;
+
+ dev_dbg(codec->dev, "\n DSP Patch Start ......\n");
+
+ ret = snd_soc_update_bits(codec, RT3261_MICBIAS,
+ RT3261_PWR_CLK25M_MASK, RT3261_PWR_CLK25M_PU);
+ if (ret < 0)
+ goto patch_err;
+
+ ret = snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_SCLK_SRC_MASK, RT3261_SCLK_SRC_RCCLK);
+ if (ret < 0)
+ goto patch_err;
+
+ ret = snd_soc_update_bits(codec, RT3261_PWR_DIG2,
+ RT3261_PWR_I2S_DSP, RT3261_PWR_I2S_DSP);
+ if (ret < 0)
+ goto patch_err;
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_PD_PIN_MASK, RT3261_DSP_PD_PIN_HI);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to power up DSP: %d\n", ret);
+ goto patch_err;
+ }
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_RST_PIN_MASK, RT3261_DSP_RST_PIN_LO);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
+ goto patch_err;
+ }
+
+ mdelay(10);
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_RST_PIN_MASK, RT3261_DSP_RST_PIN_HI);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to recover DSP: %d\n", ret);
+ goto patch_err;
+ }
+
+ ret = rt3261_dsp_patch_3(codec);
+ if (ret < 0)
+ goto patch_err;
+
+ ret = rt3261_dsp_patch_2(codec);
+ if (ret < 0)
+ goto patch_err;
+
+ return 0;
+
+patch_err:
+
+ return ret;
+}
+
+static void rt3261_do_dsp_patch(struct work_struct *work)
+{
+ struct rt3261_priv *rt3261 =
+ container_of(work, struct rt3261_priv, patch_work.work);
+ struct snd_soc_codec *codec = rt3261->codec;
+
+ if (rt3261_dsp_patch(codec) < 0)
+ dev_err(codec->dev, "Patch DSP rom code Fail !!!\n");
+}
+
+
+/**
+ * rt3261_dsp_conf - Set DSP basic setting.
+ *
+ * @codec: SoC audio codec device.
+ *
+ * Set parameters of basic setting to DSP.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_dsp_conf(struct snd_soc_codec *codec)
+{
+ struct rt3261_dsp_param param;
+ int ret, i;
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_PD_PIN_MASK, RT3261_DSP_PD_PIN_HI);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to power up DSP: %d\n", ret);
+ goto conf_err;
+ }
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_RST_PIN_MASK, RT3261_DSP_RST_PIN_LO);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
+ goto conf_err;
+ }
+
+ mdelay(10);
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_RST_PIN_MASK | RT3261_DSP_CLK_MASK,
+ RT3261_DSP_RST_PIN_HI | RT3261_DSP_CLK_384K);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to recover DSP: %d\n", ret);
+ goto conf_err;
+ }
+
+ param.cmd_fmt = 0x00e0;
+ param.cmd = RT3261_DSP_CMD_MW;
+ for(i = 0; i < RT3261_DSP_INIT_NUM; i++) {
+ param.addr = rt3261_dsp_init[i][0];
+ param.data = rt3261_dsp_init[i][1];
+ ret = rt3261_dsp_write(codec, ¶m);
+ if (ret < 0) {
+ dev_err(codec->dev, "Fail to config Dsp: %d\n", ret);
+ goto conf_err;
+ }
+ }
+
+ return 0;
+
+conf_err:
+
+ return ret;
+}
+
+/**
+ * rt3261_dsp_rate - Set DSP rate setting.
+ *
+ * @codec: SoC audio codec device.
+ * @rate: Sampling rate.
+ *
+ * Set parameters of sampling rate to DSP.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_dsp_rate(struct snd_soc_codec *codec, int rate)
+{
+ struct rt3261_dsp_param param;
+ int ret, i, tab_num;
+ unsigned short (*rate_tab)[2];
+
+ if (rate != 48000 && rate != 44100 && rate != 16000)
+ return -EINVAL;
+
+ if (rate > 44100) {
+ rate_tab = rt3261_dsp_48;
+ tab_num = RT3261_DSP_48_NUM;
+ } else {
+ if (rate > 16000) {
+ rate_tab = rt3261_dsp_441;
+ tab_num = RT3261_DSP_441_NUM;
+ } else {
+ rate_tab = rt3261_dsp_16;
+ tab_num = RT3261_DSP_16_NUM;
+ }
+ }
+
+ param.cmd_fmt = 0x00e0;
+ param.cmd = RT3261_DSP_CMD_MW;
+ for (i = 0; i < tab_num; i++) {
+ param.addr = rate_tab[i][0];
+ param.data = rate_tab[i][1];
+ ret = rt3261_dsp_write(codec, ¶m);
+ if (ret < 0)
+ goto rate_err;
+ }
+
+ return 0;
+
+rate_err:
+
+ dev_err(codec->dev, "Fail to set rate %d parameters: %d\n", rate, ret);
+ return ret;
+}
+
+/**
+ * rt3261_dsp_set_mode - Set DSP mode parameters.
+ *
+ * @codec: SoC audio codec device.
+ * @mode: DSP mode.
+ *
+ * Set parameters of mode to DSP.
+ * There are three modes which includes " mic AEC + NS + FENS",
+ * "HFBF" and "Far-field pickup".
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_dsp_set_mode(struct snd_soc_codec *codec, int mode)
+{
+ struct rt3261_dsp_param param;
+ int ret, i, tab_num;
+ unsigned short (*mode_tab)[2];
+
+ switch (mode) {
+ case RT3261_DSP_AEC_NS_FENS:
+ dev_info(codec->dev, "AEC\n");
+ mode_tab = rt3261_dsp_aec_ns_fens;
+ tab_num = RT3261_DSP_AEC_NUM;
+ break;
+
+ case RT3261_DSP_HFBF:
+ dev_info(codec->dev, "Beamforming\n");
+ mode_tab = rt3261_dsp_hfbf;
+ tab_num = RT3261_DSP_HFBF_NUM;
+ break;
+
+ case RT3261_DSP_FFP:
+ dev_info(codec->dev, "Far Field Pick-up\n");
+ mode_tab = rt3261_dsp_ffp;
+ tab_num = RT3261_DSP_FFP_NUM;
+ break;
+
+ case RT3261_DSP_DIS:
+ default:
+ dev_info(codec->dev, "Disable\n");
+ return 0;
+ }
+
+ param.cmd_fmt = 0x00e0;
+ param.cmd = RT3261_DSP_CMD_MW;
+ for (i = 0; i < tab_num; i++) {
+ param.addr = mode_tab[i][0];
+ param.data = mode_tab[i][1];
+ ret = rt3261_dsp_write(codec, ¶m);
+ if (ret < 0)
+ goto mode_err;
+ }
+
+ return 0;
+
+mode_err:
+
+ dev_err(codec->dev, "Fail to set mode %d parameters: %d\n", mode, ret);
+ return ret;
+}
+
+/**
+ * rt3261_dsp_snd_effect - Set DSP sound effect.
+ *
+ * Set parameters of sound effect to DSP.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_dsp_snd_effect(struct snd_soc_codec *codec)
+{
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ int ret;
+
+ ret = rt3261_dsp_conf(codec);
+ if (ret < 0)
+ goto effect_err;
+
+ ret = rt3261_dsp_rate(codec, rt3261->lrck[rt3261->aif_pu] ?
+ rt3261->lrck[rt3261->aif_pu] : 44100);
+ if (ret < 0)
+ goto effect_err;
+
+ ret = rt3261_dsp_set_mode(codec, rt3261->dsp_sw);
+ if (ret < 0)
+ goto effect_err;
+
+ mdelay(20);
+
+ return 0;
+
+effect_err:
+
+ return ret;
+}
+
+static int rt3261_dsp_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *k, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ static unsigned int power_on;
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMD:
+ pr_info("%s(): PMD\n", __func__);
+ if (!power_on)
+ return 0;
+
+ power_on--;
+ if (!power_on) {
+ snd_soc_update_bits(codec, RT3261_PWR_DIG2,
+ RT3261_PWR_I2S_DSP, 0);
+ snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_PD_PIN_MASK, RT3261_DSP_PD_PIN_LO);
+ }
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+ pr_info("%s(): PMU\n", __func__);
+ if (rt3261->dsp_sw == RT3261_DSP_DIS || 2 <= power_on)
+ return 0;
+
+ if (!power_on) {
+ snd_soc_update_bits(codec, RT3261_PWR_DIG2,
+ RT3261_PWR_I2S_DSP, RT3261_PWR_I2S_DSP);
+ rt3261_dsp_snd_effect(codec);
+ }
+ power_on++;
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int rt3261_pr3f_sync_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ unsigned int ret, tmp;
+ printk("enter %s\n",__func__);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ tmp = snd_soc_read(codec,RT3261_DUMMY_PR3F);
+ printk("snd_soc_read(codec,RT3261_DUMMY_PR3F)=0x%x\n",tmp);
+ ret = snd_soc_write(codec, RT3261_PRIV_INDEX, RT3261_MIXER_INT_REG);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+ return ret;;
+ }
+ ret = snd_soc_write(codec, RT3261_PRIV_DATA, tmp);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set private value: %d\n", ret);
+ return ret;
+ }
+
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget rt3261_dsp_dapm_widgets[] = {
+ SND_SOC_DAPM_PGA_E("DSP Downstream", SND_SOC_NOPM,
+ 0, 0, NULL, 0, rt3261_dsp_event,
+ SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_PGA_E("DSP Upstream", SND_SOC_NOPM,
+ 0, 0, NULL, 0, rt3261_dsp_event,
+ SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MUX_E("RxDP Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_rxdp_mux, rt3261_pr3f_sync_event,
+ SND_SOC_DAPM_PRE_PMU),
+ SND_SOC_DAPM_MUX("RxDP2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_rxdp2_mux),
+ SND_SOC_DAPM_MUX_E("RxDP1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_rxdp1_mux, rt3261_pr3f_sync_event,
+ SND_SOC_DAPM_PRE_PMU),
+ SND_SOC_DAPM_MUX("RxDC Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_rxdc_mux),
+ SND_SOC_DAPM_PGA("RxDP", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("RxDC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("TxDC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("TxDP", SND_SOC_NOPM, 0, 0, NULL, 0),
+};
+
+static const struct snd_soc_dapm_route rt3261_dsp_dapm_routes[] = {
+ {"RxDC", NULL, "RxDC Mux"},
+ {"RxDC Mux", "Mono_ADC", "Mono ADC MIXL"},
+ {"RxDC Mux", "Mono_ADC", "Mono ADC MIXR"},
+ {"RxDC Mux", "Stereo_ADC", "Stereo ADC MIXL"},
+ {"RxDC Mux", "Stereo_ADC", "Stereo ADC MIXR"},
+ {"RxDP", NULL, "RxDP Mux"},
+ {"RxDP Mux", "RxDP2", "RxDP2 Mux"},
+ {"RxDP Mux", "RxDP1", "RxDP1 Mux"},
+ {"RxDP2 Mux", "IF2_DAC", "IF2 DAC L"},
+ {"RxDP2 Mux", "IF2_DAC", "IF2 DAC R"},
+ {"RxDP2 Mux", "Stereo_ADC", "Stereo ADC MIXL"},
+ {"RxDP2 Mux", "Stereo_ADC", "Stereo ADC MIXR"},
+ {"RxDP1 Mux", "DAC1", "Stereo DAC MIXL"},
+ {"RxDP1 Mux", "DAC1", "Stereo DAC MIXR"},
+ {"RxDP1 Mux", "IF1_DAC", "IF1 DAC L"},
+ {"RxDP1 Mux", "IF1_DAC", "IF1 DAC R"},
+
+ {"DSP Downstream", NULL, "RxDP"},
+ {"TxDC", NULL, "DSP Downstream"},
+ {"DSP Upstream", NULL, "RxDC"},
+ {"TxDP", NULL, "DSP Upstream"},
+
+ {"IF2 ADC L Mux", "TxDP", "TxDP"},
+ {"IF2 ADC R Mux", "TxDP", "TxDP"},
+ {"DAC L2 Mux", "TxDC", "TxDC"},
+ {"DAC R2 Mux", "TxDC", "TxDC"},
+};
+
+/**
+ * rt3261_dsp_show - Dump DSP registers.
+ * @dev: codec device.
+ * @attr: device attribute.
+ * @buf: buffer for display.
+ *
+ * To show non-zero values of all DSP registers.
+ *
+ * Returns buffer length.
+ */
+static ssize_t rt3261_dsp_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
+ struct snd_soc_codec *codec = rt3261->codec;
+ unsigned short (*rt3261_dsp_tab)[2];
+ unsigned int val;
+ int cnt = 0, i, tab_num;
+
+ switch (rt3261->dsp_sw) {
+ case RT3261_DSP_AEC_NS_FENS:
+ cnt += sprintf(buf, "[ RT3261 DSP 'AEC' ]\n");
+ rt3261_dsp_tab = rt3261_dsp_aec_ns_fens;
+ tab_num = RT3261_DSP_AEC_NUM;
+ break;
+
+ case RT3261_DSP_HFBF:
+ cnt += sprintf(buf, "[ RT3261 DSP 'Beamforming' ]\n");
+ rt3261_dsp_tab = rt3261_dsp_hfbf;
+ tab_num = RT3261_DSP_HFBF_NUM;
+ break;
+
+ case RT3261_DSP_FFP:
+ cnt += sprintf(buf, "[ RT3261 DSP 'Far Field Pick-up' ]\n");
+ rt3261_dsp_tab = rt3261_dsp_ffp;
+ tab_num = RT3261_DSP_FFP_NUM;
+ break;
+
+ case RT3261_DSP_DIS:
+ default:
+ cnt += sprintf(buf, "RT3261 DSP Disabled\n");
+ goto dsp_done;
+ }
+
+ for (i = 0; i < tab_num; i++) {
+ if (cnt + RT3261_DSP_REG_DISP_LEN >= PAGE_SIZE)
+ break;
+ val = rt3261_dsp_read(codec, rt3261_dsp_tab[i][0]);
+ if (!val)
+ continue;
+ cnt += snprintf(buf + cnt, RT3261_DSP_REG_DISP_LEN,
+ "%04x: %04x\n", rt3261_dsp_tab[i][0], val);
+ }
+
+dsp_done:
+
+ if (cnt >= PAGE_SIZE)
+ cnt = PAGE_SIZE - 1;
+
+ return cnt;
+}
+static DEVICE_ATTR(dsp_reg, 0444, rt3261_dsp_show, NULL);
+
+/**
+ * rt3261_dsp_probe - register DSP for rt3261
+ * @codec: audio codec
+ *
+ * To register DSP function for rt3261.
+ *
+ * Returns 0 for success or negative error code.
+ */
+int rt3261_dsp_probe(struct snd_soc_codec *codec)
+{
+ struct rt3261_priv *rt3261;
+ int ret;
+
+ if (codec == NULL)
+ return -EINVAL;
+
+ snd_soc_add_controls(codec, rt3261_dsp_snd_controls,
+ ARRAY_SIZE(rt3261_dsp_snd_controls));
+ snd_soc_dapm_new_controls(&codec->dapm, rt3261_dsp_dapm_widgets,
+ ARRAY_SIZE(rt3261_dsp_dapm_widgets));
+ snd_soc_dapm_add_routes(&codec->dapm, rt3261_dsp_dapm_routes,
+ ARRAY_SIZE(rt3261_dsp_dapm_routes));
+
+ /* Patch DSP rom code if IC version is larger than C version */
+
+ ret = snd_soc_update_bits(codec, RT3261_PWR_DIG2,
+ RT3261_PWR_I2S_DSP, RT3261_PWR_I2S_DSP);
+ if (ret < 0) {
+ dev_err(codec->dev,
+ "Failed to power up DSP IIS interface: %d\n", ret);
+ }
+
+ rt3261_dsp_conf(codec);
+ ret = rt3261_dsp_read(codec, 0x3800);
+ pr_info("DSP version code = 0x%04x\n",ret);
+ if(ret != 0x501a) {
+ rt3261 = snd_soc_codec_get_drvdata(codec);
+ INIT_DELAYED_WORK(&rt3261->patch_work, rt3261_do_dsp_patch);
+ schedule_delayed_work(&rt3261->patch_work,
+ msecs_to_jiffies(100));
+ }
+ snd_soc_update_bits(codec, RT3261_PWR_DIG2,
+ RT3261_PWR_I2S_DSP, 0);
+
+ ret = device_create_file(codec->dev, &dev_attr_dsp_reg);
+ if (ret != 0) {
+ dev_err(codec->dev,
+ "Failed to create index_reg sysfs files: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(rt3261_dsp_probe);
+
+int do_rt3261_dsp_set_mode(struct snd_soc_codec *codec, int mode) {
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ dev_dbg(codec->dev, "%s mode=%d\n",__func__,mode);
+ if(rt3261->dsp_sw == mode)
+ return 0;
+ rt3261->dsp_sw = mode;
+ if(rt3261->dsp_sw == RT3261_DSP_DIS)
+ rt3261->dsp_play_pass = rt3261->dsp_rec_pass = 1;
+ else
+ rt3261->dsp_play_pass = rt3261->dsp_rec_pass = 0;
+ rt3261_conn_mux_path(codec, "DAC L2 Mux",
+ rt3261->dsp_play_pass ? "IF2" : "TxDC");
+ rt3261_conn_mux_path(codec, "DAC R2 Mux",
+ rt3261->dsp_play_pass ? "IF2" : "TxDC");
+ rt3261_conn_mux_path(codec, "IF2 ADC L Mux",
+ rt3261->dsp_rec_pass ? "Mono ADC MIXL" : "TxDP");
+ rt3261_conn_mux_path(codec, "IF2 ADC R Mux",
+ rt3261->dsp_rec_pass ? "Mono ADC MIXR" : "TxDP");
+
+ if(rt3261->dsp_sw != RT3261_DSP_DIS)
+ rt3261_dsp_snd_effect(codec);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(do_rt3261_dsp_set_mode);
+
+#ifdef RTK_IOCTL
+int rt_codec_dsp_ioctl_common(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct rt_codec_cmd rt_codec;
+ int *buf;
+ int *p;
+ int ret;
+ struct rt3261_dsp_param param;
+
+ //int mask1 = 0, mask2 = 0;
+
+ struct rt_codec_cmd __user *_rt_codec = (struct rt_codec_cmd *)arg;
+ struct snd_soc_codec *codec = hw->private_data;
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec))) {
+ dev_err(codec->dev, "copy_from_user faild\n");
+ return -EFAULT;
+ }
+ dev_dbg(codec->dev, "rt_codec.number=%d\n",rt_codec.number);
+ buf = kmalloc(sizeof(*buf) * rt_codec.number, GFP_KERNEL);
+ if (buf == NULL)
+ return -ENOMEM;
+ if (copy_from_user(buf, rt_codec.buf, sizeof(*buf) * rt_codec.number)) {
+ goto err;
+ }
+
+ ret = snd_soc_update_bits(codec, RT3261_PWR_DIG2,
+ RT3261_PWR_I2S_DSP, RT3261_PWR_I2S_DSP);
+ if (ret < 0) {
+ dev_err(codec->dev,
+ "Failed to power up DSP IIS interface: %d\n", ret);
+ goto err;
+ }
+
+ switch (cmd) {
+ case RT_READ_CODEC_DSP_IOCTL:
+ for (p = buf; p < buf + rt_codec.number/2; p++)
+ *(p+rt_codec.number/2) = rt3261_dsp_read(codec, *p);
+ if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_WRITE_CODEC_DSP_IOCTL:
+ param.cmd_fmt = 0x00e0;
+ param.cmd = RT3261_DSP_CMD_MW;
+ p = buf;
+ param.addr = *p;
+ param.data = *(p+rt_codec.number/2);
+ if(codec == NULL) {
+ dev_dbg(codec->dev, "codec is null\n");
+ break;
+ }
+ for (p = buf; p < buf + rt_codec.number/2; p++)
+ rt3261_dsp_write(codec, ¶m);
+ break;
+
+ case RT_GET_CODEC_DSP_MODE_IOCTL:
+ *buf = rt3261->dsp_sw;
+ if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ default:
+ dev_info(codec->dev, "unsported dsp command\n");
+ break;
+ }
+
+ kfree(buf);
+ return 0;
+
+err:
+ kfree(buf);
+ return -EFAULT;
+}
+EXPORT_SYMBOL_GPL(rt_codec_dsp_ioctl_common);
+#endif
+
+#ifdef CONFIG_PM
+int rt3261_dsp_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+ struct rt3261_dsp_param param;
+ int ret;
+
+ if (RT3261_VER_C == snd_soc_read(codec, RT3261_VENDOR_ID))
+ return 0;
+
+ ret = snd_soc_update_bits(codec, RT3261_PWR_DIG2,
+ RT3261_PWR_I2S_DSP, RT3261_PWR_I2S_DSP);
+ if (ret < 0) {
+ dev_err(codec->dev,
+ "Failed to power up DSP IIS interface: %d\n", ret);
+ goto rsm_err;
+ }
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_PD_PIN_MASK, RT3261_DSP_PD_PIN_HI);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to power up DSP: %d\n", ret);
+ goto rsm_err;
+ }
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_RST_PIN_MASK, RT3261_DSP_RST_PIN_LO);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
+ goto rsm_err;
+ }
+
+ mdelay(10);
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_RST_PIN_MASK, RT3261_DSP_RST_PIN_HI);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to recover DSP: %d\n", ret);
+ goto rsm_err;
+ }
+
+ param.cmd_fmt = 0x00e0;
+ param.addr = 0x3fd2;
+ param.data = 0x0030;
+ param.cmd = RT3261_DSP_CMD_MW;
+ ret = rt3261_dsp_write(codec, ¶m);
+ if (ret < 0) {
+ dev_err(codec->dev,
+ "Failed to Power up LDO of Dsp: %d\n", ret);
+ goto rsm_err;
+ }
+
+ ret = snd_soc_update_bits(codec, RT3261_DSP_CTRL3,
+ RT3261_DSP_PD_PIN_MASK, RT3261_DSP_PD_PIN_LO);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to power down DSP: %d\n", ret);
+ goto rsm_err;
+ }
+
+ return 0;
+
+rsm_err:
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(rt3261_dsp_suspend);
+
+int rt3261_dsp_resume(struct snd_soc_codec *codec)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(rt3261_dsp_resume);
+#endif
+
--- /dev/null
+/*
+ * rt3261-dsp.h -- RT3261 ALSA SoC DSP driver
+ *
+ * Copyright 2011 Realtek Microelectronics
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT3261_DSP_H__
+#define __RT3261_DSP_H__
+
+/* Debug String Length */
+#define RT3261_DSP_REG_DISP_LEN 12
+
+enum {
+ RT3261_DSP_DIS,
+ RT3261_DSP_AEC_NS_FENS,
+ RT3261_DSP_HFBF,
+ RT3261_DSP_FFP,
+};
+
+struct rt3261_dsp_param {
+ u16 cmd_fmt;
+ u16 addr;
+ u16 data;
+ u8 cmd;
+};
+
+int rt3261_dsp_probe(struct snd_soc_codec *codec);
+#ifdef CONFIG_PM
+int rt3261_dsp_suspend(struct snd_soc_codec *codec, pm_message_t state);
+int rt3261_dsp_resume(struct snd_soc_codec *codec);
+#endif
+
+#endif /* __RT3261_DSP_H__ */
+
--- /dev/null
+/*
+ * rt3261.c -- RT3261 ALSA SoC audio codec driver
+ *
+ * Copyright 2011 Realtek Semiconductor Corp.
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+
+#define RT3261_PROC
+#ifdef RT3261_PROC
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/vmalloc.h>
+char debug_write_read = 0;
+#endif
+
+static struct snd_soc_codec *rt3261_codec;
+
+#if 1
+#define DBG(x...) printk(KERN_INFO x)
+#else
+#define DBG(x...)
+#endif
+
+//#define RTK_IOCTL
+#ifdef RTK_IOCTL
+#if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
+#include "rt_codec_ioctl.h"
+#include "rt3261_ioctl.h"
+#endif
+#endif
+
+#include "rt3261.h"
+#if (CONFIG_SND_SOC_RT3261_MODULE | CONFIG_SND_SOC_RT3261)
+#include "rt3261-dsp.h"
+#endif
+
+#define RT3261_REG_RW 1 /* for debug */
+#define RT3261_DET_EXT_MIC 0
+
+#define VERSION "0.3.0 alsa 1.0.24"
+
+struct rt3261_init_reg {
+ u8 reg;
+ u16 val;
+};
+
+static struct rt3261_init_reg init_list[] = {
+ {RT3261_GEN_CTRL1 , 0x3701},//fa[12:13] = 1'b; fa[8~10]=1; fa[0]=1
+ {RT3261_ADDA_CLK1 , 0x1114},//73[2] = 1'b
+ {RT3261_MICBIAS , 0x3030},//93[5:4] = 11'b
+ {RT3261_CLS_D_OUT , 0xa000},//8d[11] = 0'b
+ {RT3261_PRIV_INDEX , 0x003d},//PR3d[12] = 0'b; PR3d[9] = 1'b
+ {RT3261_PRIV_DATA , 0x2600},
+ {RT3261_PRIV_INDEX , 0x0012},//PR12 = 0aa8'h
+ {RT3261_PRIV_DATA , 0x0aa8},
+ {RT3261_PRIV_INDEX , 0x0014},//PR14 = 8aaa'h
+ {RT3261_PRIV_DATA , 0x8aaa},
+ {RT3261_PRIV_INDEX , 0x0020},//PR20 = 6115'h
+ {RT3261_PRIV_DATA , 0x6115},
+ {RT3261_PRIV_INDEX , 0x0023},//PR23 = 0804'h
+ {RT3261_PRIV_DATA , 0x0804},
+ {RT3261_SPK_VOL , 0x8b8b},//SPKMIX -> SPKVOL
+ {RT3261_HP_VOL , 0x8888},
+};
+#define RT3261_INIT_REG_LEN ARRAY_SIZE(init_list)
+
+static int rt3261_reg_init(struct snd_soc_codec *codec)
+{
+ int i;
+
+ for (i = 0; i < RT3261_INIT_REG_LEN; i++)
+ snd_soc_write(codec, init_list[i].reg, init_list[i].val);
+
+ return 0;
+}
+
+static int rt3261_index_sync(struct snd_soc_codec *codec)
+{
+ int i;
+
+ for (i = 0; i < RT3261_INIT_REG_LEN; i++)
+ if (RT3261_PRIV_INDEX == init_list[i].reg ||
+ RT3261_PRIV_DATA == init_list[i].reg)
+ snd_soc_write(codec, init_list[i].reg,
+ init_list[i].val);
+ return 0;
+}
+
+static const u16 rt3261_reg[RT3261_VENDOR_ID2 + 1] = {
+ [RT3261_RESET] = 0x000c,
+ [RT3261_SPK_VOL] = 0xc8c8,
+ [RT3261_HP_VOL] = 0xc8c8,
+ [RT3261_OUTPUT] = 0xc8c8,
+ [RT3261_MONO_OUT] = 0x8000,
+ [RT3261_INL_INR_VOL] = 0x0808,
+ [RT3261_DAC1_DIG_VOL] = 0xafaf,
+ [RT3261_DAC2_DIG_VOL] = 0xafaf,
+ [RT3261_ADC_DIG_VOL] = 0x2f2f,
+ [RT3261_ADC_DATA] = 0x2f2f,
+ [RT3261_STO_ADC_MIXER] = 0x7060,
+ [RT3261_MONO_ADC_MIXER] = 0x7070,
+ [RT3261_AD_DA_MIXER] = 0x8080,
+ [RT3261_STO_DAC_MIXER] = 0x5454,
+ [RT3261_MONO_DAC_MIXER] = 0x5454,
+ [RT3261_DIG_MIXER] = 0xaa00,
+ [RT3261_DSP_PATH2] = 0xa000,
+ [RT3261_REC_L2_MIXER] = 0x007f,
+ [RT3261_REC_R2_MIXER] = 0x007f,
+ [RT3261_HPO_MIXER] = 0xe000,
+ [RT3261_SPK_L_MIXER] = 0x003e,
+ [RT3261_SPK_R_MIXER] = 0x003e,
+ [RT3261_SPO_L_MIXER] = 0xf800,
+ [RT3261_SPO_R_MIXER] = 0x3800,
+ [RT3261_SPO_CLSD_RATIO] = 0x0004,
+ [RT3261_MONO_MIXER] = 0xfc00,
+ [RT3261_OUT_L3_MIXER] = 0x01ff,
+ [RT3261_OUT_R3_MIXER] = 0x01ff,
+ [RT3261_LOUT_MIXER] = 0xf000,
+ [RT3261_PWR_ANLG1] = 0x00c0,
+ [RT3261_I2S1_SDP] = 0x8000,
+ [RT3261_I2S2_SDP] = 0x8000,
+ [RT3261_I2S3_SDP] = 0x8000,
+ [RT3261_ADDA_CLK1] = 0x1110,
+ [RT3261_ADDA_CLK2] = 0x0c00,
+ [RT3261_DMIC] = 0x1d00,
+ [RT3261_ASRC_3] = 0x0008,
+ [RT3261_HP_OVCD] = 0x0600,
+ [RT3261_CLS_D_OVCD] = 0x0228,
+ [RT3261_CLS_D_OUT] = 0xa800,
+ [RT3261_DEPOP_M1] = 0x0004,
+ [RT3261_DEPOP_M2] = 0x1100,
+ [RT3261_DEPOP_M3] = 0x0646,
+ [RT3261_CHARGE_PUMP] = 0x0c00,
+ [RT3261_MICBIAS] = 0x3000,
+ [RT3261_EQ_CTRL1] = 0x2080,
+ [RT3261_DRC_AGC_1] = 0x2206,
+ [RT3261_DRC_AGC_2] = 0x1f00,
+ [RT3261_ANC_CTRL1] = 0x034b,
+ [RT3261_ANC_CTRL2] = 0x0066,
+ [RT3261_ANC_CTRL3] = 0x000b,
+ [RT3261_GPIO_CTRL1] = 0x0400,
+ [RT3261_DSP_CTRL3] = 0x2000,
+ [RT3261_BASE_BACK] = 0x0013,
+ [RT3261_MP3_PLUS1] = 0x0680,
+ [RT3261_MP3_PLUS2] = 0x1c17,
+ [RT3261_3D_HP] = 0x8c00,
+ [RT3261_ADJ_HPF] = 0x2a20,
+ [RT3261_HP_CALIB_AMP_DET] = 0x0400,
+ [RT3261_SV_ZCD1] = 0x0809,
+ [RT3261_VENDOR_ID1] = 0x10ec,
+ [RT3261_VENDOR_ID2] = 0x6231,
+};
+
+static int rt3261_reset(struct snd_soc_codec *codec)
+{
+ return snd_soc_write(codec, RT3261_RESET, 0);
+}
+
+static unsigned int rt3261_read(struct snd_soc_codec *codec,
+ unsigned int reg)
+{
+ unsigned int val;
+
+ val = codec->hw_read(codec, reg);
+ return val;
+}
+
+static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value, const void *data, int len)
+{
+ int ret;
+
+ if (!snd_soc_codec_volatile_register(codec, reg) &&
+ reg < codec->driver->reg_cache_size &&
+ !codec->cache_bypass) {
+ ret = snd_soc_cache_write(codec, reg, value);
+ if (ret < 0)
+ return -1;
+ }
+
+ if (codec->cache_only) {
+ codec->cache_sync = 1;
+ return 0;
+ }
+
+ ret = codec->hw_write(codec->control_data, data, len);
+ if (ret == len)
+ return 0;
+ if (ret < 0)
+ return ret;
+ else
+ return -EIO;
+}
+
+static int rt3261_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value)
+{
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ u8 data[3];
+
+ data[0] = reg;
+ data[1] = (value >> 8) & 0xff;
+ data[2] = value & 0xff;
+
+ return do_hw_write(codec, reg, value, data, 3);
+}
+
+/**
+ * rt3261_index_write - Write private register.
+ * @codec: SoC audio codec device.
+ * @reg: Private register index.
+ * @value: Private register Data.
+ *
+ * Modify private register for advanced setting. It can be written through
+ * private index (0x6a) and data (0x6c) register.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_index_write(struct snd_soc_codec *codec,
+ unsigned int reg, unsigned int value)
+{
+ int ret;
+
+ ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+ goto err;
+ }
+ ret = snd_soc_write(codec, RT3261_PRIV_DATA, value);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set private value: %d\n", ret);
+ goto err;
+ }
+ return 0;
+
+err:
+ return ret;
+}
+
+/**
+ * rt3261_index_read - Read private register.
+ * @codec: SoC audio codec device.
+ * @reg: Private register index.
+ *
+ * Read advanced setting from private register. It can be read through
+ * private index (0x6a) and data (0x6c) register.
+ *
+ * Returns private register value or negative error code.
+ */
+static unsigned int rt3261_index_read(
+ struct snd_soc_codec *codec, unsigned int reg)
+{
+ int ret;
+
+ ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+ return ret;
+ }
+ return snd_soc_read(codec, RT3261_PRIV_DATA);
+}
+
+/**
+ * rt3261_index_update_bits - update private register bits
+ * @codec: audio codec
+ * @reg: Private register index.
+ * @mask: register mask
+ * @value: new value
+ *
+ * Writes new register value.
+ *
+ * Returns 1 for change, 0 for no change, or negative error code.
+ */
+static int rt3261_index_update_bits(struct snd_soc_codec *codec,
+ unsigned int reg, unsigned int mask, unsigned int value)
+{
+ unsigned int old, new;
+ int change, ret;
+
+ ret = rt3261_index_read(codec, reg);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
+ goto err;
+ }
+
+ old = ret;
+ new = (old & ~mask) | (value & mask);
+ change = old != new;
+ if (change) {
+ ret = rt3261_index_write(codec, reg, new);
+ if (ret < 0) {
+ dev_err(codec->dev,
+ "Failed to write private reg: %d\n", ret);
+ goto err;
+ }
+ }
+ return change;
+
+err:
+ return ret;
+}
+
+static int rt3261_volatile_register(
+ struct snd_soc_codec *codec, unsigned int reg)
+{
+ switch (reg) {
+ case RT3261_RESET:
+ case RT3261_PRIV_DATA:
+ case RT3261_ASRC_5:
+ case RT3261_EQ_CTRL1:
+ case RT3261_DRC_AGC_1:
+ case RT3261_ANC_CTRL1:
+ case RT3261_IRQ_CTRL2:
+ case RT3261_INT_IRQ_ST:
+ case RT3261_DSP_CTRL2:
+ case RT3261_DSP_CTRL3:
+ case RT3261_PGM_REG_ARR1:
+ case RT3261_PGM_REG_ARR3:
+ case RT3261_VENDOR_ID:
+ case RT3261_VENDOR_ID1:
+ case RT3261_VENDOR_ID2:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+static int rt3261_readable_register(
+ struct snd_soc_codec *codec, unsigned int reg)
+{
+ switch (reg) {
+ case RT3261_RESET:
+ case RT3261_SPK_VOL:
+ case RT3261_HP_VOL:
+ case RT3261_OUTPUT:
+ case RT3261_MONO_OUT:
+ case RT3261_IN1_IN2:
+ case RT3261_IN3_IN4:
+ case RT3261_INL_INR_VOL:
+ case RT3261_DAC1_DIG_VOL:
+ case RT3261_DAC2_DIG_VOL:
+ case RT3261_DAC2_CTRL:
+ case RT3261_ADC_DIG_VOL:
+ case RT3261_ADC_DATA:
+ case RT3261_ADC_BST_VOL:
+ case RT3261_STO_ADC_MIXER:
+ case RT3261_MONO_ADC_MIXER:
+ case RT3261_AD_DA_MIXER:
+ case RT3261_STO_DAC_MIXER:
+ case RT3261_MONO_DAC_MIXER:
+ case RT3261_DIG_MIXER:
+ case RT3261_DSP_PATH1:
+ case RT3261_DSP_PATH2:
+ case RT3261_DIG_INF_DATA:
+ case RT3261_REC_L1_MIXER:
+ case RT3261_REC_L2_MIXER:
+ case RT3261_REC_R1_MIXER:
+ case RT3261_REC_R2_MIXER:
+ case RT3261_HPO_MIXER:
+ case RT3261_SPK_L_MIXER:
+ case RT3261_SPK_R_MIXER:
+ case RT3261_SPO_L_MIXER:
+ case RT3261_SPO_R_MIXER:
+ case RT3261_SPO_CLSD_RATIO:
+ case RT3261_MONO_MIXER:
+ case RT3261_OUT_L1_MIXER:
+ case RT3261_OUT_L2_MIXER:
+ case RT3261_OUT_L3_MIXER:
+ case RT3261_OUT_R1_MIXER:
+ case RT3261_OUT_R2_MIXER:
+ case RT3261_OUT_R3_MIXER:
+ case RT3261_LOUT_MIXER:
+ case RT3261_PWR_DIG1:
+ case RT3261_PWR_DIG2:
+ case RT3261_PWR_ANLG1:
+ case RT3261_PWR_ANLG2:
+ case RT3261_PWR_MIXER:
+ case RT3261_PWR_VOL:
+ case RT3261_PRIV_INDEX:
+ case RT3261_PRIV_DATA:
+ case RT3261_I2S1_SDP:
+ case RT3261_I2S2_SDP:
+ case RT3261_I2S3_SDP:
+ case RT3261_ADDA_CLK1:
+ case RT3261_ADDA_CLK2:
+ case RT3261_DMIC:
+ case RT3261_GLB_CLK:
+ case RT3261_PLL_CTRL1:
+ case RT3261_PLL_CTRL2:
+ case RT3261_ASRC_1:
+ case RT3261_ASRC_2:
+ case RT3261_ASRC_3:
+ case RT3261_ASRC_4:
+ case RT3261_ASRC_5:
+ case RT3261_HP_OVCD:
+ case RT3261_CLS_D_OVCD:
+ case RT3261_CLS_D_OUT:
+ case RT3261_DEPOP_M1:
+ case RT3261_DEPOP_M2:
+ case RT3261_DEPOP_M3:
+ case RT3261_CHARGE_PUMP:
+ case RT3261_PV_DET_SPK_G:
+ case RT3261_MICBIAS:
+ case RT3261_EQ_CTRL1:
+ case RT3261_EQ_CTRL2:
+ case RT3261_WIND_FILTER:
+ case RT3261_DRC_AGC_1:
+ case RT3261_DRC_AGC_2:
+ case RT3261_DRC_AGC_3:
+ case RT3261_SVOL_ZC:
+ case RT3261_ANC_CTRL1:
+ case RT3261_ANC_CTRL2:
+ case RT3261_ANC_CTRL3:
+ case RT3261_JD_CTRL:
+ case RT3261_ANC_JD:
+ case RT3261_IRQ_CTRL1:
+ case RT3261_IRQ_CTRL2:
+ case RT3261_INT_IRQ_ST:
+ case RT3261_GPIO_CTRL1:
+ case RT3261_GPIO_CTRL2:
+ case RT3261_GPIO_CTRL3:
+ case RT3261_DSP_CTRL1:
+ case RT3261_DSP_CTRL2:
+ case RT3261_DSP_CTRL3:
+ case RT3261_DSP_CTRL4:
+ case RT3261_PGM_REG_ARR1:
+ case RT3261_PGM_REG_ARR2:
+ case RT3261_PGM_REG_ARR3:
+ case RT3261_PGM_REG_ARR4:
+ case RT3261_PGM_REG_ARR5:
+ case RT3261_SCB_FUNC:
+ case RT3261_SCB_CTRL:
+ case RT3261_BASE_BACK:
+ case RT3261_MP3_PLUS1:
+ case RT3261_MP3_PLUS2:
+ case RT3261_3D_HP:
+ case RT3261_ADJ_HPF:
+ case RT3261_HP_CALIB_AMP_DET:
+ case RT3261_HP_CALIB2:
+ case RT3261_SV_ZCD1:
+ case RT3261_SV_ZCD2:
+ case RT3261_GEN_CTRL1:
+ case RT3261_GEN_CTRL2:
+ case RT3261_GEN_CTRL3:
+ case RT3261_VENDOR_ID:
+ case RT3261_VENDOR_ID1:
+ case RT3261_VENDOR_ID2:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+/**
+ * rt3261_headset_detect - Detect headset.
+ * @codec: SoC audio codec device.
+ * @jack_insert: Jack insert or not.
+ *
+ * Detect whether is headset or not when jack inserted.
+ *
+ * Returns detect status.
+ */
+int rt3261_headset_detect(struct snd_soc_codec *codec, int jack_insert)
+{
+ int jack_type;
+ int sclk_src;
+
+ if(jack_insert) {
+ if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
+ snd_soc_write(codec, RT3261_PWR_ANLG1, 0x2004);
+ snd_soc_write(codec, RT3261_MICBIAS, 0x3830);
+ snd_soc_write(codec, RT3261_GEN_CTRL1 , 0x3701);
+ }
+ sclk_src = snd_soc_read(codec, RT3261_GLB_CLK) &
+ RT3261_SCLK_SRC_MASK;
+ snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_SCLK_SRC_MASK, 0x3 << RT3261_SCLK_SRC_SFT);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_LDO2, RT3261_PWR_LDO2);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
+ RT3261_PWR_MB1, RT3261_PWR_MB1);
+ snd_soc_update_bits(codec, RT3261_MICBIAS,
+ RT3261_MIC1_OVCD_MASK | RT3261_MIC1_OVTH_MASK |
+ RT3261_PWR_CLK25M_MASK | RT3261_PWR_MB_MASK,
+ RT3261_MIC1_OVCD_EN | RT3261_MIC1_OVTH_600UA |
+ RT3261_PWR_MB_PU | RT3261_PWR_CLK25M_PU);
+ snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
+ 0x1, 0x1);
+ msleep(100);
+ if (snd_soc_read(codec, RT3261_IRQ_CTRL2) & 0x8)
+ jack_type = RT3261_HEADPHO_DET;
+ else
+ jack_type = RT3261_HEADSET_DET;
+ snd_soc_update_bits(codec, RT3261_IRQ_CTRL2,
+ RT3261_MB1_OC_CLR, 0);
+ snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_SCLK_SRC_MASK, sclk_src);
+ } else {
+ snd_soc_update_bits(codec, RT3261_MICBIAS,
+ RT3261_MIC1_OVCD_MASK,
+ RT3261_MIC1_OVCD_DIS);
+
+ jack_type = RT3261_NO_JACK;
+ }
+
+ return jack_type;
+}
+EXPORT_SYMBOL(rt3261_headset_detect);
+
+/**
+ * rt3261_conn_mux_path - connect MUX widget path.
+ * @codec: SoC audio codec device.
+ * @widget_name: widget name.
+ * @path_name: path name.
+ *
+ * Make MUX path connected and update register.
+ *
+ * Returns 0 for success or negative error code.
+ */
+int rt3261_conn_mux_path(struct snd_soc_codec *codec,
+ char *widget_name, char *path_name)
+{
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ struct snd_soc_dapm_widget *w;
+ struct snd_soc_dapm_path *path;
+ struct snd_kcontrol_new *kcontrol;
+ struct soc_enum *em;
+ unsigned int val, mask, bitmask;
+ int i, update = 0;
+
+ if (codec == NULL || widget_name == NULL || path_name == NULL)
+ return -EINVAL;
+
+ list_for_each_entry(w, &dapm->card->widgets, list)
+ {
+ if (!w->name || w->dapm != dapm)
+ continue;
+ if (!(strcmp(w->name, widget_name))) {
+ if (w->id != snd_soc_dapm_mux)
+ return -EINVAL;
+ dev_info(codec->dev, "w->name=%s\n", w->name);
+ list_for_each_entry(path, &w->sources, list_sink)
+ {
+ if (!(strcmp(path->name, path_name)))
+ path->connect = 1;
+ else
+ path->connect = 0;
+ dev_info(codec->dev,
+ "path->name=%s path->connect=%d\n",
+ path->name, path->connect);
+ }
+ update = 1;
+ break;
+ }
+ }
+
+ if (update) {
+ snd_soc_dapm_sync(dapm);
+
+ kcontrol = &w->kcontrols[0];
+ em = (struct soc_enum *)kcontrol->private_value;
+ for (i = 0; i < em->max; i++)
+ if (!(strcmp(path_name, em->texts[i])))
+ break;
+ for (bitmask = 1; bitmask < em->max; bitmask <<= 1)
+ ;
+ val = i << em->shift_l;
+ mask = (bitmask - 1) << em->shift_l;
+ snd_soc_update_bits(codec, em->reg, mask, val);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(rt3261_conn_mux_path);
+
+static const char *rt3261_dacr2_src[] = { "TxDC_R", "TxDP_R" };
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_dacr2_enum,RT3261_DUMMY_PR3F,
+ 14, rt3261_dacr2_src);
+static const struct snd_kcontrol_new rt3261_dacr2_mux =
+ SOC_DAPM_ENUM("Mono dacr source", rt3261_dacr2_enum);
+
+static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
+static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
+static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
+
+/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
+static unsigned int bst_tlv[] = {
+ TLV_DB_RANGE_HEAD(7),
+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
+ 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
+ 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
+ 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
+ 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
+ 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
+};
+
+static int rt3261_dmic_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = rt3261->dmic_en;
+
+ return 0;
+}
+
+static int rt3261_dmic_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ if (rt3261->dmic_en == ucontrol->value.integer.value[0])
+ return 0;
+
+ rt3261->dmic_en = ucontrol->value.integer.value[0];
+ switch (rt3261->dmic_en) {
+ case RT3261_DMIC_DIS:
+ snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
+ RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK |
+ RT3261_GP4_PIN_MASK,
+ RT3261_GP2_PIN_GPIO2 | RT3261_GP3_PIN_GPIO3 |
+ RT3261_GP4_PIN_GPIO4);
+ snd_soc_update_bits(codec, RT3261_DMIC,
+ RT3261_DMIC_1_DP_MASK | RT3261_DMIC_2_DP_MASK,
+ RT3261_DMIC_1_DP_GPIO3 | RT3261_DMIC_2_DP_GPIO4);
+ snd_soc_update_bits(codec, RT3261_DMIC,
+ RT3261_DMIC_1_EN_MASK | RT3261_DMIC_2_EN_MASK,
+ RT3261_DMIC_1_DIS | RT3261_DMIC_2_DIS);
+ break;
+
+ case RT3261_DMIC1:
+ snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
+ RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK,
+ RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP3_PIN_DMIC1_SDA);
+ snd_soc_update_bits(codec, RT3261_DMIC,
+ RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK |
+ RT3261_DMIC_1_DP_MASK,
+ RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING |
+ RT3261_DMIC_1_DP_IN1P);
+ snd_soc_update_bits(codec, RT3261_DMIC,
+ RT3261_DMIC_1_EN_MASK, RT3261_DMIC_1_EN);
+ break;
+
+ case RT3261_DMIC2:
+ snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
+ RT3261_GP2_PIN_MASK | RT3261_GP4_PIN_MASK,
+ RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP4_PIN_DMIC2_SDA);
+ snd_soc_update_bits(codec, RT3261_DMIC,
+ RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK |
+ RT3261_DMIC_2_DP_MASK,
+ RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING |
+ RT3261_DMIC_2_DP_IN1N);
+ snd_soc_update_bits(codec, RT3261_DMIC,
+ RT3261_DMIC_2_EN_MASK, RT3261_DMIC_2_EN);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+
+/* IN1/IN2 Input Type */
+static const char *rt3261_input_mode[] = {
+ "Single ended", "Differential"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_in1_mode_enum, RT3261_IN1_IN2,
+ RT3261_IN_SFT1, rt3261_input_mode);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_in2_mode_enum, RT3261_IN3_IN4,
+ RT3261_IN_SFT2, rt3261_input_mode);
+
+/* Interface data select */
+static const char *rt3261_data_select[] = {
+ "Normal", "left copy to right", "right copy to left", "Swap"};
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_if1_dac_enum, RT3261_DIG_INF_DATA,
+ RT3261_IF1_DAC_SEL_SFT, rt3261_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_if1_adc_enum, RT3261_DIG_INF_DATA,
+ RT3261_IF1_ADC_SEL_SFT, rt3261_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_if2_dac_enum, RT3261_DIG_INF_DATA,
+ RT3261_IF2_DAC_SEL_SFT, rt3261_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_enum, RT3261_DIG_INF_DATA,
+ RT3261_IF2_ADC_SEL_SFT, rt3261_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_if3_dac_enum, RT3261_DIG_INF_DATA,
+ RT3261_IF3_DAC_SEL_SFT, rt3261_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_if3_adc_enum, RT3261_DIG_INF_DATA,
+ RT3261_IF3_ADC_SEL_SFT, rt3261_data_select);
+
+/* Class D speaker gain ratio */
+static const char *rt3261_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
+ "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_clsd_spk_ratio_enum, RT3261_CLS_D_OUT,
+ RT3261_CLSD_RATIO_SFT, rt3261_clsd_spk_ratio);
+
+/* DMIC */
+static const char *rt3261_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_dmic_enum, 0, 0, rt3261_dmic_mode);
+
+
+
+#ifdef RT3261_REG_RW
+#define REGVAL_MAX 0xffff
+static unsigned int regctl_addr;
+static int rt3261_regctl_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 2;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = REGVAL_MAX;
+ return 0;
+}
+
+static int rt3261_regctl_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ ucontrol->value.integer.value[0] = regctl_addr;
+ ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
+ return 0;
+}
+
+static int rt3261_regctl_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ regctl_addr = ucontrol->value.integer.value[0];
+ if(ucontrol->value.integer.value[1] <= REGVAL_MAX)
+ snd_soc_write(codec, regctl_addr, ucontrol->value.integer.value[1]);
+ return 0;
+}
+#endif
+
+
+static int rt3261_vol_rescale_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ unsigned int val = snd_soc_read(codec, mc->reg);
+
+ ucontrol->value.integer.value[0] = RT3261_VOL_RSCL_MAX -
+ ((val & RT3261_L_VOL_MASK) >> mc->shift);
+ ucontrol->value.integer.value[1] = RT3261_VOL_RSCL_MAX -
+ (val & RT3261_R_VOL_MASK);
+
+ return 0;
+}
+
+static int rt3261_vol_rescale_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ unsigned int val, val2;
+
+ val = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[0];
+ val2 = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[1];
+ return snd_soc_update_bits_locked(codec, mc->reg, RT3261_L_VOL_MASK |
+ RT3261_R_VOL_MASK, val << mc->shift | val2);
+}
+
+
+static const struct snd_kcontrol_new rt3261_snd_controls[] = {
+ /* Speaker Output Volume */
+ SOC_DOUBLE("Speaker Playback Switch", RT3261_SPK_VOL,
+ RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
+ SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT3261_SPK_VOL,
+ RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
+ rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
+ /* Headphone Output Volume */
+ SOC_DOUBLE("HP Playback Switch", RT3261_HP_VOL,
+ RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
+ SOC_DOUBLE_EXT_TLV("HP Playback Volume", RT3261_HP_VOL,
+ RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
+ rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
+ /* OUTPUT Control */
+ SOC_DOUBLE("OUT Playback Switch", RT3261_OUTPUT,
+ RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
+ SOC_DOUBLE("OUT Channel Switch", RT3261_OUTPUT,
+ RT3261_VOL_L_SFT, RT3261_VOL_R_SFT, 1, 1),
+ SOC_DOUBLE_TLV("OUT Playback Volume", RT3261_OUTPUT,
+ RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, 39, 1, out_vol_tlv),
+ /* MONO Output Control */
+ SOC_SINGLE("Mono Playback Switch", RT3261_MONO_OUT,
+ RT3261_L_MUTE_SFT, 1, 1),
+ /* DAC Digital Volume */
+ SOC_DOUBLE("DAC2 Playback Switch", RT3261_DAC2_CTRL,
+ RT3261_M_DAC_L2_VOL_SFT, RT3261_M_DAC_R2_VOL_SFT, 1, 1),
+ SOC_DOUBLE_TLV("DAC1 Playback Volume", RT3261_DAC1_DIG_VOL,
+ RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
+ 175, 0, dac_vol_tlv),
+ SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT3261_DAC2_DIG_VOL,
+ RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
+ 175, 0, dac_vol_tlv),
+ /* IN1/IN2 Control */
+ SOC_ENUM("IN1 Mode Control", rt3261_in1_mode_enum),
+ SOC_SINGLE_TLV("IN1 Boost", RT3261_IN1_IN2,
+ RT3261_BST_SFT1, 8, 0, bst_tlv),
+ SOC_ENUM("IN2 Mode Control", rt3261_in2_mode_enum),
+ SOC_SINGLE_TLV("IN2 Boost", RT3261_IN3_IN4,
+ RT3261_BST_SFT2, 8, 0, bst_tlv),
+ /* INL/INR Volume Control */
+ SOC_DOUBLE_TLV("IN Capture Volume", RT3261_INL_INR_VOL,
+ RT3261_INL_VOL_SFT, RT3261_INR_VOL_SFT,
+ 31, 1, in_vol_tlv),
+ /* ADC Digital Volume Control */
+ SOC_DOUBLE("ADC Capture Switch", RT3261_ADC_DIG_VOL,
+ RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
+ SOC_DOUBLE_TLV("ADC Capture Volume", RT3261_ADC_DIG_VOL,
+ RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
+ 127, 0, adc_vol_tlv),
+ SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT3261_ADC_DATA,
+ RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
+ 127, 0, adc_vol_tlv),
+ /* ADC Boost Volume Control */
+ SOC_DOUBLE_TLV("ADC Boost Gain", RT3261_ADC_BST_VOL,
+ RT3261_ADC_L_BST_SFT, RT3261_ADC_R_BST_SFT,
+ 3, 0, adc_bst_tlv),
+ /* Class D speaker gain ratio */
+ SOC_ENUM("Class D SPK Ratio Control", rt3261_clsd_spk_ratio_enum),
+ /* DMIC */
+ SOC_ENUM_EXT("DMIC Switch", rt3261_dmic_enum,
+ rt3261_dmic_get, rt3261_dmic_put),
+
+#ifdef RT3261_REG_RW
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Register Control",
+ .info = rt3261_regctl_info,
+ .get = rt3261_regctl_get,
+ .put = rt3261_regctl_put,
+ },
+#endif
+};
+
+/**
+ * set_dmic_clk - Set parameter of dmic.
+ *
+ * @w: DAPM widget.
+ * @kcontrol: The kcontrol of this widget.
+ * @event: Event id.
+ *
+ * Choose dmic clock between 1MHz and 3MHz.
+ * It is better for clock to approximate 3MHz.
+ */
+static int set_dmic_clk(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
+
+ rate = rt3261->lrck[rt3261->aif_pu] << 8;
+ red = 3000000 * 12;
+ for (i = 0; i < ARRAY_SIZE(div); i++) {
+ bound = div[i] * 3000000;
+ if (rate > bound)
+ continue;
+ temp = bound - rate;
+ if (temp < red) {
+ red = temp;
+ idx = i;
+ }
+ }
+ if (idx < 0)
+ dev_err(codec->dev, "Failed to set DMIC clock\n");
+ else
+ snd_soc_update_bits(codec, RT3261_DMIC, RT3261_DMIC_CLK_MASK,
+ idx << RT3261_DMIC_CLK_SFT);
+ return idx;
+}
+
+static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
+ struct snd_soc_dapm_widget *sink)
+{
+ unsigned int val;
+
+ val = snd_soc_read(source->codec, RT3261_GLB_CLK);
+ val &= RT3261_SCLK_SRC_MASK;
+ if (val == RT3261_SCLK_SRC_PLL1)
+ return 1;
+ else
+ return 0;
+}
+
+/* Digital Mixer */
+static const struct snd_kcontrol_new rt3261_sto_adc_l_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
+ RT3261_M_ADC_L1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
+ RT3261_M_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_sto_adc_r_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
+ RT3261_M_ADC_R1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
+ RT3261_M_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_mono_adc_l_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
+ RT3261_M_MONO_ADC_L1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
+ RT3261_M_MONO_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_mono_adc_r_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
+ RT3261_M_MONO_ADC_R1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
+ RT3261_M_MONO_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_dac_l_mix[] = {
+ SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
+ RT3261_M_ADCMIX_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
+ RT3261_M_IF1_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_dac_r_mix[] = {
+ SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
+ RT3261_M_ADCMIX_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
+ RT3261_M_IF1_DAC_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_sto_dac_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_STO_DAC_MIXER,
+ RT3261_M_DAC_L1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_STO_DAC_MIXER,
+ RT3261_M_DAC_L2_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
+ RT3261_M_ANC_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_sto_dac_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_STO_DAC_MIXER,
+ RT3261_M_DAC_R1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_STO_DAC_MIXER,
+ RT3261_M_DAC_R2_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
+ RT3261_M_ANC_DAC_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_mono_dac_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_MONO_DAC_MIXER,
+ RT3261_M_DAC_L1_MONO_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
+ RT3261_M_DAC_L2_MONO_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
+ RT3261_M_DAC_R2_MONO_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_mono_dac_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_MONO_DAC_MIXER,
+ RT3261_M_DAC_R1_MONO_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
+ RT3261_M_DAC_R2_MONO_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
+ RT3261_M_DAC_L2_MONO_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_dig_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_DIG_MIXER,
+ RT3261_M_STO_L_DAC_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_DIG_MIXER,
+ RT3261_M_DAC_L2_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_dig_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_DIG_MIXER,
+ RT3261_M_STO_R_DAC_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_DIG_MIXER,
+ RT3261_M_DAC_R2_DAC_R_SFT, 1, 1),
+};
+
+/* Analog Input Mixer */
+static const struct snd_kcontrol_new rt3261_rec_l_mix[] = {
+ SOC_DAPM_SINGLE("HPOL Switch", RT3261_REC_L2_MIXER,
+ RT3261_M_HP_L_RM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INL Switch", RT3261_REC_L2_MIXER,
+ RT3261_M_IN_L_RM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_L2_MIXER,
+ RT3261_M_BST2_RM_L, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_L2_MIXER,
+ RT3261_M_BST4_RM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_L2_MIXER,
+ RT3261_M_BST1_RM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_REC_L2_MIXER,
+ RT3261_M_OM_L_RM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_rec_r_mix[] = {
+ SOC_DAPM_SINGLE("HPOR Switch", RT3261_REC_R2_MIXER,
+ RT3261_M_HP_R_RM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INR Switch", RT3261_REC_R2_MIXER,
+ RT3261_M_IN_R_RM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_R2_MIXER,
+ RT3261_M_BST2_RM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_R2_MIXER,
+ RT3261_M_BST4_RM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_R2_MIXER,
+ RT3261_M_BST1_RM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_REC_R2_MIXER,
+ RT3261_M_OM_R_RM_R_SFT, 1, 1),
+};
+
+/* Analog Output Mixer */
+static const struct snd_kcontrol_new rt3261_spk_l_mix[] = {
+ SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_SPK_L_MIXER,
+ RT3261_M_RM_L_SM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INL Switch", RT3261_SPK_L_MIXER,
+ RT3261_M_IN_L_SM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPK_L_MIXER,
+ RT3261_M_DAC_L1_SM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_SPK_L_MIXER,
+ RT3261_M_DAC_L2_SM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_SPK_L_MIXER,
+ RT3261_M_OM_L_SM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_spk_r_mix[] = {
+ SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_SPK_R_MIXER,
+ RT3261_M_RM_R_SM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INR Switch", RT3261_SPK_R_MIXER,
+ RT3261_M_IN_R_SM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPK_R_MIXER,
+ RT3261_M_DAC_R1_SM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_SPK_R_MIXER,
+ RT3261_M_DAC_R2_SM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_SPK_R_MIXER,
+ RT3261_M_OM_R_SM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_out_l_mix[] = {
+ SOC_DAPM_SINGLE("SPK MIXL Switch", RT3261_OUT_L3_MIXER,
+ RT3261_M_SM_L_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_L3_MIXER,
+ RT3261_M_BST1_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INL Switch", RT3261_OUT_L3_MIXER,
+ RT3261_M_IN_L_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_OUT_L3_MIXER,
+ RT3261_M_RM_L_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_L3_MIXER,
+ RT3261_M_DAC_R2_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_L3_MIXER,
+ RT3261_M_DAC_L2_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_OUT_L3_MIXER,
+ RT3261_M_DAC_L1_OM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_out_r_mix[] = {
+ SOC_DAPM_SINGLE("SPK MIXR Switch", RT3261_OUT_R3_MIXER,
+ RT3261_M_SM_L_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT3261_OUT_R3_MIXER,
+ RT3261_M_BST4_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_R3_MIXER,
+ RT3261_M_BST1_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INR Switch", RT3261_OUT_R3_MIXER,
+ RT3261_M_IN_R_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_OUT_R3_MIXER,
+ RT3261_M_RM_R_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_R3_MIXER,
+ RT3261_M_DAC_L2_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_R3_MIXER,
+ RT3261_M_DAC_R2_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_OUT_R3_MIXER,
+ RT3261_M_DAC_R1_OM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_spo_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
+ RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
+ RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_L_MIXER,
+ RT3261_M_SV_R_SPM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("SPKVOL L Switch", RT3261_SPO_L_MIXER,
+ RT3261_M_SV_L_SPM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_L_MIXER,
+ RT3261_M_BST1_SPM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_spo_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_R_MIXER,
+ RT3261_M_DAC_R1_SPM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_R_MIXER,
+ RT3261_M_SV_R_SPM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_R_MIXER,
+ RT3261_M_BST1_SPM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_hpo_mix[] = {
+ SOC_DAPM_SINGLE("DAC2 Switch", RT3261_HPO_MIXER,
+ RT3261_M_DAC2_HM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC1 Switch", RT3261_HPO_MIXER,
+ RT3261_M_DAC1_HM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("HPVOL Switch", RT3261_HPO_MIXER,
+ RT3261_M_HPVOL_HM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_lout_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_LOUT_MIXER,
+ RT3261_M_DAC_L1_LM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_LOUT_MIXER,
+ RT3261_M_DAC_R1_LM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_LOUT_MIXER,
+ RT3261_M_OV_L_LM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_LOUT_MIXER,
+ RT3261_M_OV_R_LM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt3261_mono_mix[] = {
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_MIXER,
+ RT3261_M_DAC_R2_MM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_MIXER,
+ RT3261_M_DAC_L2_MM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_MONO_MIXER,
+ RT3261_M_OV_R_MM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_MONO_MIXER,
+ RT3261_M_OV_L_MM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT3261_MONO_MIXER,
+ RT3261_M_BST1_MM_SFT, 1, 1),
+};
+
+/* INL/R source */
+static const char *rt3261_inl_src[] = {"IN2P", "MonoP"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_inl_enum, RT3261_INL_INR_VOL,
+ RT3261_INL_SEL_SFT, rt3261_inl_src);
+
+static const struct snd_kcontrol_new rt3261_inl_mux =
+ SOC_DAPM_ENUM("INL source", rt3261_inl_enum);
+
+static const char *rt3261_inr_src[] = {"IN2N", "MonoN"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_inr_enum, RT3261_INL_INR_VOL,
+ RT3261_INR_SEL_SFT, rt3261_inr_src);
+
+static const struct snd_kcontrol_new rt3261_inr_mux =
+ SOC_DAPM_ENUM("INR source", rt3261_inr_enum);
+
+/* Stereo ADC source */
+static const char *rt3261_stereo_adc1_src[] = {"DIG MIX", "ADC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_stereo_adc1_enum, RT3261_STO_ADC_MIXER,
+ RT3261_ADC_1_SRC_SFT, rt3261_stereo_adc1_src);
+
+static const struct snd_kcontrol_new rt3261_sto_adc_l1_mux =
+ SOC_DAPM_ENUM("Stereo ADC L1 source", rt3261_stereo_adc1_enum);
+
+static const struct snd_kcontrol_new rt3261_sto_adc_r1_mux =
+ SOC_DAPM_ENUM("Stereo ADC R1 source", rt3261_stereo_adc1_enum);
+
+static const char *rt3261_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_stereo_adc2_enum, RT3261_STO_ADC_MIXER,
+ RT3261_ADC_2_SRC_SFT, rt3261_stereo_adc2_src);
+
+static const struct snd_kcontrol_new rt3261_sto_adc_l2_mux =
+ SOC_DAPM_ENUM("Stereo ADC L2 source", rt3261_stereo_adc2_enum);
+
+static const struct snd_kcontrol_new rt3261_sto_adc_r2_mux =
+ SOC_DAPM_ENUM("Stereo ADC R2 source", rt3261_stereo_adc2_enum);
+
+/* Mono ADC source */
+static const char *rt3261_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_mono_adc_l1_enum, RT3261_MONO_ADC_MIXER,
+ RT3261_MONO_ADC_L1_SRC_SFT, rt3261_mono_adc_l1_src);
+
+static const struct snd_kcontrol_new rt3261_mono_adc_l1_mux =
+ SOC_DAPM_ENUM("Mono ADC1 left source", rt3261_mono_adc_l1_enum);
+
+static const char *rt3261_mono_adc_l2_src[] =
+ {"DMIC L1", "DMIC L2", "Mono DAC MIXL"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_mono_adc_l2_enum, RT3261_MONO_ADC_MIXER,
+ RT3261_MONO_ADC_L2_SRC_SFT, rt3261_mono_adc_l2_src);
+
+static const struct snd_kcontrol_new rt3261_mono_adc_l2_mux =
+ SOC_DAPM_ENUM("Mono ADC2 left source", rt3261_mono_adc_l2_enum);
+
+static const char *rt3261_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_mono_adc_r1_enum, RT3261_MONO_ADC_MIXER,
+ RT3261_MONO_ADC_R1_SRC_SFT, rt3261_mono_adc_r1_src);
+
+static const struct snd_kcontrol_new rt3261_mono_adc_r1_mux =
+ SOC_DAPM_ENUM("Mono ADC1 right source", rt3261_mono_adc_r1_enum);
+
+static const char *rt3261_mono_adc_r2_src[] =
+ {"DMIC R1", "DMIC R2", "Mono DAC MIXR"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_mono_adc_r2_enum, RT3261_MONO_ADC_MIXER,
+ RT3261_MONO_ADC_R2_SRC_SFT, rt3261_mono_adc_r2_src);
+
+static const struct snd_kcontrol_new rt3261_mono_adc_r2_mux =
+ SOC_DAPM_ENUM("Mono ADC2 right source", rt3261_mono_adc_r2_enum);
+
+/* DAC2 channel source */
+static const char *rt3261_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_dac_l2_enum, RT3261_DSP_PATH2,
+ RT3261_DAC_L2_SEL_SFT, rt3261_dac_l2_src);
+
+static const struct snd_kcontrol_new rt3261_dac_l2_mux =
+ SOC_DAPM_ENUM("DAC2 left channel source", rt3261_dac_l2_enum);
+
+static const char *rt3261_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_dac_r2_enum, RT3261_DSP_PATH2,
+ RT3261_DAC_R2_SEL_SFT, rt3261_dac_r2_src);
+
+static const struct snd_kcontrol_new rt3261_dac_r2_mux =
+ SOC_DAPM_ENUM("DAC2 right channel source", rt3261_dac_r2_enum);
+
+/* Interface 2 ADC channel source */
+static const char *rt3261_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_l_enum, RT3261_DSP_PATH2,
+ RT3261_IF2_ADC_L_SEL_SFT, rt3261_if2_adc_l_src);
+
+static const struct snd_kcontrol_new rt3261_if2_adc_l_mux =
+ SOC_DAPM_ENUM("IF2 ADC left channel source", rt3261_if2_adc_l_enum);
+
+static const char *rt3261_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
+
+static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_r_enum, RT3261_DSP_PATH2,
+ RT3261_IF2_ADC_R_SEL_SFT, rt3261_if2_adc_r_src);
+
+static const struct snd_kcontrol_new rt3261_if2_adc_r_mux =
+ SOC_DAPM_ENUM("IF2 ADC right channel source", rt3261_if2_adc_r_enum);
+
+/* digital interface and iis interface map */
+static const char *rt3261_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
+ "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
+ "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_dai_iis_map_enum, RT3261_I2S1_SDP,
+ RT3261_I2S_IF_SFT, rt3261_dai_iis_map);
+
+static const struct snd_kcontrol_new rt3261_dai_mux =
+ SOC_DAPM_ENUM("DAI select", rt3261_dai_iis_map_enum);
+
+/* SDI select */
+static const char *rt3261_sdi_sel[] = {"IF1", "IF2"};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt3261_sdi_sel_enum, RT3261_I2S2_SDP,
+ RT3261_I2S2_SDI_SFT, rt3261_sdi_sel);
+
+static const struct snd_kcontrol_new rt3261_sdi_mux =
+ SOC_DAPM_ENUM("SDI select", rt3261_sdi_sel_enum);
+
+static int rt3261_adc_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ unsigned int val, mask;
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ rt3261_index_update_bits(codec,
+ RT3261_CHOP_DAC_ADC, 0x1000, 0x1000);
+ val = snd_soc_read(codec, RT3261_MONO_ADC_MIXER);
+ mask = RT3261_M_MONO_ADC_L1 | RT3261_M_MONO_ADC_L2 |
+ RT3261_M_MONO_ADC_R1 | RT3261_M_MONO_ADC_R2;
+ if ((val & mask) ^ mask)
+ snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
+ RT3261_M_MAMIX_L | RT3261_M_MAMIX_R, 0);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
+ RT3261_M_MAMIX_L | RT3261_M_MAMIX_R,
+ RT3261_M_MAMIX_L | RT3261_M_MAMIX_R);
+ rt3261_index_update_bits(codec,
+ RT3261_CHOP_DAC_ADC, 0x1000, 0x0000);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int rt3261_spk_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, RT3261_PWR_DIG1,
+ RT3261_PWR_CLS_D, RT3261_PWR_CLS_D);
+ rt3261_index_update_bits(codec,
+ RT3261_CLSD_INT_REG1, 0xf000, 0xf000);
+ snd_soc_update_bits(codec, RT3261_SPK_VOL,
+ RT3261_L_MUTE | RT3261_R_MUTE, 0);
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, RT3261_SPK_VOL,
+ RT3261_L_MUTE | RT3261_R_MUTE,
+ RT3261_L_MUTE | RT3261_R_MUTE);
+ rt3261_index_update_bits(codec,
+ RT3261_CLSD_INT_REG1, 0xf000, 0x0000);
+ snd_soc_update_bits(codec, RT3261_PWR_DIG1,
+ RT3261_PWR_CLS_D, 0);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+void hp_amp_power(struct snd_soc_codec *codec, int on)
+{
+ static int hp_amp_power_count;
+ printk("hp_amp_power on=%d hp_amp_power_count=%d\n",on,hp_amp_power_count);
+// dump_reg(codec);
+ if(on) {
+ if(hp_amp_power_count <= 0) {
+ /* depop parameters */
+ snd_soc_update_bits(codec, RT3261_DEPOP_M2,
+ RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
+ RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
+ rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
+ /* headphone amp power on */
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2 , 0);
+ snd_soc_update_bits(codec, RT3261_PWR_VOL,
+ RT3261_PWR_HV_L | RT3261_PWR_HV_R,
+ RT3261_PWR_HV_L | RT3261_PWR_HV_R);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA | RT3261_PWR_LM,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA | RT3261_PWR_LM);
+ msleep(50);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2);
+
+ snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
+ RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
+ rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
+ RT3261_HP_CO_EN | RT3261_HP_SG_EN);
+ }
+ hp_amp_power_count++;
+ } else {
+ hp_amp_power_count--;
+ if(hp_amp_power_count <= 0) {
+ rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
+ RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
+ RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
+ /* headphone amp power down */
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
+ RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
+ RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
+ RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
+ RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
+ RT3261_HP_SG_EN | RT3261_HP_CB_PD);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA | RT3261_PWR_LM,
+ 0);
+ }
+ }
+}
+
+#if 1 //seq
+static void rt3261_pmu_depop(struct snd_soc_codec *codec)
+{
+#if 0
+ /* depop parameters */
+ snd_soc_update_bits(codec, RT3261_DEPOP_M2,
+ RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
+ RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
+ rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
+ /* headphone amp power on */
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
+ snd_soc_update_bits(codec, RT3261_PWR_VOL,
+ RT3261_PWR_HV_L | RT3261_PWR_HV_R,
+ RT3261_PWR_HV_L | RT3261_PWR_HV_R);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
+ msleep(50);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
+ RT3261_PWR_HP_R | RT3261_PWR_HA,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
+ RT3261_PWR_HP_R | RT3261_PWR_HA);
+ snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
+ RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
+ rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
+ RT3261_HP_CO_EN | RT3261_HP_SG_EN);
+#else
+ hp_amp_power(codec, 1);
+#endif
+ /* headphone unmute sequence */
+ snd_soc_update_bits(codec, RT3261_DEPOP_M3,
+ RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
+ (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
+ (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
+ (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
+ rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_RSTN_MASK, RT3261_RSTN_EN);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
+ RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
+ snd_soc_update_bits(codec, RT3261_HP_VOL,
+ RT3261_L_MUTE | RT3261_R_MUTE, 0);
+ msleep(100);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
+ RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
+ RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
+ msleep(20);
+ snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
+ RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
+}
+
+static void rt3261_pmd_depop(struct snd_soc_codec *codec)
+{
+ /* headphone mute sequence */
+ snd_soc_update_bits(codec, RT3261_DEPOP_M3,
+ RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
+ (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
+ (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
+ (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
+ rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_RSTP_MASK, RT3261_RSTP_EN);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
+ RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
+ RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
+ snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
+ RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
+ msleep(90);
+ snd_soc_update_bits(codec, RT3261_HP_VOL,
+ RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
+ msleep(30);
+#if 0
+ rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
+ RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
+ RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
+ /* headphone amp power down */
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
+ RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
+ RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
+ RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
+ RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
+ RT3261_HP_SG_EN | RT3261_HP_CB_PD);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
+ 0);
+#else
+ hp_amp_power(codec, 0);
+#endif
+}
+#else //one bit
+static void rt3261_pmu_depop(struct snd_soc_codec *codec)
+{
+ /* depop parameters */
+ snd_soc_update_bits(codec, RT3261_DEPOP_M2,
+ RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
+ RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
+ rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
+ /* headphone amp power on */
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
+ snd_soc_update_bits(codec, RT3261_PWR_VOL,
+ RT3261_PWR_HV_L | RT3261_PWR_HV_R,
+ RT3261_PWR_HV_L | RT3261_PWR_HV_R);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
+ msleep(50);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2 ,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2 );
+ rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
+ /* headphone unmute sequence */
+ snd_soc_update_bits(codec, RT3261_DEPOP_M2,
+ RT3261_DEPOP_MASK | RT3261_DIG_DP_MASK,
+ RT3261_DEPOP_AUTO | RT3261_DIG_DP_EN);
+ snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
+ RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M3,
+ RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
+ (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
+ (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
+ (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_CP_MASK | RT3261_HP_SG_MASK,
+ RT3261_HP_CP_PD | RT3261_HP_SG_EN);
+ msleep(10);
+ snd_soc_update_bits(codec, RT3261_HP_VOL,
+ RT3261_L_MUTE | RT3261_R_MUTE, 0);
+ msleep(180);
+ snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
+ RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
+}
+
+static void rt3261_pmd_depop(struct snd_soc_codec *codec)
+{
+ snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
+ RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
+ snd_soc_update_bits(codec, RT3261_HP_VOL,
+ RT3261_L_MUTE | RT3261_R_MUTE,
+ RT3261_L_MUTE | RT3261_R_MUTE);
+ msleep(90);
+ snd_soc_update_bits(codec, RT3261_DEPOP_M1,
+ RT3261_HP_CB_MASK, RT3261_HP_CB_PD);
+ msleep(30);
+ rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
+ 0);
+}
+#endif
+
+static int rt3261_hp_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ rt3261_pmu_depop(codec);
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+ rt3261_pmd_depop(codec);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int rt3261_mono_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, RT3261_MONO_OUT,
+ RT3261_L_MUTE, 0);
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, RT3261_MONO_OUT,
+ RT3261_L_MUTE, RT3261_L_MUTE);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int rt3261_lout_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ hp_amp_power(codec,1);
+ snd_soc_update_bits(codec, RT3261_OUTPUT,
+ RT3261_L_MUTE | RT3261_R_MUTE, 0);
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, RT3261_OUTPUT,
+ RT3261_L_MUTE | RT3261_R_MUTE,
+ RT3261_L_MUTE | RT3261_R_MUTE);
+ hp_amp_power(codec,0);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int rt3261_index_sync_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ printk("enter %s\n",__func__);
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ case SND_SOC_DAPM_POST_PMD:
+ printk("snd_soc_read(codec,RT3261_DUMMY_PR3F)=0x%x\n",snd_soc_read(codec,RT3261_DUMMY_PR3F));
+ rt3261_index_write(codec, RT3261_MIXER_INT_REG, snd_soc_read(codec,RT3261_DUMMY_PR3F));
+
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget rt3261_dapm_widgets[] = {
+ SND_SOC_DAPM_SUPPLY("PLL1", RT3261_PWR_ANLG2,
+ RT3261_PWR_PLL_BIT, 0, NULL, 0),
+ /* Input Side */
+ /* micbias */
+ SND_SOC_DAPM_SUPPLY("LDO2", RT3261_PWR_ANLG1,
+ RT3261_PWR_LDO2_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MICBIAS("micbias1", RT3261_PWR_ANLG2,
+ RT3261_PWR_MB1_BIT, 0),
+ SND_SOC_DAPM_MICBIAS("micbias2", RT3261_PWR_ANLG2,
+ RT3261_PWR_MB2_BIT, 0),
+ /* Input Lines */
+ SND_SOC_DAPM_INPUT("MIC1"),
+ SND_SOC_DAPM_INPUT("MIC2"),
+ SND_SOC_DAPM_INPUT("MIC3"),
+ SND_SOC_DAPM_INPUT("DMIC1"),
+ SND_SOC_DAPM_INPUT("DMIC2"),
+
+ SND_SOC_DAPM_INPUT("IN1P"),
+ SND_SOC_DAPM_INPUT("IN1N"),
+ SND_SOC_DAPM_INPUT("IN2P"),
+ SND_SOC_DAPM_INPUT("IN2N"),
+ SND_SOC_DAPM_INPUT("IN3P"),
+ SND_SOC_DAPM_INPUT("IN3N"),
+ SND_SOC_DAPM_INPUT("DMIC L1"),
+ SND_SOC_DAPM_INPUT("DMIC R1"),
+ SND_SOC_DAPM_INPUT("DMIC L2"),
+ SND_SOC_DAPM_INPUT("DMIC R2"),
+ SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
+ set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
+ /* Boost */
+ SND_SOC_DAPM_PGA("BST1", RT3261_PWR_ANLG2,
+ RT3261_PWR_BST1_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("BST2", RT3261_PWR_ANLG2,
+ RT3261_PWR_BST4_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("BST3", RT3261_PWR_ANLG2,
+ RT3261_PWR_BST2_BIT, 0, NULL, 0),
+ /* Input Volume */
+ SND_SOC_DAPM_PGA("INL VOL", RT3261_PWR_VOL,
+ RT3261_PWR_IN_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("INR VOL", RT3261_PWR_VOL,
+ RT3261_PWR_IN_R_BIT, 0, NULL, 0),
+ /* IN Mux */
+ SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt3261_inl_mux),
+ SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt3261_inr_mux),
+ /* REC Mixer */
+ SND_SOC_DAPM_MIXER("RECMIXL", RT3261_PWR_MIXER, RT3261_PWR_RM_L_BIT, 0,
+ rt3261_rec_l_mix, ARRAY_SIZE(rt3261_rec_l_mix)),
+ SND_SOC_DAPM_MIXER("RECMIXR", RT3261_PWR_MIXER, RT3261_PWR_RM_R_BIT, 0,
+ rt3261_rec_r_mix, ARRAY_SIZE(rt3261_rec_r_mix)),
+ /* ADCs */
+ SND_SOC_DAPM_ADC_E("ADC L", NULL, RT3261_PWR_DIG1,
+ RT3261_PWR_ADC_L_BIT, 0, rt3261_adc_event,
+ SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_ADC_E("ADC R", NULL, RT3261_PWR_DIG1,
+ RT3261_PWR_ADC_R_BIT, 0, rt3261_adc_event,
+ SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
+ /* ADC Mux */
+ SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_sto_adc_l2_mux),
+ SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_sto_adc_r2_mux),
+ SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_sto_adc_l1_mux),
+ SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_sto_adc_r1_mux),
+ SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_mono_adc_l2_mux),
+ SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_mono_adc_l1_mux),
+ SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_mono_adc_r1_mux),
+ SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_mono_adc_r2_mux),
+ /* ADC Mixer */
+ SND_SOC_DAPM_SUPPLY("stereo filter", RT3261_PWR_DIG2,
+ RT3261_PWR_ADC_SF_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
+ rt3261_sto_adc_l_mix, ARRAY_SIZE(rt3261_sto_adc_l_mix)),
+ SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
+ rt3261_sto_adc_r_mix, ARRAY_SIZE(rt3261_sto_adc_r_mix)),
+ SND_SOC_DAPM_SUPPLY("mono left filter", RT3261_PWR_DIG2,
+ RT3261_PWR_ADC_MF_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
+ rt3261_mono_adc_l_mix, ARRAY_SIZE(rt3261_mono_adc_l_mix)),
+ SND_SOC_DAPM_SUPPLY("mono right filter", RT3261_PWR_DIG2,
+ RT3261_PWR_ADC_MF_R_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
+ rt3261_mono_adc_r_mix, ARRAY_SIZE(rt3261_mono_adc_r_mix)),
+
+ /* IF2 Mux */
+ SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_if2_adc_l_mux),
+ SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_if2_adc_r_mux),
+
+ /* Digital Interface */
+ SND_SOC_DAPM_SUPPLY("I2S1", RT3261_PWR_DIG1,
+ RT3261_PWR_I2S1_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("I2S2", RT3261_PWR_DIG1,
+ RT3261_PWR_I2S2_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("I2S3", RT3261_PWR_DIG1,
+ RT3261_PWR_I2S3_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* Digital Interface Select */
+ SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
+
+ SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
+
+ SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+ SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
+
+ /* Audio Interface */
+ SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
+
+ /* Audio DSP */
+ SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* ANC */
+ SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* Output Side */
+ /* DAC mixer before sound effect */
+ SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
+ rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix)),
+ SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
+ rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix)),
+
+ /* DAC2 channel Mux */
+ SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_dac_l2_mux),
+ SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_dac_r2_mux),
+ SND_SOC_DAPM_PGA("DAC L2 Volume", RT3261_PWR_DIG1,
+ RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("DAC R2 Volume", RT3261_PWR_DIG1,
+ RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
+
+ /* DAC Mixer */
+ SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
+ rt3261_sto_dac_l_mix, ARRAY_SIZE(rt3261_sto_dac_l_mix)),
+ SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
+ rt3261_sto_dac_r_mix, ARRAY_SIZE(rt3261_sto_dac_r_mix)),
+ SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
+ rt3261_mono_dac_l_mix, ARRAY_SIZE(rt3261_mono_dac_l_mix)),
+ SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
+ rt3261_mono_dac_r_mix, ARRAY_SIZE(rt3261_mono_dac_r_mix)),
+ SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
+ rt3261_dig_l_mix, ARRAY_SIZE(rt3261_dig_l_mix)),
+ SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
+ rt3261_dig_r_mix, ARRAY_SIZE(rt3261_dig_r_mix)),
+ SND_SOC_DAPM_MUX_E("Mono dacr Mux", SND_SOC_NOPM, 0, 0,
+ &rt3261_dacr2_mux, rt3261_index_sync_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /* DACs */
+ SND_SOC_DAPM_DAC("DAC L1", NULL, RT3261_PWR_DIG1,
+ RT3261_PWR_DAC_L1_BIT, 0),
+ SND_SOC_DAPM_DAC("DAC L2", NULL, RT3261_PWR_DIG1,
+ RT3261_PWR_DAC_L2_BIT, 0),
+ SND_SOC_DAPM_DAC("DAC R1", NULL, RT3261_PWR_DIG1,
+ RT3261_PWR_DAC_R1_BIT, 0),
+ SND_SOC_DAPM_DAC("DAC R2", NULL, RT3261_PWR_DIG1,
+ RT3261_PWR_DAC_R2_BIT, 0),
+ /* SPK/OUT Mixer */
+ SND_SOC_DAPM_MIXER("SPK MIXL", RT3261_PWR_MIXER, RT3261_PWR_SM_L_BIT,
+ 0, rt3261_spk_l_mix, ARRAY_SIZE(rt3261_spk_l_mix)),
+ SND_SOC_DAPM_MIXER("SPK MIXR", RT3261_PWR_MIXER, RT3261_PWR_SM_R_BIT,
+ 0, rt3261_spk_r_mix, ARRAY_SIZE(rt3261_spk_r_mix)),
+ SND_SOC_DAPM_MIXER("OUT MIXL", RT3261_PWR_MIXER, RT3261_PWR_OM_L_BIT,
+ 0, rt3261_out_l_mix, ARRAY_SIZE(rt3261_out_l_mix)),
+ SND_SOC_DAPM_MIXER("OUT MIXR", RT3261_PWR_MIXER, RT3261_PWR_OM_R_BIT,
+ 0, rt3261_out_r_mix, ARRAY_SIZE(rt3261_out_r_mix)),
+ /* Ouput Volume */
+ SND_SOC_DAPM_PGA("SPKVOL L", RT3261_PWR_VOL,
+ RT3261_PWR_SV_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("SPKVOL R", RT3261_PWR_VOL,
+ RT3261_PWR_SV_R_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("OUTVOL L", RT3261_PWR_VOL,
+ RT3261_PWR_OV_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("OUTVOL R", RT3261_PWR_VOL,
+ RT3261_PWR_OV_R_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("HPOVOL L", RT3261_PWR_VOL,
+ RT3261_PWR_HV_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("HPOVOL R", RT3261_PWR_VOL,
+ RT3261_PWR_HV_R_BIT, 0, NULL, 0),
+ /* SPO/HPO/LOUT/Mono Mixer */
+ SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
+ 0, rt3261_spo_l_mix, ARRAY_SIZE(rt3261_spo_l_mix)),
+ SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
+ 0, rt3261_spo_r_mix, ARRAY_SIZE(rt3261_spo_r_mix)),
+ SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
+ rt3261_hpo_mix, ARRAY_SIZE(rt3261_hpo_mix)),
+ SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
+ rt3261_hpo_mix, ARRAY_SIZE(rt3261_hpo_mix)),
+ SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
+ rt3261_lout_mix, ARRAY_SIZE(rt3261_lout_mix)),
+ SND_SOC_DAPM_MIXER("Mono MIX", RT3261_PWR_ANLG1, RT3261_PWR_MM_BIT, 0,
+ rt3261_mono_mix, ARRAY_SIZE(rt3261_mono_mix)),
+
+ SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
+ rt3261_hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_PGA_S("SPK amp", 1, SND_SOC_NOPM, 0, 0,
+ rt3261_spk_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
+ rt3261_lout_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_PGA_S("Mono amp", 1, RT3261_PWR_ANLG1,
+ RT3261_PWR_MA_BIT, 0, rt3261_mono_event,
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
+
+ /* Output Lines */
+ SND_SOC_DAPM_OUTPUT("SPOLP"),
+ SND_SOC_DAPM_OUTPUT("SPOLN"),
+ SND_SOC_DAPM_OUTPUT("SPORP"),
+ SND_SOC_DAPM_OUTPUT("SPORN"),
+ SND_SOC_DAPM_OUTPUT("HPOL"),
+ SND_SOC_DAPM_OUTPUT("HPOR"),
+ SND_SOC_DAPM_OUTPUT("LOUTL"),
+ SND_SOC_DAPM_OUTPUT("LOUTR"),
+ SND_SOC_DAPM_OUTPUT("MonoP"),
+ SND_SOC_DAPM_OUTPUT("MonoN"),
+};
+
+static const struct snd_soc_dapm_route rt3261_dapm_routes[] = {
+ {"IN1P", NULL, "LDO2"},
+ {"IN2P", NULL, "LDO2"},
+ {"IN3P", NULL, "LDO2"},
+
+ {"IN1P", NULL, "MIC1"},
+ {"IN1N", NULL, "MIC1"},
+ {"IN2P", NULL, "MIC2"},
+ {"IN2N", NULL, "MIC2"},
+ {"IN3P", NULL, "MIC3"},
+ {"IN3N", NULL, "MIC3"},
+
+ {"DMIC L1", NULL, "DMIC1"},
+ {"DMIC R1", NULL, "DMIC1"},
+ {"DMIC L2", NULL, "DMIC2"},
+ {"DMIC R2", NULL, "DMIC2"},
+
+ {"BST1", NULL, "IN1P"},
+ {"BST1", NULL, "IN1N"},
+ {"BST2", NULL, "IN2P"},
+ {"BST2", NULL, "IN2N"},
+ {"BST3", NULL, "IN3P"},
+ {"BST3", NULL, "IN3N"},
+
+ {"INL VOL", NULL, "IN2P"},
+ {"INR VOL", NULL, "IN2N"},
+
+ {"RECMIXL", "HPOL Switch", "HPOL"},
+ {"RECMIXL", "INL Switch", "INL VOL"},
+ {"RECMIXL", "BST3 Switch", "BST3"},
+ {"RECMIXL", "BST2 Switch", "BST2"},
+ {"RECMIXL", "BST1 Switch", "BST1"},
+ {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
+
+ {"RECMIXR", "HPOR Switch", "HPOR"},
+ {"RECMIXR", "INR Switch", "INR VOL"},
+ {"RECMIXR", "BST3 Switch", "BST3"},
+ {"RECMIXR", "BST2 Switch", "BST2"},
+ {"RECMIXR", "BST1 Switch", "BST1"},
+ {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
+
+ {"ADC L", NULL, "RECMIXL"},
+ {"ADC R", NULL, "RECMIXR"},
+
+ {"DMIC L1", NULL, "DMIC CLK"},
+ {"DMIC L2", NULL, "DMIC CLK"},
+
+ {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
+ {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
+ {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
+ {"Stereo ADC L1 Mux", "ADC", "ADC L"},
+ {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
+
+ {"Stereo ADC R1 Mux", "ADC", "ADC R"},
+ {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
+ {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
+ {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
+ {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
+
+ {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
+ {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
+ {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
+ {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
+ {"Mono ADC L1 Mux", "ADCL", "ADC L"},
+
+ {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
+ {"Mono ADC R1 Mux", "ADCR", "ADC R"},
+ {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
+ {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
+ {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
+
+ {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
+ {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
+ {"Stereo ADC MIXL", NULL, "stereo filter"},
+ {"stereo filter", NULL, "PLL1", check_sysclk1_source},
+
+ {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
+ {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
+ {"Stereo ADC MIXR", NULL, "stereo filter"},
+ {"stereo filter", NULL, "PLL1", check_sysclk1_source},
+
+ {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
+ {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
+ {"Mono ADC MIXL", NULL, "mono left filter"},
+ {"mono left filter", NULL, "PLL1", check_sysclk1_source},
+
+ {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
+ {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
+ {"Mono ADC MIXR", NULL, "mono right filter"},
+ {"mono right filter", NULL, "PLL1", check_sysclk1_source},
+
+ {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
+ {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
+
+ {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
+ {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
+ {"IF3 ADC L", NULL, "Mono ADC MIXL"},
+ {"IF3 ADC R", NULL, "Mono ADC MIXR"},
+ {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
+ {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
+
+ {"IF1 ADC", NULL, "I2S1"},
+ {"IF1 ADC", NULL, "IF1 ADC L"},
+ {"IF1 ADC", NULL, "IF1 ADC R"},
+ {"IF2 ADC", NULL, "I2S2"},
+ {"IF2 ADC", NULL, "IF2 ADC L"},
+ {"IF2 ADC", NULL, "IF2 ADC R"},
+ {"IF3 ADC", NULL, "I2S3"},
+ {"IF3 ADC", NULL, "IF3 ADC L"},
+ {"IF3 ADC", NULL, "IF3 ADC R"},
+
+ {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
+ {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
+ {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
+ {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
+ {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
+ {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
+ {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
+ {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
+ {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
+ {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
+
+ {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
+ {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
+ {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
+ {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
+ {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
+ {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
+ {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
+ {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
+ {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
+ {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
+
+ {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
+ {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
+ {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
+ {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
+ {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
+ {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
+ {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
+ {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
+
+ {"AIF1TX", NULL, "DAI1 TX Mux"},
+ {"AIF1TX", NULL, "SDI1 TX Mux"},
+ {"AIF2TX", NULL, "DAI2 TX Mux"},
+ {"AIF2TX", NULL, "SDI2 TX Mux"},
+ {"AIF3TX", NULL, "DAI3 TX Mux"},
+
+ {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
+ {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
+ {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
+ {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
+ {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
+ {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
+ {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
+ {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
+
+ {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
+ {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
+ {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
+ {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
+ {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
+ {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
+ {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
+ {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
+
+ {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
+ {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
+ {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
+ {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
+ {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
+ {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
+ {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
+ {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
+
+ {"IF1 DAC", NULL, "I2S1"},
+ {"IF1 DAC", NULL, "DAI1 RX Mux"},
+ {"IF2 DAC", NULL, "I2S2"},
+ {"IF2 DAC", NULL, "DAI2 RX Mux"},
+ {"IF3 DAC", NULL, "I2S3"},
+ {"IF3 DAC", NULL, "DAI3 RX Mux"},
+
+ {"IF1 DAC L", NULL, "IF1 DAC"},
+ {"IF1 DAC R", NULL, "IF1 DAC"},
+ {"IF2 DAC L", NULL, "IF2 DAC"},
+ {"IF2 DAC R", NULL, "IF2 DAC"},
+ {"IF3 DAC L", NULL, "IF3 DAC"},
+ {"IF3 DAC R", NULL, "IF3 DAC"},
+
+ {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
+ {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
+ {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
+ {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
+
+ {"ANC", NULL, "Stereo ADC MIXL"},
+ {"ANC", NULL, "Stereo ADC MIXR"},
+
+ {"Audio DSP", NULL, "DAC MIXL"},
+ {"Audio DSP", NULL, "DAC MIXR"},
+
+ {"DAC L2 Mux", "IF2", "IF2 DAC L"},
+ {"DAC L2 Mux", "IF3", "IF3 DAC L"},
+ {"DAC L2 Mux", "Base L/R", "Audio DSP"},
+ {"DAC L2 Volume", NULL, "DAC L2 Mux"},
+
+ {"DAC R2 Mux", "IF2", "IF2 DAC R"},
+ {"DAC R2 Mux", "IF3", "IF3 DAC R"},
+#if (CONFIG_SND_SOC_RT3261_MODULE | CONFIG_SND_SOC_RT3261)
+ {"DAC R2 Volume", NULL, "Mono dacr Mux"},
+ {"Mono dacr Mux", "TxDC_R", "DAC R2 Mux"},
+ {"Mono dacr Mux", "TxDP_R", "IF2 ADC R Mux"},
+#else
+ {"DAC R2 Volume", NULL, "DAC R2 Mux"},
+#endif
+
+ {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
+ {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
+ {"Stereo DAC MIXL", "ANC Switch", "ANC"},
+ {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
+ {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
+ {"Stereo DAC MIXR", "ANC Switch", "ANC"},
+
+ {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
+ {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
+ {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume"},
+ {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
+ {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
+ {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume"},
+
+ {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
+ {"DIG MIXL", "DAC L2 Switch", "DAC L2 Volume"},
+ {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
+ {"DIG MIXR", "DAC R2 Switch", "DAC R2 Volume"},
+
+ {"DAC L1", NULL, "Stereo DAC MIXL"},
+ {"DAC L1", NULL, "PLL1", check_sysclk1_source},
+ {"DAC R1", NULL, "Stereo DAC MIXR"},
+ {"DAC R1", NULL, "PLL1", check_sysclk1_source},
+ {"DAC L2", NULL, "Mono DAC MIXL"},
+ {"DAC L2", NULL, "PLL1", check_sysclk1_source},
+ {"DAC R2", NULL, "Mono DAC MIXR"},
+ {"DAC R2", NULL, "PLL1", check_sysclk1_source},
+
+ {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
+ {"SPK MIXL", "INL Switch", "INL VOL"},
+ {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
+ {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
+ {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
+ {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
+ {"SPK MIXR", "INR Switch", "INR VOL"},
+ {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
+ {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
+ {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
+
+ {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
+ {"OUT MIXL", "BST1 Switch", "BST1"},
+ {"OUT MIXL", "INL Switch", "INL VOL"},
+ {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
+ {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
+ {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
+ {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
+
+ {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
+ {"OUT MIXR", "BST2 Switch", "BST2"},
+ {"OUT MIXR", "BST1 Switch", "BST1"},
+ {"OUT MIXR", "INR Switch", "INR VOL"},
+ {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
+ {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
+ {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
+ {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
+
+ {"SPKVOL L", NULL, "SPK MIXL"},
+ {"SPKVOL R", NULL, "SPK MIXR"},
+ {"HPOVOL L", NULL, "OUT MIXL"},
+ {"HPOVOL R", NULL, "OUT MIXR"},
+ {"OUTVOL L", NULL, "OUT MIXL"},
+ {"OUTVOL R", NULL, "OUT MIXR"},
+
+ {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
+ {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
+ {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
+ {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
+ {"SPOL MIX", "BST1 Switch", "BST1"},
+ {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
+ {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
+ {"SPOR MIX", "BST1 Switch", "BST1"},
+
+ {"HPOL MIX", "DAC2 Switch", "DAC L2"},
+ {"HPOL MIX", "DAC1 Switch", "DAC L1"},
+ {"HPOL MIX", "HPVOL Switch", "HPOVOL L"},
+ {"HPOR MIX", "DAC2 Switch", "DAC R2"},
+ {"HPOR MIX", "DAC1 Switch", "DAC R1"},
+ {"HPOR MIX", "HPVOL Switch", "HPOVOL R"},
+
+ {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
+ {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
+ {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
+ {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
+
+ {"Mono MIX", "DAC R2 Switch", "DAC R2"},
+ {"Mono MIX", "DAC L2 Switch", "DAC L2"},
+ {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
+ {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
+ {"Mono MIX", "BST1 Switch", "BST1"},
+
+ {"SPK amp", NULL, "SPOL MIX"},
+ {"SPK amp", NULL, "SPOR MIX"},
+ {"SPOLP", NULL, "SPK amp"},
+ {"SPOLN", NULL, "SPK amp"},
+ {"SPORP", NULL, "SPK amp"},
+ {"SPORN", NULL, "SPK amp"},
+
+ {"HP amp", NULL, "HPOL MIX"},
+ {"HP amp", NULL, "HPOR MIX"},
+ {"HPOL", NULL, "HP amp"},
+ {"HPOR", NULL, "HP amp"},
+
+ {"LOUT amp", NULL, "LOUT MIX"},
+ {"LOUTL", NULL, "LOUT amp"},
+ {"LOUTR", NULL, "LOUT amp"},
+
+ {"Mono amp", NULL, "Mono MIX"},
+ {"MonoP", NULL, "Mono amp"},
+ {"MonoN", NULL, "Mono amp"},
+};
+
+static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
+{
+ int ret = 0, val;
+
+ if(codec == NULL)
+ return -EINVAL;
+
+ val = snd_soc_read(codec, RT3261_I2S1_SDP);
+ val = (val & RT3261_I2S_IF_MASK) >> RT3261_I2S_IF_SFT;
+ switch (dai_id) {
+ case RT3261_AIF1:
+ if (val == RT3261_IF_123 || val == RT3261_IF_132 ||
+ val == RT3261_IF_113)
+ ret |= RT3261_U_IF1;
+ if (val == RT3261_IF_312 || val == RT3261_IF_213 ||
+ val == RT3261_IF_113)
+ ret |= RT3261_U_IF2;
+ if (val == RT3261_IF_321 || val == RT3261_IF_231)
+ ret |= RT3261_U_IF3;
+ break;
+
+ case RT3261_AIF2:
+ if (val == RT3261_IF_231 || val == RT3261_IF_213 ||
+ val == RT3261_IF_223)
+ ret |= RT3261_U_IF1;
+ if (val == RT3261_IF_123 || val == RT3261_IF_321 ||
+ val == RT3261_IF_223)
+ ret |= RT3261_U_IF2;
+ if (val == RT3261_IF_132 || val == RT3261_IF_312)
+ ret |= RT3261_U_IF3;
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int get_clk_info(int sclk, int rate)
+{
+ int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
+
+ if (sclk <= 0 || rate <= 0)
+ return -EINVAL;
+
+ rate = rate << 8;
+ for (i = 0; i < ARRAY_SIZE(pd); i++)
+ if (sclk == rate * pd[i])
+ return i;
+
+ return -EINVAL;
+}
+
+static int rt3261_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_codec *codec = rtd->codec;
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
+ int pre_div, bclk_ms, frame_size;
+
+ rt3261->lrck[dai->id] = params_rate(params);
+ pre_div = get_clk_info(rt3261->sysclk, rt3261->lrck[dai->id]);
+ if (pre_div < 0) {
+ dev_err(codec->dev, "Unsupported clock setting\n");
+ return -EINVAL;
+ }
+ frame_size = snd_soc_params_to_frame_size(params);
+ if (frame_size < 0) {
+ dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
+ return -EINVAL;
+ }
+ bclk_ms = frame_size > 32 ? 1 : 0;
+ rt3261->bclk[dai->id] = rt3261->lrck[dai->id] * (32 << bclk_ms);
+
+ dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
+ rt3261->bclk[dai->id], rt3261->lrck[dai->id]);
+ dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
+ bclk_ms, pre_div, dai->id);
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ break;
+ case SNDRV_PCM_FORMAT_S20_3LE:
+ val_len |= RT3261_I2S_DL_20;
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ val_len |= RT3261_I2S_DL_24;
+ break;
+ case SNDRV_PCM_FORMAT_S8:
+ val_len |= RT3261_I2S_DL_8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dai_sel = get_sdp_info(codec, dai->id);
+ if (dai_sel < 0) {
+ dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
+ return -EINVAL;
+ }
+ if (dai_sel & RT3261_U_IF1) {
+ mask_clk = RT3261_I2S_BCLK_MS1_MASK | RT3261_I2S_PD1_MASK;
+ val_clk = bclk_ms << RT3261_I2S_BCLK_MS1_SFT |
+ pre_div << RT3261_I2S_PD1_SFT;
+ snd_soc_update_bits(codec, RT3261_I2S1_SDP,
+ RT3261_I2S_DL_MASK, val_len);
+ snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
+ }
+ if (dai_sel & RT3261_U_IF2) {
+ mask_clk = RT3261_I2S_BCLK_MS2_MASK | RT3261_I2S_PD2_MASK;
+ val_clk = bclk_ms << RT3261_I2S_BCLK_MS2_SFT |
+ pre_div << RT3261_I2S_PD2_SFT;
+ snd_soc_update_bits(codec, RT3261_I2S2_SDP,
+ RT3261_I2S_DL_MASK, val_len);
+ snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
+ }
+
+ return 0;
+}
+
+static int rt3261_prepare(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_codec *codec = rtd->codec;
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+
+ rt3261->aif_pu = dai->id;
+ return 0;
+}
+
+static int rt3261_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ unsigned int reg_val = 0, dai_sel;
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBM_CFM:
+ rt3261->master[dai->id] = 1;
+ break;
+ case SND_SOC_DAIFMT_CBS_CFS:
+ reg_val |= RT3261_I2S_MS_S;
+ rt3261->master[dai->id] = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ reg_val |= RT3261_I2S_BP_INV;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ reg_val |= RT3261_I2S_DF_LEFT;
+ break;
+ case SND_SOC_DAIFMT_DSP_A:
+ reg_val |= RT3261_I2S_DF_PCM_A;
+ break;
+ case SND_SOC_DAIFMT_DSP_B:
+ reg_val |= RT3261_I2S_DF_PCM_B;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dai_sel = get_sdp_info(codec, dai->id);
+ if (dai_sel < 0) {
+ dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
+ return -EINVAL;
+ }
+ if (dai_sel & RT3261_U_IF1) {
+ snd_soc_update_bits(codec, RT3261_I2S1_SDP,
+ RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
+ RT3261_I2S_DF_MASK, reg_val);
+ }
+ if (dai_sel & RT3261_U_IF2) {
+ snd_soc_update_bits(codec, RT3261_I2S2_SDP,
+ RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
+ RT3261_I2S_DF_MASK, reg_val);
+ }
+
+ return 0;
+}
+
+static int rt3261_set_dai_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ unsigned int reg_val = 0;
+
+ if (freq == rt3261->sysclk && clk_id == rt3261->sysclk_src)
+ return 0;
+
+ switch (clk_id) {
+ case RT3261_SCLK_S_MCLK:
+ reg_val |= RT3261_SCLK_SRC_MCLK;
+ break;
+ case RT3261_SCLK_S_PLL1:
+ reg_val |= RT3261_SCLK_SRC_PLL1;
+ break;
+ case RT3261_SCLK_S_RCCLK:
+ reg_val |= RT3261_SCLK_SRC_RCCLK;
+ break;
+ default:
+ dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
+ return -EINVAL;
+ }
+ snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_SCLK_SRC_MASK, reg_val);
+ rt3261->sysclk = freq;
+ rt3261->sysclk_src = clk_id;
+
+ dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
+
+ return 0;
+}
+
+/**
+ * rt3261_pll_calc - Calcualte PLL M/N/K code.
+ * @freq_in: external clock provided to codec.
+ * @freq_out: target clock which codec works on.
+ * @pll_code: Pointer to structure with M, N, K and bypass flag.
+ *
+ * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
+ * which make calculation more efficiently.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt3261_pll_calc(const unsigned int freq_in,
+ const unsigned int freq_out, struct rt3261_pll_code *pll_code)
+{
+ int max_n = RT3261_PLL_N_MAX, max_m = RT3261_PLL_M_MAX;
+ int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
+ bool bypass = false;
+
+ if (RT3261_PLL_INP_MAX < freq_in || RT3261_PLL_INP_MIN > freq_in)
+ return -EINVAL;
+
+ for (n_t = 0; n_t <= max_n; n_t++) {
+ in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
+ if (in_t < 0)
+ continue;
+ if (in_t == freq_out) {
+ bypass = true;
+ n = n_t;
+ goto code_find;
+ }
+ for (m_t = 0; m_t <= max_m; m_t++) {
+ out_t = in_t / (m_t + 2);
+ red = abs(out_t - freq_out);
+ if (red < red_t) {
+ n = n_t;
+ m = m_t;
+ if (red == 0)
+ goto code_find;
+ red_t = red;
+ }
+ }
+ }
+ pr_debug("Only get approximation about PLL\n");
+
+code_find:
+
+ pll_code->m_bp = bypass;
+ pll_code->m_code = m;
+ pll_code->n_code = n;
+ pll_code->k_code = 2;
+ return 0;
+}
+
+static int rt3261_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
+ unsigned int freq_in, unsigned int freq_out)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ struct rt3261_pll_code pll_code;
+ int ret, dai_sel;
+
+ if (source == rt3261->pll_src && freq_in == rt3261->pll_in &&
+ freq_out == rt3261->pll_out)
+ return 0;
+
+ if (!freq_in || !freq_out) {
+ dev_dbg(codec->dev, "PLL disabled\n");
+
+ rt3261->pll_in = 0;
+ rt3261->pll_out = 0;
+ snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_SCLK_SRC_MASK, RT3261_SCLK_SRC_MCLK);
+ return 0;
+ }
+
+ switch (source) {
+ case RT3261_PLL1_S_MCLK:
+ snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_MCLK);
+ break;
+ case RT3261_PLL1_S_BCLK1:
+ case RT3261_PLL1_S_BCLK2:
+ dai_sel = get_sdp_info(codec, dai->id);
+ if (dai_sel < 0) {
+ dev_err(codec->dev,
+ "Failed to get sdp info: %d\n", dai_sel);
+ return -EINVAL;
+ }
+ if (dai_sel & RT3261_U_IF1) {
+ snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK1);
+ }
+ if (dai_sel & RT3261_U_IF2) {
+ snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK2);
+ }
+ if (dai_sel & RT3261_U_IF3) {
+ snd_soc_update_bits(codec, RT3261_GLB_CLK,
+ RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK3);
+ }
+ break;
+ default:
+ dev_err(codec->dev, "Unknown PLL source %d\n", source);
+ return -EINVAL;
+ }
+
+ ret = rt3261_pll_calc(freq_in, freq_out, &pll_code);
+ if (ret < 0) {
+ dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
+ return ret;
+ }
+
+ dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
+ (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
+
+ snd_soc_write(codec, RT3261_PLL_CTRL1,
+ pll_code.n_code << RT3261_PLL_N_SFT | pll_code.k_code);
+ snd_soc_write(codec, RT3261_PLL_CTRL2,
+ (pll_code.m_bp ? 0 : pll_code.m_code) << RT3261_PLL_M_SFT |
+ pll_code.m_bp << RT3261_PLL_M_BP_SFT);
+
+ rt3261->pll_in = freq_in;
+ rt3261->pll_out = freq_out;
+ rt3261->pll_src = source;
+
+ return 0;
+}
+
+/**
+ * rt3261_index_show - Dump private registers.
+ * @dev: codec device.
+ * @attr: device attribute.
+ * @buf: buffer for display.
+ *
+ * To show non-zero values of all private registers.
+ *
+ * Returns buffer length.
+ */
+static ssize_t rt3261_index_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
+ struct snd_soc_codec *codec = rt3261->codec;
+ unsigned int val;
+ int cnt = 0, i;
+
+ cnt += sprintf(buf, "RT3261 index register\n");
+ for (i = 0; i < 0xb4; i++) {
+ if (cnt + RT3261_REG_DISP_LEN >= PAGE_SIZE)
+ break;
+ val = rt3261_index_read(codec, i);
+ if (!val)
+ continue;
+ cnt += snprintf(buf + cnt, RT3261_REG_DISP_LEN,
+ "%02x: %04x\n", i, val);
+ }
+
+ if (cnt >= PAGE_SIZE)
+ cnt = PAGE_SIZE - 1;
+
+ return cnt;
+}
+static DEVICE_ATTR(index_reg, 0444, rt3261_index_show, NULL);
+
+static int rt3261_set_bias_level(struct snd_soc_codec *codec,
+ enum snd_soc_bias_level level)
+{
+ switch (level) {
+ case SND_SOC_BIAS_ON:
+ break;
+
+ case SND_SOC_BIAS_PREPARE:
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
+ RT3261_PWR_MB1 | RT3261_PWR_MB2,
+ RT3261_PWR_MB1 | RT3261_PWR_MB2);
+ break;
+
+ case SND_SOC_BIAS_STANDBY:
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
+ RT3261_PWR_MB1 | RT3261_PWR_MB2, 0);
+ if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_VREF1 | RT3261_PWR_MB |
+ RT3261_PWR_BG | RT3261_PWR_VREF2,
+ RT3261_PWR_VREF1 | RT3261_PWR_MB |
+ RT3261_PWR_BG | RT3261_PWR_VREF2);
+ msleep(10);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2);
+ snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3701);
+ codec->cache_only = false;
+ codec->cache_sync = 1;
+ snd_soc_cache_sync(codec);
+ rt3261_index_sync(codec);
+ }
+ break;
+
+ case SND_SOC_BIAS_OFF:
+ snd_soc_write(codec, RT3261_DEPOP_M1, 0x0004);
+ snd_soc_write(codec, RT3261_DEPOP_M2, 0x1100);
+ snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3700);
+ snd_soc_write(codec, RT3261_PWR_DIG1, 0x0000);
+ snd_soc_write(codec, RT3261_PWR_DIG2, 0x0000);
+ snd_soc_write(codec, RT3261_PWR_VOL, 0x0000);
+ snd_soc_write(codec, RT3261_PWR_MIXER, 0x0000);
+ snd_soc_write(codec, RT3261_PWR_ANLG1, 0x0000);
+ snd_soc_write(codec, RT3261_PWR_ANLG2, 0x0000);
+ break;
+
+ default:
+ break;
+ }
+ codec->dapm.bias_level = level;
+
+ return 0;
+}
+
+static int rt3261_proc_init(void);
+
+
+static int rt3261_probe(struct snd_soc_codec *codec)
+{
+ struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
+ int ret;
+
+ pr_info("Codec driver version %s\n", VERSION);
+
+ ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
+ if (ret != 0) {
+ dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+ return ret;
+ }
+
+ #ifdef RT3261_PROC
+ rt3261_proc_init();
+ #endif
+
+ rt3261_reset(codec);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_VREF1 | RT3261_PWR_MB |
+ RT3261_PWR_BG | RT3261_PWR_VREF2,
+ RT3261_PWR_VREF1 | RT3261_PWR_MB |
+ RT3261_PWR_BG | RT3261_PWR_VREF2);
+ msleep(10);
+ snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2,
+ RT3261_PWR_FV1 | RT3261_PWR_FV2);
+ /* DMIC */
+ if (rt3261->dmic_en == RT3261_DMIC1) {
+ snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
+ RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
+ snd_soc_update_bits(codec, RT3261_DMIC,
+ RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK,
+ RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING);
+ } else if (rt3261->dmic_en == RT3261_DMIC2) {
+ snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
+ RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
+ snd_soc_update_bits(codec, RT3261_DMIC,
+ RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK,
+ RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING);
+ }
+ snd_soc_write(codec, RT3261_GEN_CTRL2, 0x4040);
+ ret = snd_soc_read(codec, RT3261_VENDOR_ID);
+ printk("read 0x%x=0x%x\n",RT3261_VENDOR_ID,ret);
+ if(0x5==ret) {
+ snd_soc_update_bits(codec, RT3261_JD_CTRL,
+ RT3261_JD1_IN4P_MASK | RT3261_JD2_IN4N_MASK,
+ RT3261_JD1_IN4P_EN | RT3261_JD2_IN4N_EN);
+ }
+ rt3261_reg_init(codec);
+
+ codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
+ rt3261->codec = codec;
+
+ snd_soc_add_controls(codec, rt3261_snd_controls,
+ ARRAY_SIZE(rt3261_snd_controls));
+ snd_soc_dapm_new_controls(&codec->dapm, rt3261_dapm_widgets,
+ ARRAY_SIZE(rt3261_dapm_widgets));
+ snd_soc_dapm_add_routes(&codec->dapm, rt3261_dapm_routes,
+ ARRAY_SIZE(rt3261_dapm_routes));
+
+#if 0
+#if (CONFIG_SND_SOC_RT3261_MODULE | CONFIG_SND_SOC_RT3261)
+ rt3261->dsp_sw = RT3261_DSP_AEC_NS_FENS;
+ rt3261_dsp_probe(codec);
+#endif
+
+#ifdef RTK_IOCTL
+#if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
+ struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
+ ioctl_ops->index_write = rt3261_index_write;
+ ioctl_ops->index_read = rt3261_index_read;
+ ioctl_ops->index_update_bits = rt3261_index_update_bits;
+ ioctl_ops->ioctl_common = rt3261_ioctl_common;
+ realtek_ce_init_hwdep(codec);
+#endif
+#endif
+
+ ret = device_create_file(codec->dev, &dev_attr_index_reg);
+ if (ret != 0) {
+ dev_err(codec->dev,
+ "Failed to create index_reg sysfs files: %d\n", ret);
+ return ret;
+ }
+#endif
+ rt3261_codec = codec;
+ return 0;
+}
+
+static int rt3261_remove(struct snd_soc_codec *codec)
+{
+ rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int rt3261_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+#if (CONFIG_SND_SOC_RT3261_MODULE | CONFIG_SND_SOC_RT3261)
+ /* After opening LDO of DSP, then close LDO of codec.
+ * (1) DSP LDO power on
+ * (2) DSP core power off
+ * (3) DSP IIS interface power off
+ * (4) Toggle pin of codec LDO1 to power off
+ */
+ rt3261_dsp_suspend(codec, state);
+#endif
+ rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
+ return 0;
+}
+
+static int rt3261_resume(struct snd_soc_codec *codec)
+{
+ rt3261_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+#if (CONFIG_SND_SOC_RT3261_MODULE | CONFIG_SND_SOC_RT3261)
+ /* After opening LDO of codec, then close LDO of DSP. */
+ rt3261_dsp_resume(codec);
+#endif
+ return 0;
+}
+#else
+#define rt3261_suspend NULL
+#define rt3261_resume NULL
+#endif
+
+#define RT3261_STEREO_RATES SNDRV_PCM_RATE_8000_96000
+#define RT3261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
+
+struct snd_soc_dai_ops rt3261_aif_dai_ops = {
+ .hw_params = rt3261_hw_params,
+ .prepare = rt3261_prepare,
+ .set_fmt = rt3261_set_dai_fmt,
+ .set_sysclk = rt3261_set_dai_sysclk,
+ .set_pll = rt3261_set_dai_pll,
+};
+
+struct snd_soc_dai_driver rt3261_dai[] = {
+ {
+ .name = "rt3261-aif1",
+ .id = RT3261_AIF1,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT3261_STEREO_RATES,
+ .formats = RT3261_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT3261_STEREO_RATES,
+ .formats = RT3261_FORMATS,
+ },
+ .ops = &rt3261_aif_dai_ops,
+ },
+ {
+ .name = "rt3261-aif2",
+ .id = RT3261_AIF2,
+ .playback = {
+ .stream_name = "AIF2 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT3261_STEREO_RATES,
+ .formats = RT3261_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF2 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT3261_STEREO_RATES,
+ .formats = RT3261_FORMATS,
+ },
+ .ops = &rt3261_aif_dai_ops,
+ },
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_rt3261 = {
+ .probe = rt3261_probe,
+ .remove = rt3261_remove,
+ .suspend = rt3261_suspend,
+ .resume = rt3261_resume,
+ .set_bias_level = rt3261_set_bias_level,
+ .reg_cache_size = RT3261_VENDOR_ID2 + 1,
+ .reg_word_size = sizeof(u16),
+ .reg_cache_default = rt3261_reg,
+ .volatile_register = rt3261_volatile_register,
+ .readable_register = rt3261_readable_register,
+ .reg_cache_step = 1,
+};
+
+static const struct i2c_device_id rt3261_i2c_id[] = {
+ { "rt3261", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, rt3261_i2c_id);
+
+static int __devinit rt3261_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ struct rt3261_priv *rt3261;
+ int ret;
+
+ rt3261 = kzalloc(sizeof(struct rt3261_priv), GFP_KERNEL);
+ if (NULL == rt3261)
+ return -ENOMEM;
+
+ i2c_set_clientdata(i2c, rt3261);
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt3261,
+ rt3261_dai, ARRAY_SIZE(rt3261_dai));
+ if (ret < 0)
+ kfree(rt3261);
+
+ return ret;
+}
+
+static int __devexit rt3261_i2c_remove(struct i2c_client *i2c)
+{
+ snd_soc_unregister_codec(&i2c->dev);
+ kfree(i2c_get_clientdata(i2c));
+ return 0;
+}
+
+static void rt3261_i2c_shutdown(struct i2c_client *client)
+{
+ struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
+ struct snd_soc_codec *codec = rt3261->codec;
+
+ if (codec != NULL)
+ rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
+}
+
+struct i2c_driver rt3261_i2c_driver = {
+ .driver = {
+ .name = "rt3261",
+ .owner = THIS_MODULE,
+ },
+ .probe = rt3261_i2c_probe,
+ .remove = __devexit_p(rt3261_i2c_remove),
+ .shutdown = rt3261_i2c_shutdown,
+ .id_table = rt3261_i2c_id,
+};
+
+static int __init rt3261_modinit(void)
+{
+ return i2c_add_driver(&rt3261_i2c_driver);
+}
+module_init(rt3261_modinit);
+
+static void __exit rt3261_modexit(void)
+{
+ i2c_del_driver(&rt3261_i2c_driver);
+}
+module_exit(rt3261_modexit);
+
+MODULE_DESCRIPTION("ASoC RT3261 driver");
+MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
+MODULE_LICENSE("GPL");
+
+
+#ifdef RT3261_PROC
+
+static ssize_t rt3261_proc_write(struct file *file, const char __user *buffer,
+ unsigned long len, void *data)
+{
+ char *cookie_pot;
+ char *p;
+ int reg;
+ int value;
+
+ cookie_pot = (char *)vmalloc( len );
+ if (!cookie_pot)
+ {
+ return -ENOMEM;
+ }
+ else
+ {
+ if (copy_from_user( cookie_pot, buffer, len ))
+ return -EFAULT;
+ }
+
+ switch(cookie_pot[0])
+ {
+ case 'd':
+ case 'D':
+ debug_write_read ++;
+ debug_write_read %= 2;
+ if(debug_write_read != 0)
+ printk("Debug read and write reg on\n");
+ else
+ printk("Debug read and write reg off\n");
+ break;
+ case 'r':
+ case 'R':
+ printk("Read reg debug\n");
+ if(cookie_pot[1] ==':')
+ {
+ debug_write_read = 1;
+ strsep(&cookie_pot,":");
+ while((p=strsep(&cookie_pot,",")))
+ {
+ reg = simple_strtol(p,NULL,16);
+ value = rt3261_read(rt3261_codec,reg);
+ printk("rt3261_read:0x%04x = 0x%04x\n",reg,value);
+ }
+ debug_write_read = 0;
+ printk("\n");
+ }
+ else
+ {
+ printk("Error Read reg debug.\n");
+ printk("For example: echo r:22,23,24,25>rt3261_ts\n");
+ }
+ break;
+ case 'w':
+ case 'W':
+ printk("Write reg debug\n");
+ if(cookie_pot[1] ==':')
+ {
+ debug_write_read = 1;
+ strsep(&cookie_pot,":");
+ while((p=strsep(&cookie_pot,"=")))
+ {
+ reg = simple_strtol(p,NULL,16);
+ p=strsep(&cookie_pot,",");
+ value = simple_strtol(p,NULL,16);
+ rt3261_write(rt3261_codec,reg,value);
+ printk("rt3261_write:0x%04x = 0x%04x\n",reg,value);
+ }
+ debug_write_read = 0;
+ printk("\n");
+ }
+ else
+ {
+ printk("Error Write reg debug.\n");
+ printk("For example: w:22=0,23=0,24=0,25=0>rt3261_ts\n");
+ }
+ break;
+ case 'a':
+ printk("Dump reg \n");
+
+ for(reg = 0; reg < 0x6e; reg+=2)
+ {
+ value = rt3261_read(rt3261_codec,reg);
+ printk("rt3261_read:0x%04x = 0x%04x\n",reg,value);
+ }
+
+ break;
+ default:
+ printk("Help for rt3261_ts .\n-->The Cmd list: \n");
+ printk("-->'d&&D' Open or Off the debug\n");
+ printk("-->'r&&R' Read reg debug,Example: echo 'r:22,23,24,25'>rt3261_ts\n");
+ printk("-->'w&&W' Write reg debug,Example: echo 'w:22=0,23=0,24=0,25=0'>rt3261_ts\n");
+ break;
+ }
+
+ return len;
+}
+
+static const struct file_operations rt3261_proc_fops = {
+ .owner = THIS_MODULE,
+};
+
+static int rt3261_proc_init(void)
+{
+ struct proc_dir_entry *rt3261_proc_entry;
+ rt3261_proc_entry = create_proc_entry("driver/rt3261_ts", 0777, NULL);
+ if(rt3261_proc_entry != NULL)
+ {
+ rt3261_proc_entry->write_proc = rt3261_proc_write;
+ return 0;
+ }
+ else
+ {
+ printk("create proc error !\n");
+ return -1;
+ }
+}
+#endif
--- /dev/null
+/*
+ * rt3261.h -- RT3261 ALSA SoC audio driver
+ *
+ * Copyright 2011 Realtek Microelectronics
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT3261_H__
+#define __RT3261_H__
+
+/* Info */
+#define RT3261_RESET 0x00
+#define RT3261_VENDOR_ID 0xfd
+#define RT3261_VENDOR_ID1 0xfe
+#define RT3261_VENDOR_ID2 0xff
+/* I/O - Output */
+#define RT3261_SPK_VOL 0x01
+#define RT3261_HP_VOL 0x02
+#define RT3261_OUTPUT 0x03
+#define RT3261_MONO_OUT 0x04
+/* Dummy */
+#define RT3261_DUMMY_PR3F 0x05
+/* I/O - Input */
+#define RT3261_IN1_IN2 0x0d
+#define RT3261_IN3_IN4 0x0e
+#define RT3261_INL_INR_VOL 0x0f
+/* I/O - ADC/DAC/DMIC */
+#define RT3261_DAC1_DIG_VOL 0x19
+#define RT3261_DAC2_DIG_VOL 0x1a
+#define RT3261_DAC2_CTRL 0x1b
+#define RT3261_ADC_DIG_VOL 0x1c
+#define RT3261_ADC_DATA 0x1d
+#define RT3261_ADC_BST_VOL 0x1e
+/* Mixer - D-D */
+#define RT3261_STO_ADC_MIXER 0x27
+#define RT3261_MONO_ADC_MIXER 0x28
+#define RT3261_AD_DA_MIXER 0x29
+#define RT3261_STO_DAC_MIXER 0x2a
+#define RT3261_MONO_DAC_MIXER 0x2b
+#define RT3261_DIG_MIXER 0x2c
+#define RT3261_DSP_PATH1 0x2d
+#define RT3261_DSP_PATH2 0x2e
+#define RT3261_DIG_INF_DATA 0x2f
+/* Mixer - ADC */
+#define RT3261_REC_L1_MIXER 0x3b
+#define RT3261_REC_L2_MIXER 0x3c
+#define RT3261_REC_R1_MIXER 0x3d
+#define RT3261_REC_R2_MIXER 0x3e
+/* Mixer - DAC */
+#define RT3261_HPO_MIXER 0x45
+#define RT3261_SPK_L_MIXER 0x46
+#define RT3261_SPK_R_MIXER 0x47
+#define RT3261_SPO_L_MIXER 0x48
+#define RT3261_SPO_R_MIXER 0x49
+#define RT3261_SPO_CLSD_RATIO 0x4a
+#define RT3261_MONO_MIXER 0x4c
+#define RT3261_OUT_L1_MIXER 0x4d
+#define RT3261_OUT_L2_MIXER 0x4e
+#define RT3261_OUT_L3_MIXER 0x4f
+#define RT3261_OUT_R1_MIXER 0x50
+#define RT3261_OUT_R2_MIXER 0x51
+#define RT3261_OUT_R3_MIXER 0x52
+#define RT3261_LOUT_MIXER 0x53
+/* Power */
+#define RT3261_PWR_DIG1 0x61
+#define RT3261_PWR_DIG2 0x62
+#define RT3261_PWR_ANLG1 0x63
+#define RT3261_PWR_ANLG2 0x64
+#define RT3261_PWR_MIXER 0x65
+#define RT3261_PWR_VOL 0x66
+/* Private Register Control */
+#define RT3261_PRIV_INDEX 0x6a
+#define RT3261_PRIV_DATA 0x6c
+/* Format - ADC/DAC */
+#define RT3261_I2S1_SDP 0x70
+#define RT3261_I2S2_SDP 0x71
+#define RT3261_I2S3_SDP 0x72
+#define RT3261_ADDA_CLK1 0x73
+#define RT3261_ADDA_CLK2 0x74
+#define RT3261_DMIC 0x75
+/* Function - Analog */
+#define RT3261_GLB_CLK 0x80
+#define RT3261_PLL_CTRL1 0x81
+#define RT3261_PLL_CTRL2 0x82
+#define RT3261_ASRC_1 0x83
+#define RT3261_ASRC_2 0x84
+#define RT3261_ASRC_3 0x85
+#define RT3261_ASRC_4 0x89
+#define RT3261_ASRC_5 0x8a
+#define RT3261_HP_OVCD 0x8b
+#define RT3261_CLS_D_OVCD 0x8c
+#define RT3261_CLS_D_OUT 0x8d
+#define RT3261_DEPOP_M1 0x8e
+#define RT3261_DEPOP_M2 0x8f
+#define RT3261_DEPOP_M3 0x90
+#define RT3261_CHARGE_PUMP 0x91
+#define RT3261_PV_DET_SPK_G 0x92
+#define RT3261_MICBIAS 0x93
+/* Function - Digital */
+#define RT3261_EQ_CTRL1 0xb0
+#define RT3261_EQ_CTRL2 0xb1
+#define RT3261_WIND_FILTER 0xb2
+#define RT3261_DRC_AGC_1 0xb4
+#define RT3261_DRC_AGC_2 0xb5
+#define RT3261_DRC_AGC_3 0xb6
+#define RT3261_SVOL_ZC 0xb7
+#define RT3261_ANC_CTRL1 0xb8
+#define RT3261_ANC_CTRL2 0xb9
+#define RT3261_ANC_CTRL3 0xba
+#define RT3261_JD_CTRL 0xbb
+#define RT3261_ANC_JD 0xbc
+#define RT3261_IRQ_CTRL1 0xbd
+#define RT3261_IRQ_CTRL2 0xbe
+#define RT3261_INT_IRQ_ST 0xbf
+#define RT3261_GPIO_CTRL1 0xc0
+#define RT3261_GPIO_CTRL2 0xc1
+#define RT3261_GPIO_CTRL3 0xc2
+#define RT3261_DSP_CTRL1 0xc4
+#define RT3261_DSP_CTRL2 0xc5
+#define RT3261_DSP_CTRL3 0xc6
+#define RT3261_DSP_CTRL4 0xc7
+#define RT3261_PGM_REG_ARR1 0xc8
+#define RT3261_PGM_REG_ARR2 0xc9
+#define RT3261_PGM_REG_ARR3 0xca
+#define RT3261_PGM_REG_ARR4 0xcb
+#define RT3261_PGM_REG_ARR5 0xcc
+#define RT3261_SCB_FUNC 0xcd
+#define RT3261_SCB_CTRL 0xce
+#define RT3261_BASE_BACK 0xcf
+#define RT3261_MP3_PLUS1 0xd0
+#define RT3261_MP3_PLUS2 0xd1
+#define RT3261_3D_HP 0xd2
+#define RT3261_ADJ_HPF 0xd3
+#define RT3261_HP_CALIB_AMP_DET 0xd6
+#define RT3261_HP_CALIB2 0xd7
+#define RT3261_SV_ZCD1 0xd9
+#define RT3261_SV_ZCD2 0xda
+/* General Control */
+#define RT3261_GEN_CTRL1 0xfa
+#define RT3261_GEN_CTRL2 0xfb
+#define RT3261_GEN_CTRL3 0xfc
+
+
+/* Index of Codec Private Register definition */
+#define RT3261_BIAS_CUR1 0x12
+#define RT3261_BIAS_CUR3 0x14
+#define RT3261_CLSD_INT_REG1 0x1c
+#define RT3261_MAMP_INT_REG2 0x37
+#define RT3261_CHOP_DAC_ADC 0x3d
+#define RT3261_MIXER_INT_REG 0x3f
+#define RT3261_3D_SPK 0x63
+#define RT3261_WND_1 0x6c
+#define RT3261_WND_2 0x6d
+#define RT3261_WND_3 0x6e
+#define RT3261_WND_4 0x6f
+#define RT3261_WND_5 0x70
+#define RT3261_WND_8 0x73
+#define RT3261_DIP_SPK_INF 0x75
+#define RT3261_HP_DCC_INT1 0x77
+#define RT3261_EQ_BW_LOP 0xa0
+#define RT3261_EQ_GN_LOP 0xa1
+#define RT3261_EQ_FC_BP1 0xa2
+#define RT3261_EQ_BW_BP1 0xa3
+#define RT3261_EQ_GN_BP1 0xa4
+#define RT3261_EQ_FC_BP2 0xa5
+#define RT3261_EQ_BW_BP2 0xa6
+#define RT3261_EQ_GN_BP2 0xa7
+#define RT3261_EQ_FC_BP3 0xa8
+#define RT3261_EQ_BW_BP3 0xa9
+#define RT3261_EQ_GN_BP3 0xaa
+#define RT3261_EQ_FC_BP4 0xab
+#define RT3261_EQ_BW_BP4 0xac
+#define RT3261_EQ_GN_BP4 0xad
+#define RT3261_EQ_FC_HIP1 0xae
+#define RT3261_EQ_GN_HIP1 0xaf
+#define RT3261_EQ_FC_HIP2 0xb0
+#define RT3261_EQ_BW_HIP2 0xb1
+#define RT3261_EQ_GN_HIP2 0xb2
+#define RT3261_EQ_PRE_VOL 0xb3
+#define RT3261_EQ_PST_VOL 0xb4
+
+
+/* global definition */
+#define RT3261_L_MUTE (0x1 << 15)
+#define RT3261_L_MUTE_SFT 15
+#define RT3261_VOL_L_MUTE (0x1 << 14)
+#define RT3261_VOL_L_SFT 14
+#define RT3261_R_MUTE (0x1 << 7)
+#define RT3261_R_MUTE_SFT 7
+#define RT3261_VOL_R_MUTE (0x1 << 6)
+#define RT3261_VOL_R_SFT 6
+#define RT3261_L_VOL_MASK (0x3f << 8)
+#define RT3261_L_VOL_SFT 8
+#define RT3261_R_VOL_MASK (0x3f)
+#define RT3261_R_VOL_SFT 0
+
+/* IN1 and IN2 Control (0x0d) */
+/* IN3 and IN4 Control (0x0e) */
+#define RT3261_BST_MASK1 (0xf<<12)
+#define RT3261_BST_SFT1 12
+#define RT3261_BST_MASK2 (0xf<<8)
+#define RT3261_BST_SFT2 8
+#define RT3261_IN_DF1 (0x1 << 7)
+#define RT3261_IN_SFT1 7
+#define RT3261_IN_DF2 (0x1 << 6)
+#define RT3261_IN_SFT2 6
+
+/* INL and INR Volume Control (0x0f) */
+#define RT3261_INL_SEL_MASK (0x1 << 15)
+#define RT3261_INL_SEL_SFT 15
+#define RT3261_INL_SEL_IN4P (0x0 << 15)
+#define RT3261_INL_SEL_MONOP (0x1 << 15)
+#define RT3261_INL_VOL_MASK (0x1f << 8)
+#define RT3261_INL_VOL_SFT 8
+#define RT3261_INR_SEL_MASK (0x1 << 7)
+#define RT3261_INR_SEL_SFT 7
+#define RT3261_INR_SEL_IN4N (0x0 << 7)
+#define RT3261_INR_SEL_MONON (0x1 << 7)
+#define RT3261_INR_VOL_MASK (0x1f)
+#define RT3261_INR_VOL_SFT 0
+
+/* DAC1 Digital Volume (0x19) */
+#define RT3261_DAC_L1_VOL_MASK (0xff << 8)
+#define RT3261_DAC_L1_VOL_SFT 8
+#define RT3261_DAC_R1_VOL_MASK (0xff)
+#define RT3261_DAC_R1_VOL_SFT 0
+
+/* DAC2 Digital Volume (0x1a) */
+#define RT3261_DAC_L2_VOL_MASK (0xff << 8)
+#define RT3261_DAC_L2_VOL_SFT 8
+#define RT3261_DAC_R2_VOL_MASK (0xff)
+#define RT3261_DAC_R2_VOL_SFT 0
+
+/* DAC2 Control (0x1b) */
+#define RT3261_M_DAC_L2_VOL (0x1 << 13)
+#define RT3261_M_DAC_L2_VOL_SFT 13
+#define RT3261_M_DAC_R2_VOL (0x1 << 12)
+#define RT3261_M_DAC_R2_VOL_SFT 12
+
+/* ADC Digital Volume Control (0x1c) */
+#define RT3261_ADC_L_VOL_MASK (0x7f << 8)
+#define RT3261_ADC_L_VOL_SFT 8
+#define RT3261_ADC_R_VOL_MASK (0x7f)
+#define RT3261_ADC_R_VOL_SFT 0
+
+/* Mono ADC Digital Volume Control (0x1d) */
+#define RT3261_MONO_ADC_L_VOL_MASK (0x7f << 8)
+#define RT3261_MONO_ADC_L_VOL_SFT 8
+#define RT3261_MONO_ADC_R_VOL_MASK (0x7f)
+#define RT3261_MONO_ADC_R_VOL_SFT 0
+
+/* ADC Boost Volume Control (0x1e) */
+#define RT3261_ADC_L_BST_MASK (0x3 << 14)
+#define RT3261_ADC_L_BST_SFT 14
+#define RT3261_ADC_R_BST_MASK (0x3 << 12)
+#define RT3261_ADC_R_BST_SFT 12
+#define RT3261_ADC_COMP_MASK (0x3 << 10)
+#define RT3261_ADC_COMP_SFT 10
+
+/* Stereo ADC Mixer Control (0x27) */
+#define RT3261_M_ADC_L1 (0x1 << 14)
+#define RT3261_M_ADC_L1_SFT 14
+#define RT3261_M_ADC_L2 (0x1 << 13)
+#define RT3261_M_ADC_L2_SFT 13
+#define RT3261_ADC_1_SRC_MASK (0x1 << 12)
+#define RT3261_ADC_1_SRC_SFT 12
+#define RT3261_ADC_1_SRC_ADC (0x1 << 12)
+#define RT3261_ADC_1_SRC_DACMIX (0x0 << 12)
+#define RT3261_ADC_2_SRC_MASK (0x3 << 10)
+#define RT3261_ADC_2_SRC_SFT 10
+#define RT3261_ADC_2_SRC_DMIC1 (0x0 << 10)
+#define RT3261_ADC_2_SRC_DMIC2 (0x1 << 10)
+#define RT3261_ADC_2_SRC_DACMIX (0x2 << 10)
+#define RT3261_M_ADC_R1 (0x1 << 6)
+#define RT3261_M_ADC_R1_SFT 6
+#define RT3261_M_ADC_R2 (0x1 << 5)
+#define RT3261_M_ADC_R2_SFT 5
+
+/* Mono ADC Mixer Control (0x28) */
+#define RT3261_M_MONO_ADC_L1 (0x1 << 14)
+#define RT3261_M_MONO_ADC_L1_SFT 14
+#define RT3261_M_MONO_ADC_L2 (0x1 << 13)
+#define RT3261_M_MONO_ADC_L2_SFT 13
+#define RT3261_MONO_ADC_L1_SRC_MASK (0x1 << 12)
+#define RT3261_MONO_ADC_L1_SRC_SFT 12
+#define RT3261_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
+#define RT3261_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
+#define RT3261_MONO_ADC_L2_SRC_MASK (0x3 << 10)
+#define RT3261_MONO_ADC_L2_SRC_SFT 10
+#define RT3261_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
+#define RT3261_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
+#define RT3261_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
+#define RT3261_M_MONO_ADC_R1 (0x1 << 6)
+#define RT3261_M_MONO_ADC_R1_SFT 6
+#define RT3261_M_MONO_ADC_R2 (0x1 << 5)
+#define RT3261_M_MONO_ADC_R2_SFT 5
+#define RT3261_MONO_ADC_R1_SRC_MASK (0x1 << 4)
+#define RT3261_MONO_ADC_R1_SRC_SFT 4
+#define RT3261_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
+#define RT3261_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
+#define RT3261_MONO_ADC_R2_SRC_MASK (0x3 << 2)
+#define RT3261_MONO_ADC_R2_SRC_SFT 2
+#define RT3261_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
+#define RT3261_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
+#define RT3261_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
+
+/* ADC Mixer to DAC Mixer Control (0x29) */
+#define RT3261_M_ADCMIX_L (0x1 << 15)
+#define RT3261_M_ADCMIX_L_SFT 15
+#define RT3261_M_IF1_DAC_L (0x1 << 14)
+#define RT3261_M_IF1_DAC_L_SFT 14
+#define RT3261_M_ADCMIX_R (0x1 << 7)
+#define RT3261_M_ADCMIX_R_SFT 7
+#define RT3261_M_IF1_DAC_R (0x1 << 6)
+#define RT3261_M_IF1_DAC_R_SFT 6
+
+/* Stereo DAC Mixer Control (0x2a) */
+#define RT3261_M_DAC_L1 (0x1 << 14)
+#define RT3261_M_DAC_L1_SFT 14
+#define RT3261_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
+#define RT3261_DAC_L1_STO_L_VOL_SFT 13
+#define RT3261_M_DAC_L2 (0x1 << 12)
+#define RT3261_M_DAC_L2_SFT 12
+#define RT3261_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
+#define RT3261_DAC_L2_STO_L_VOL_SFT 11
+#define RT3261_M_ANC_DAC_L (0x1 << 10)
+#define RT3261_M_ANC_DAC_L_SFT 10
+#define RT3261_M_DAC_R1 (0x1 << 6)
+#define RT3261_M_DAC_R1_SFT 6
+#define RT3261_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
+#define RT3261_DAC_R1_STO_R_VOL_SFT 5
+#define RT3261_M_DAC_R2 (0x1 << 4)
+#define RT3261_M_DAC_R2_SFT 4
+#define RT3261_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
+#define RT3261_DAC_R2_STO_R_VOL_SFT 3
+#define RT3261_M_ANC_DAC_R (0x1 << 2)
+#define RT3261_M_ANC_DAC_R_SFT 2
+
+/* Mono DAC Mixer Control (0x2b) */
+#define RT3261_M_DAC_L1_MONO_L (0x1 << 14)
+#define RT3261_M_DAC_L1_MONO_L_SFT 14
+#define RT3261_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
+#define RT3261_DAC_L1_MONO_L_VOL_SFT 13
+#define RT3261_M_DAC_L2_MONO_L (0x1 << 12)
+#define RT3261_M_DAC_L2_MONO_L_SFT 12
+#define RT3261_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
+#define RT3261_DAC_L2_MONO_L_VOL_SFT 11
+#define RT3261_M_DAC_R2_MONO_L (0x1 << 10)
+#define RT3261_M_DAC_R2_MONO_L_SFT 10
+#define RT3261_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
+#define RT3261_DAC_R2_MONO_L_VOL_SFT 9
+#define RT3261_M_DAC_R1_MONO_R (0x1 << 6)
+#define RT3261_M_DAC_R1_MONO_R_SFT 6
+#define RT3261_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
+#define RT3261_DAC_R1_MONO_R_VOL_SFT 5
+#define RT3261_M_DAC_R2_MONO_R (0x1 << 4)
+#define RT3261_M_DAC_R2_MONO_R_SFT 4
+#define RT3261_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
+#define RT3261_DAC_R2_MONO_R_VOL_SFT 3
+#define RT3261_M_DAC_L2_MONO_R (0x1 << 2)
+#define RT3261_M_DAC_L2_MONO_R_SFT 2
+#define RT3261_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
+#define RT3261_DAC_L2_MONO_R_VOL_SFT 1
+
+/* Digital Mixer Control (0x2c) */
+#define RT3261_M_STO_L_DAC_L (0x1 << 15)
+#define RT3261_M_STO_L_DAC_L_SFT 15
+#define RT3261_STO_L_DAC_L_VOL_MASK (0x1 << 14)
+#define RT3261_STO_L_DAC_L_VOL_SFT 14
+#define RT3261_M_DAC_L2_DAC_L (0x1 << 13)
+#define RT3261_M_DAC_L2_DAC_L_SFT 13
+#define RT3261_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
+#define RT3261_DAC_L2_DAC_L_VOL_SFT 12
+#define RT3261_M_STO_R_DAC_R (0x1 << 11)
+#define RT3261_M_STO_R_DAC_R_SFT 11
+#define RT3261_STO_R_DAC_R_VOL_MASK (0x1 << 10)
+#define RT3261_STO_R_DAC_R_VOL_SFT 10
+#define RT3261_M_DAC_R2_DAC_R (0x1 << 9)
+#define RT3261_M_DAC_R2_DAC_R_SFT 9
+#define RT3261_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
+#define RT3261_DAC_R2_DAC_R_VOL_SFT 8
+
+/* DSP Path Control 1 (0x2d) */
+#define RT3261_RXDP_SRC_MASK (0x1 << 15)
+#define RT3261_RXDP_SRC_SFT 15
+#define RT3261_RXDP_SRC_NOR (0x0 << 15)
+#define RT3261_RXDP_SRC_DIV3 (0x1 << 15)
+#define RT3261_TXDP_SRC_MASK (0x1 << 14)
+#define RT3261_TXDP_SRC_SFT 14
+#define RT3261_TXDP_SRC_NOR (0x0 << 14)
+#define RT3261_TXDP_SRC_DIV3 (0x1 << 14)
+
+/* DSP Path Control 2 (0x2e) */
+#define RT3261_DAC_L2_SEL_MASK (0x3 << 14)
+#define RT3261_DAC_L2_SEL_SFT 14
+#define RT3261_DAC_L2_SEL_IF2 (0x0 << 14)
+#define RT3261_DAC_L2_SEL_IF3 (0x1 << 14)
+#define RT3261_DAC_L2_SEL_TXDC (0x2 << 14)
+#define RT3261_DAC_L2_SEL_BASS (0x3 << 14)
+#define RT3261_DAC_R2_SEL_MASK (0x3 << 12)
+#define RT3261_DAC_R2_SEL_SFT 12
+#define RT3261_DAC_R2_SEL_IF2 (0x0 << 12)
+#define RT3261_DAC_R2_SEL_IF3 (0x1 << 12)
+#define RT3261_DAC_R2_SEL_TXDC (0x2 << 12)
+#define RT3261_IF2_ADC_L_SEL_MASK (0x1 << 11)
+#define RT3261_IF2_ADC_L_SEL_SFT 11
+#define RT3261_IF2_ADC_L_SEL_TXDP (0x0 << 11)
+#define RT3261_IF2_ADC_L_SEL_PASS (0x1 << 11)
+#define RT3261_IF2_ADC_R_SEL_MASK (0x1 << 10)
+#define RT3261_IF2_ADC_R_SEL_SFT 10
+#define RT3261_IF2_ADC_R_SEL_TXDP (0x0 << 10)
+#define RT3261_IF2_ADC_R_SEL_PASS (0x1 << 10)
+#define RT3261_RXDC_SEL_MASK (0x3 << 8)
+#define RT3261_RXDC_SEL_SFT 8
+#define RT3261_RXDC_SEL_NOR (0x0 << 8)
+#define RT3261_RXDC_SEL_L2R (0x1 << 8)
+#define RT3261_RXDC_SEL_R2L (0x2 << 8)
+#define RT3261_RXDC_SEL_SWAP (0x3 << 8)
+#define RT3261_RXDP_SEL_MASK (0x3 << 6)
+#define RT3261_RXDP_SEL_SFT 6
+#define RT3261_RXDP_SEL_NOR (0x0 << 6)
+#define RT3261_RXDP_SEL_L2R (0x1 << 6)
+#define RT3261_RXDP_SEL_R2L (0x2 << 6)
+#define RT3261_RXDP_SEL_SWAP (0x3 << 6)
+#define RT3261_TXDC_SEL_MASK (0x3 << 4)
+#define RT3261_TXDC_SEL_SFT 4
+#define RT3261_TXDC_SEL_NOR (0x0 << 4)
+#define RT3261_TXDC_SEL_L2R (0x1 << 4)
+#define RT3261_TXDC_SEL_R2L (0x2 << 4)
+#define RT3261_TXDC_SEL_SWAP (0x3 << 4)
+#define RT3261_TXDP_SEL_MASK (0x3 << 2)
+#define RT3261_TXDP_SEL_SFT 2
+#define RT3261_TXDP_SEL_NOR (0x0 << 2)
+#define RT3261_TXDP_SEL_L2R (0x1 << 2)
+#define RT3261_TXDP_SEL_R2L (0x2 << 2)
+#define RT3261_TRXDP_SEL_SWAP (0x3 << 2)
+
+/* Digital Interface Data Control (0x2f) */
+#define RT3261_IF1_DAC_SEL_MASK (0x3 << 14)
+#define RT3261_IF1_DAC_SEL_SFT 14
+#define RT3261_IF1_DAC_SEL_NOR (0x0 << 14)
+#define RT3261_IF1_DAC_SEL_L2R (0x1 << 14)
+#define RT3261_IF1_DAC_SEL_R2L (0x2 << 14)
+#define RT3261_IF1_DAC_SEL_SWAP (0x3 << 14)
+#define RT3261_IF1_ADC_SEL_MASK (0x3 << 12)
+#define RT3261_IF1_ADC_SEL_SFT 12
+#define RT3261_IF1_ADC_SEL_NOR (0x0 << 12)
+#define RT3261_IF1_ADC_SEL_L2R (0x1 << 12)
+#define RT3261_IF1_ADC_SEL_R2L (0x2 << 12)
+#define RT3261_IF1_ADC_SEL_SWAP (0x3 << 12)
+#define RT3261_IF2_DAC_SEL_MASK (0x3 << 10)
+#define RT3261_IF2_DAC_SEL_SFT 10
+#define RT3261_IF2_DAC_SEL_NOR (0x0 << 10)
+#define RT3261_IF2_DAC_SEL_L2R (0x1 << 10)
+#define RT3261_IF2_DAC_SEL_R2L (0x2 << 10)
+#define RT3261_IF2_DAC_SEL_SWAP (0x3 << 10)
+#define RT3261_IF2_ADC_SEL_MASK (0x3 << 8)
+#define RT3261_IF2_ADC_SEL_SFT 8
+#define RT3261_IF2_ADC_SEL_NOR (0x0 << 8)
+#define RT3261_IF2_ADC_SEL_L2R (0x1 << 8)
+#define RT3261_IF2_ADC_SEL_R2L (0x2 << 8)
+#define RT3261_IF2_ADC_SEL_SWAP (0x3 << 8)
+#define RT3261_IF3_DAC_SEL_MASK (0x3 << 6)
+#define RT3261_IF3_DAC_SEL_SFT 6
+#define RT3261_IF3_DAC_SEL_NOR (0x0 << 6)
+#define RT3261_IF3_DAC_SEL_L2R (0x1 << 6)
+#define RT3261_IF3_DAC_SEL_R2L (0x2 << 6)
+#define RT3261_IF3_DAC_SEL_SWAP (0x3 << 6)
+#define RT3261_IF3_ADC_SEL_MASK (0x3 << 4)
+#define RT3261_IF3_ADC_SEL_SFT 4
+#define RT3261_IF3_ADC_SEL_NOR (0x0 << 4)
+#define RT3261_IF3_ADC_SEL_L2R (0x1 << 4)
+#define RT3261_IF3_ADC_SEL_R2L (0x2 << 4)
+#define RT3261_IF3_ADC_SEL_SWAP (0x3 << 4)
+
+/* REC Left Mixer Control 1 (0x3b) */
+#define RT3261_G_HP_L_RM_L_MASK (0x7 << 13)
+#define RT3261_G_HP_L_RM_L_SFT 13
+#define RT3261_G_IN_L_RM_L_MASK (0x7 << 10)
+#define RT3261_G_IN_L_RM_L_SFT 10
+#define RT3261_G_BST4_RM_L_MASK (0x7 << 7)
+#define RT3261_G_BST4_RM_L_SFT 7
+#define RT3261_G_BST3_RM_L_MASK (0x7 << 4)
+#define RT3261_G_BST3_RM_L_SFT 4
+#define RT3261_G_BST2_RM_L_MASK (0x7 << 1)
+#define RT3261_G_BST2_RM_L_SFT 1
+
+/* REC Left Mixer Control 2 (0x3c) */
+#define RT3261_G_BST1_RM_L_MASK (0x7 << 13)
+#define RT3261_G_BST1_RM_L_SFT 13
+#define RT3261_G_OM_L_RM_L_MASK (0x7 << 10)
+#define RT3261_G_OM_L_RM_L_SFT 10
+#define RT3261_M_HP_L_RM_L (0x1 << 6)
+#define RT3261_M_HP_L_RM_L_SFT 6
+#define RT3261_M_IN_L_RM_L (0x1 << 5)
+#define RT3261_M_IN_L_RM_L_SFT 5
+#define RT3261_M_BST4_RM_L (0x1 << 4)
+#define RT3261_M_BST4_RM_L_SFT 4
+#define RT3261_M_BST3_RM_L (0x1 << 3)
+#define RT3261_M_BST3_RM_L_SFT 3
+#define RT3261_M_BST2_RM_L (0x1 << 2)
+#define RT3261_M_BST2_RM_L_SFT 2
+#define RT3261_M_BST1_RM_L (0x1 << 1)
+#define RT3261_M_BST1_RM_L_SFT 1
+#define RT3261_M_OM_L_RM_L (0x1)
+#define RT3261_M_OM_L_RM_L_SFT 0
+
+/* REC Right Mixer Control 1 (0x3d) */
+#define RT3261_G_HP_R_RM_R_MASK (0x7 << 13)
+#define RT3261_G_HP_R_RM_R_SFT 13
+#define RT3261_G_IN_R_RM_R_MASK (0x7 << 10)
+#define RT3261_G_IN_R_RM_R_SFT 10
+#define RT3261_G_BST4_RM_R_MASK (0x7 << 7)
+#define RT3261_G_BST4_RM_R_SFT 7
+#define RT3261_G_BST3_RM_R_MASK (0x7 << 4)
+#define RT3261_G_BST3_RM_R_SFT 4
+#define RT3261_G_BST2_RM_R_MASK (0x7 << 1)
+#define RT3261_G_BST2_RM_R_SFT 1
+
+/* REC Right Mixer Control 2 (0x3e) */
+#define RT3261_G_BST1_RM_R_MASK (0x7 << 13)
+#define RT3261_G_BST1_RM_R_SFT 13
+#define RT3261_G_OM_R_RM_R_MASK (0x7 << 10)
+#define RT3261_G_OM_R_RM_R_SFT 10
+#define RT3261_M_HP_R_RM_R (0x1 << 6)
+#define RT3261_M_HP_R_RM_R_SFT 6
+#define RT3261_M_IN_R_RM_R (0x1 << 5)
+#define RT3261_M_IN_R_RM_R_SFT 5
+#define RT3261_M_BST4_RM_R (0x1 << 4)
+#define RT3261_M_BST4_RM_R_SFT 4
+#define RT3261_M_BST3_RM_R (0x1 << 3)
+#define RT3261_M_BST3_RM_R_SFT 3
+#define RT3261_M_BST2_RM_R (0x1 << 2)
+#define RT3261_M_BST2_RM_R_SFT 2
+#define RT3261_M_BST1_RM_R (0x1 << 1)
+#define RT3261_M_BST1_RM_R_SFT 1
+#define RT3261_M_OM_R_RM_R (0x1)
+#define RT3261_M_OM_R_RM_R_SFT 0
+
+/* HPMIX Control (0x45) */
+#define RT3261_M_DAC2_HM (0x1 << 15)
+#define RT3261_M_DAC2_HM_SFT 15
+#define RT3261_M_DAC1_HM (0x1 << 14)
+#define RT3261_M_DAC1_HM_SFT 14
+#define RT3261_M_HPVOL_HM (0x1 << 13)
+#define RT3261_M_HPVOL_HM_SFT 13
+#define RT3261_G_HPOMIX_MASK (0x1 << 12)
+#define RT3261_G_HPOMIX_SFT 12
+
+/* SPK Left Mixer Control (0x46) */
+#define RT3261_G_RM_L_SM_L_MASK (0x3 << 14)
+#define RT3261_G_RM_L_SM_L_SFT 14
+#define RT3261_G_IN_L_SM_L_MASK (0x3 << 12)
+#define RT3261_G_IN_L_SM_L_SFT 12
+#define RT3261_G_DAC_L1_SM_L_MASK (0x3 << 10)
+#define RT3261_G_DAC_L1_SM_L_SFT 10
+#define RT3261_G_DAC_L2_SM_L_MASK (0x3 << 8)
+#define RT3261_G_DAC_L2_SM_L_SFT 8
+#define RT3261_G_OM_L_SM_L_MASK (0x3 << 6)
+#define RT3261_G_OM_L_SM_L_SFT 6
+#define RT3261_M_RM_L_SM_L (0x1 << 5)
+#define RT3261_M_RM_L_SM_L_SFT 5
+#define RT3261_M_IN_L_SM_L (0x1 << 4)
+#define RT3261_M_IN_L_SM_L_SFT 4
+#define RT3261_M_DAC_L1_SM_L (0x1 << 3)
+#define RT3261_M_DAC_L1_SM_L_SFT 3
+#define RT3261_M_DAC_L2_SM_L (0x1 << 2)
+#define RT3261_M_DAC_L2_SM_L_SFT 2
+#define RT3261_M_OM_L_SM_L (0x1 << 1)
+#define RT3261_M_OM_L_SM_L_SFT 1
+
+/* SPK Right Mixer Control (0x47) */
+#define RT3261_G_RM_R_SM_R_MASK (0x3 << 14)
+#define RT3261_G_RM_R_SM_R_SFT 14
+#define RT3261_G_IN_R_SM_R_MASK (0x3 << 12)
+#define RT3261_G_IN_R_SM_R_SFT 12
+#define RT3261_G_DAC_R1_SM_R_MASK (0x3 << 10)
+#define RT3261_G_DAC_R1_SM_R_SFT 10
+#define RT3261_G_DAC_R2_SM_R_MASK (0x3 << 8)
+#define RT3261_G_DAC_R2_SM_R_SFT 8
+#define RT3261_G_OM_R_SM_R_MASK (0x3 << 6)
+#define RT3261_G_OM_R_SM_R_SFT 6
+#define RT3261_M_RM_R_SM_R (0x1 << 5)
+#define RT3261_M_RM_R_SM_R_SFT 5
+#define RT3261_M_IN_R_SM_R (0x1 << 4)
+#define RT3261_M_IN_R_SM_R_SFT 4
+#define RT3261_M_DAC_R1_SM_R (0x1 << 3)
+#define RT3261_M_DAC_R1_SM_R_SFT 3
+#define RT3261_M_DAC_R2_SM_R (0x1 << 2)
+#define RT3261_M_DAC_R2_SM_R_SFT 2
+#define RT3261_M_OM_R_SM_R (0x1 << 1)
+#define RT3261_M_OM_R_SM_R_SFT 1
+
+/* SPOLMIX Control (0x48) */
+#define RT3261_M_DAC_R1_SPM_L (0x1 << 15)
+#define RT3261_M_DAC_R1_SPM_L_SFT 15
+#define RT3261_M_DAC_L1_SPM_L (0x1 << 14)
+#define RT3261_M_DAC_L1_SPM_L_SFT 14
+#define RT3261_M_SV_R_SPM_L (0x1 << 13)
+#define RT3261_M_SV_R_SPM_L_SFT 13
+#define RT3261_M_SV_L_SPM_L (0x1 << 12)
+#define RT3261_M_SV_L_SPM_L_SFT 12
+#define RT3261_M_BST1_SPM_L (0x1 << 11)
+#define RT3261_M_BST1_SPM_L_SFT 11
+
+/* SPORMIX Control (0x49) */
+#define RT3261_M_DAC_R1_SPM_R (0x1 << 13)
+#define RT3261_M_DAC_R1_SPM_R_SFT 13
+#define RT3261_M_SV_R_SPM_R (0x1 << 12)
+#define RT3261_M_SV_R_SPM_R_SFT 12
+#define RT3261_M_BST1_SPM_R (0x1 << 11)
+#define RT3261_M_BST1_SPM_R_SFT 11
+
+/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
+#define RT3261_SPO_CLSD_RATIO_MASK (0x7)
+#define RT3261_SPO_CLSD_RATIO_SFT 0
+
+/* Mono Output Mixer Control (0x4c) */
+#define RT3261_M_DAC_R2_MM (0x1 << 15)
+#define RT3261_M_DAC_R2_MM_SFT 15
+#define RT3261_M_DAC_L2_MM (0x1 << 14)
+#define RT3261_M_DAC_L2_MM_SFT 14
+#define RT3261_M_OV_R_MM (0x1 << 13)
+#define RT3261_M_OV_R_MM_SFT 13
+#define RT3261_M_OV_L_MM (0x1 << 12)
+#define RT3261_M_OV_L_MM_SFT 12
+#define RT3261_M_BST1_MM (0x1 << 11)
+#define RT3261_M_BST1_MM_SFT 11
+#define RT3261_G_MONOMIX_MASK (0x1 << 10)
+#define RT3261_G_MONOMIX_SFT 10
+
+/* Output Left Mixer Control 1 (0x4d) */
+#define RT3261_G_BST3_OM_L_MASK (0x7 << 13)
+#define RT3261_G_BST3_OM_L_SFT 13
+#define RT3261_G_BST2_OM_L_MASK (0x7 << 10)
+#define RT3261_G_BST2_OM_L_SFT 10
+#define RT3261_G_BST1_OM_L_MASK (0x7 << 7)
+#define RT3261_G_BST1_OM_L_SFT 7
+#define RT3261_G_IN_L_OM_L_MASK (0x7 << 4)
+#define RT3261_G_IN_L_OM_L_SFT 4
+#define RT3261_G_RM_L_OM_L_MASK (0x7 << 1)
+#define RT3261_G_RM_L_OM_L_SFT 1
+
+/* Output Left Mixer Control 2 (0x4e) */
+#define RT3261_G_DAC_R2_OM_L_MASK (0x7 << 13)
+#define RT3261_G_DAC_R2_OM_L_SFT 13
+#define RT3261_G_DAC_L2_OM_L_MASK (0x7 << 10)
+#define RT3261_G_DAC_L2_OM_L_SFT 10
+#define RT3261_G_DAC_L1_OM_L_MASK (0x7 << 7)
+#define RT3261_G_DAC_L1_OM_L_SFT 7
+
+/* Output Left Mixer Control 3 (0x4f) */
+#define RT3261_M_SM_L_OM_L (0x1 << 8)
+#define RT3261_M_SM_L_OM_L_SFT 8
+#define RT3261_M_BST3_OM_L (0x1 << 7)
+#define RT3261_M_BST3_OM_L_SFT 7
+#define RT3261_M_BST2_OM_L (0x1 << 6)
+#define RT3261_M_BST2_OM_L_SFT 6
+#define RT3261_M_BST1_OM_L (0x1 << 5)
+#define RT3261_M_BST1_OM_L_SFT 5
+#define RT3261_M_IN_L_OM_L (0x1 << 4)
+#define RT3261_M_IN_L_OM_L_SFT 4
+#define RT3261_M_RM_L_OM_L (0x1 << 3)
+#define RT3261_M_RM_L_OM_L_SFT 3
+#define RT3261_M_DAC_R2_OM_L (0x1 << 2)
+#define RT3261_M_DAC_R2_OM_L_SFT 2
+#define RT3261_M_DAC_L2_OM_L (0x1 << 1)
+#define RT3261_M_DAC_L2_OM_L_SFT 1
+#define RT3261_M_DAC_L1_OM_L (0x1)
+#define RT3261_M_DAC_L1_OM_L_SFT 0
+
+/* Output Right Mixer Control 1 (0x50) */
+#define RT3261_G_BST4_OM_R_MASK (0x7 << 13)
+#define RT3261_G_BST4_OM_R_SFT 13
+#define RT3261_G_BST2_OM_R_MASK (0x7 << 10)
+#define RT3261_G_BST2_OM_R_SFT 10
+#define RT3261_G_BST1_OM_R_MASK (0x7 << 7)
+#define RT3261_G_BST1_OM_R_SFT 7
+#define RT3261_G_IN_R_OM_R_MASK (0x7 << 4)
+#define RT3261_G_IN_R_OM_R_SFT 4
+#define RT3261_G_RM_R_OM_R_MASK (0x7 << 1)
+#define RT3261_G_RM_R_OM_R_SFT 1
+
+/* Output Right Mixer Control 2 (0x51) */
+#define RT3261_G_DAC_L2_OM_R_MASK (0x7 << 13)
+#define RT3261_G_DAC_L2_OM_R_SFT 13
+#define RT3261_G_DAC_R2_OM_R_MASK (0x7 << 10)
+#define RT3261_G_DAC_R2_OM_R_SFT 10
+#define RT3261_G_DAC_R1_OM_R_MASK (0x7 << 7)
+#define RT3261_G_DAC_R1_OM_R_SFT 7
+
+/* Output Right Mixer Control 3 (0x52) */
+#define RT3261_M_SM_L_OM_R (0x1 << 8)
+#define RT3261_M_SM_L_OM_R_SFT 8
+#define RT3261_M_BST4_OM_R (0x1 << 7)
+#define RT3261_M_BST4_OM_R_SFT 7
+#define RT3261_M_BST2_OM_R (0x1 << 6)
+#define RT3261_M_BST2_OM_R_SFT 6
+#define RT3261_M_BST1_OM_R (0x1 << 5)
+#define RT3261_M_BST1_OM_R_SFT 5
+#define RT3261_M_IN_R_OM_R (0x1 << 4)
+#define RT3261_M_IN_R_OM_R_SFT 4
+#define RT3261_M_RM_R_OM_R (0x1 << 3)
+#define RT3261_M_RM_R_OM_R_SFT 3
+#define RT3261_M_DAC_L2_OM_R (0x1 << 2)
+#define RT3261_M_DAC_L2_OM_R_SFT 2
+#define RT3261_M_DAC_R2_OM_R (0x1 << 1)
+#define RT3261_M_DAC_R2_OM_R_SFT 1
+#define RT3261_M_DAC_R1_OM_R (0x1)
+#define RT3261_M_DAC_R1_OM_R_SFT 0
+
+/* LOUT Mixer Control (0x53) */
+#define RT3261_M_DAC_L1_LM (0x1 << 15)
+#define RT3261_M_DAC_L1_LM_SFT 15
+#define RT3261_M_DAC_R1_LM (0x1 << 14)
+#define RT3261_M_DAC_R1_LM_SFT 14
+#define RT3261_M_OV_L_LM (0x1 << 13)
+#define RT3261_M_OV_L_LM_SFT 13
+#define RT3261_M_OV_R_LM (0x1 << 12)
+#define RT3261_M_OV_R_LM_SFT 12
+#define RT3261_G_LOUTMIX_MASK (0x1 << 11)
+#define RT3261_G_LOUTMIX_SFT 11
+
+/* Power Management for Digital 1 (0x61) */
+#define RT3261_PWR_I2S1 (0x1 << 15)
+#define RT3261_PWR_I2S1_BIT 15
+#define RT3261_PWR_I2S2 (0x1 << 14)
+#define RT3261_PWR_I2S2_BIT 14
+#define RT3261_PWR_I2S3 (0x1 << 13)
+#define RT3261_PWR_I2S3_BIT 13
+#define RT3261_PWR_DAC_L1 (0x1 << 12)
+#define RT3261_PWR_DAC_L1_BIT 12
+#define RT3261_PWR_DAC_R1 (0x1 << 11)
+#define RT3261_PWR_DAC_R1_BIT 11
+#define RT3261_PWR_DAC_L2 (0x1 << 7)
+#define RT3261_PWR_DAC_L2_BIT 7
+#define RT3261_PWR_DAC_R2 (0x1 << 6)
+#define RT3261_PWR_DAC_R2_BIT 6
+#define RT3261_PWR_ADC_L (0x1 << 2)
+#define RT3261_PWR_ADC_L_BIT 2
+#define RT3261_PWR_ADC_R (0x1 << 1)
+#define RT3261_PWR_ADC_R_BIT 1
+#define RT3261_PWR_CLS_D (0x1)
+#define RT3261_PWR_CLS_D_BIT 0
+
+/* Power Management for Digital 2 (0x62) */
+#define RT3261_PWR_ADC_SF (0x1 << 15)
+#define RT3261_PWR_ADC_SF_BIT 15
+#define RT3261_PWR_ADC_MF_L (0x1 << 14)
+#define RT3261_PWR_ADC_MF_L_BIT 14
+#define RT3261_PWR_ADC_MF_R (0x1 << 13)
+#define RT3261_PWR_ADC_MF_R_BIT 13
+#define RT3261_PWR_I2S_DSP (0x1 << 12)
+#define RT3261_PWR_I2S_DSP_BIT 12
+
+/* Power Management for Analog 1 (0x63) */
+#define RT3261_PWR_VREF1 (0x1 << 15)
+#define RT3261_PWR_VREF1_BIT 15
+#define RT3261_PWR_FV1 (0x1 << 14)
+#define RT3261_PWR_FV1_BIT 14
+#define RT3261_PWR_MB (0x1 << 13)
+#define RT3261_PWR_MB_BIT 13
+#define RT3261_PWR_LM (0x1 << 12)
+#define RT3261_PWR_LM_BIT 12
+#define RT3261_PWR_BG (0x1 << 11)
+#define RT3261_PWR_BG_BIT 11
+#define RT3261_PWR_MM (0x1 << 10)
+#define RT3261_PWR_MM_BIT 10
+#define RT3261_PWR_MA (0x1 << 8)
+#define RT3261_PWR_MA_BIT 8
+#define RT3261_PWR_HP_L (0x1 << 7)
+#define RT3261_PWR_HP_L_BIT 7
+#define RT3261_PWR_HP_R (0x1 << 6)
+#define RT3261_PWR_HP_R_BIT 6
+#define RT3261_PWR_HA (0x1 << 5)
+#define RT3261_PWR_HA_BIT 5
+#define RT3261_PWR_VREF2 (0x1 << 4)
+#define RT3261_PWR_VREF2_BIT 4
+#define RT3261_PWR_FV2 (0x1 << 3)
+#define RT3261_PWR_FV2_BIT 3
+#define RT3261_PWR_LDO2 (0x1 << 2)
+#define RT3261_PWR_LDO2_BIT 2
+
+/* Power Management for Analog 2 (0x64) */
+#define RT3261_PWR_BST1 (0x1 << 15)
+#define RT3261_PWR_BST1_BIT 15
+#define RT3261_PWR_BST2 (0x1 << 14)
+#define RT3261_PWR_BST2_BIT 14
+#define RT3261_PWR_BST3 (0x1 << 13)
+#define RT3261_PWR_BST3_BIT 13
+#define RT3261_PWR_BST4 (0x1 << 12)
+#define RT3261_PWR_BST4_BIT 12
+#define RT3261_PWR_MB1 (0x1 << 11)
+#define RT3261_PWR_MB1_BIT 11
+#define RT3261_PWR_MB2 (0x1 << 10)
+#define RT3261_PWR_MB2_BIT 10
+#define RT3261_PWR_PLL (0x1 << 9)
+#define RT3261_PWR_PLL_BIT 9
+
+/* Power Management for Mixer (0x65) */
+#define RT3261_PWR_OM_L (0x1 << 15)
+#define RT3261_PWR_OM_L_BIT 15
+#define RT3261_PWR_OM_R (0x1 << 14)
+#define RT3261_PWR_OM_R_BIT 14
+#define RT3261_PWR_SM_L (0x1 << 13)
+#define RT3261_PWR_SM_L_BIT 13
+#define RT3261_PWR_SM_R (0x1 << 12)
+#define RT3261_PWR_SM_R_BIT 12
+#define RT3261_PWR_RM_L (0x1 << 11)
+#define RT3261_PWR_RM_L_BIT 11
+#define RT3261_PWR_RM_R (0x1 << 10)
+#define RT3261_PWR_RM_R_BIT 10
+
+/* Power Management for Volume (0x66) */
+#define RT3261_PWR_SV_L (0x1 << 15)
+#define RT3261_PWR_SV_L_BIT 15
+#define RT3261_PWR_SV_R (0x1 << 14)
+#define RT3261_PWR_SV_R_BIT 14
+#define RT3261_PWR_OV_L (0x1 << 13)
+#define RT3261_PWR_OV_L_BIT 13
+#define RT3261_PWR_OV_R (0x1 << 12)
+#define RT3261_PWR_OV_R_BIT 12
+#define RT3261_PWR_HV_L (0x1 << 11)
+#define RT3261_PWR_HV_L_BIT 11
+#define RT3261_PWR_HV_R (0x1 << 10)
+#define RT3261_PWR_HV_R_BIT 10
+#define RT3261_PWR_IN_L (0x1 << 9)
+#define RT3261_PWR_IN_L_BIT 9
+#define RT3261_PWR_IN_R (0x1 << 8)
+#define RT3261_PWR_IN_R_BIT 8
+
+/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
+#define RT3261_I2S_MS_MASK (0x1 << 15)
+#define RT3261_I2S_MS_SFT 15
+#define RT3261_I2S_MS_M (0x0 << 15)
+#define RT3261_I2S_MS_S (0x1 << 15)
+#define RT3261_I2S_IF_MASK (0x7 << 12)
+#define RT3261_I2S_IF_SFT 12
+#define RT3261_I2S_O_CP_MASK (0x3 << 10)
+#define RT3261_I2S_O_CP_SFT 10
+#define RT3261_I2S_O_CP_OFF (0x0 << 10)
+#define RT3261_I2S_O_CP_U_LAW (0x1 << 10)
+#define RT3261_I2S_O_CP_A_LAW (0x2 << 10)
+#define RT3261_I2S_I_CP_MASK (0x3 << 8)
+#define RT3261_I2S_I_CP_SFT 8
+#define RT3261_I2S_I_CP_OFF (0x0 << 8)
+#define RT3261_I2S_I_CP_U_LAW (0x1 << 8)
+#define RT3261_I2S_I_CP_A_LAW (0x2 << 8)
+#define RT3261_I2S_BP_MASK (0x1 << 7)
+#define RT3261_I2S_BP_SFT 7
+#define RT3261_I2S_BP_NOR (0x0 << 7)
+#define RT3261_I2S_BP_INV (0x1 << 7)
+#define RT3261_I2S_DL_MASK (0x3 << 2)
+#define RT3261_I2S_DL_SFT 2
+#define RT3261_I2S_DL_16 (0x0 << 2)
+#define RT3261_I2S_DL_20 (0x1 << 2)
+#define RT3261_I2S_DL_24 (0x2 << 2)
+#define RT3261_I2S_DL_8 (0x3 << 2)
+#define RT3261_I2S_DF_MASK (0x3)
+#define RT3261_I2S_DF_SFT 0
+#define RT3261_I2S_DF_I2S (0x0)
+#define RT3261_I2S_DF_LEFT (0x1)
+#define RT3261_I2S_DF_PCM_A (0x2)
+#define RT3261_I2S_DF_PCM_B (0x3)
+
+/* I2S2 Audio Serial Data Port Control (0x71) */
+#define RT3261_I2S2_SDI_MASK (0x1 << 6)
+#define RT3261_I2S2_SDI_SFT 6
+#define RT3261_I2S2_SDI_I2S1 (0x0 << 6)
+#define RT3261_I2S2_SDI_I2S2 (0x1 << 6)
+
+/* ADC/DAC Clock Control 1 (0x73) */
+#define RT3261_I2S_BCLK_MS1_MASK (0x1 << 15)
+#define RT3261_I2S_BCLK_MS1_SFT 15
+#define RT3261_I2S_BCLK_MS1_32 (0x0 << 15)
+#define RT3261_I2S_BCLK_MS1_64 (0x1 << 15)
+#define RT3261_I2S_PD1_MASK (0x7 << 12)
+#define RT3261_I2S_PD1_SFT 12
+#define RT3261_I2S_PD1_1 (0x0 << 12)
+#define RT3261_I2S_PD1_2 (0x1 << 12)
+#define RT3261_I2S_PD1_3 (0x2 << 12)
+#define RT3261_I2S_PD1_4 (0x3 << 12)
+#define RT3261_I2S_PD1_6 (0x4 << 12)
+#define RT3261_I2S_PD1_8 (0x5 << 12)
+#define RT3261_I2S_PD1_12 (0x6 << 12)
+#define RT3261_I2S_PD1_16 (0x7 << 12)
+#define RT3261_I2S_BCLK_MS2_MASK (0x1 << 11)
+#define RT3261_I2S_BCLK_MS2_SFT 11
+#define RT3261_I2S_BCLK_MS2_32 (0x0 << 11)
+#define RT3261_I2S_BCLK_MS2_64 (0x1 << 11)
+#define RT3261_I2S_PD2_MASK (0x7 << 8)
+#define RT3261_I2S_PD2_SFT 8
+#define RT3261_I2S_PD2_1 (0x0 << 8)
+#define RT3261_I2S_PD2_2 (0x1 << 8)
+#define RT3261_I2S_PD2_3 (0x2 << 8)
+#define RT3261_I2S_PD2_4 (0x3 << 8)
+#define RT3261_I2S_PD2_6 (0x4 << 8)
+#define RT3261_I2S_PD2_8 (0x5 << 8)
+#define RT3261_I2S_PD2_12 (0x6 << 8)
+#define RT3261_I2S_PD2_16 (0x7 << 8)
+#define RT3261_I2S_BCLK_MS3_MASK (0x1 << 7)
+#define RT3261_I2S_BCLK_MS3_SFT 7
+#define RT3261_I2S_BCLK_MS3_32 (0x0 << 7)
+#define RT3261_I2S_BCLK_MS3_64 (0x1 << 7)
+#define RT3261_I2S_PD3_MASK (0x7 << 4)
+#define RT3261_I2S_PD3_SFT 4
+#define RT3261_I2S_PD3_1 (0x0 << 4)
+#define RT3261_I2S_PD3_2 (0x1 << 4)
+#define RT3261_I2S_PD3_3 (0x2 << 4)
+#define RT3261_I2S_PD3_4 (0x3 << 4)
+#define RT3261_I2S_PD3_6 (0x4 << 4)
+#define RT3261_I2S_PD3_8 (0x5 << 4)
+#define RT3261_I2S_PD3_12 (0x6 << 4)
+#define RT3261_I2S_PD3_16 (0x7 << 4)
+#define RT3261_DAC_OSR_MASK (0x3 << 2)
+#define RT3261_DAC_OSR_SFT 2
+#define RT3261_DAC_OSR_128 (0x0 << 2)
+#define RT3261_DAC_OSR_64 (0x1 << 2)
+#define RT3261_DAC_OSR_32 (0x2 << 2)
+#define RT3261_DAC_OSR_16 (0x3 << 2)
+#define RT3261_ADC_OSR_MASK (0x3)
+#define RT3261_ADC_OSR_SFT 0
+#define RT3261_ADC_OSR_128 (0x0)
+#define RT3261_ADC_OSR_64 (0x1)
+#define RT3261_ADC_OSR_32 (0x2)
+#define RT3261_ADC_OSR_16 (0x3)
+
+/* ADC/DAC Clock Control 2 (0x74) */
+#define RT3261_DAC_L_OSR_MASK (0x3 << 14)
+#define RT3261_DAC_L_OSR_SFT 14
+#define RT3261_DAC_L_OSR_128 (0x0 << 14)
+#define RT3261_DAC_L_OSR_64 (0x1 << 14)
+#define RT3261_DAC_L_OSR_32 (0x2 << 14)
+#define RT3261_DAC_L_OSR_16 (0x3 << 14)
+#define RT3261_ADC_R_OSR_MASK (0x3 << 12)
+#define RT3261_ADC_R_OSR_SFT 12
+#define RT3261_ADC_R_OSR_128 (0x0 << 12)
+#define RT3261_ADC_R_OSR_64 (0x1 << 12)
+#define RT3261_ADC_R_OSR_32 (0x2 << 12)
+#define RT3261_ADC_R_OSR_16 (0x3 << 12)
+#define RT3261_DAHPF_EN (0x1 << 11)
+#define RT3261_DAHPF_EN_SFT 11
+#define RT3261_ADHPF_EN (0x1 << 10)
+#define RT3261_ADHPF_EN_SFT 10
+
+/* Digital Microphone Control (0x75) */
+#define RT3261_DMIC_1_EN_MASK (0x1 << 15)
+#define RT3261_DMIC_1_EN_SFT 15
+#define RT3261_DMIC_1_DIS (0x0 << 15)
+#define RT3261_DMIC_1_EN (0x1 << 15)
+#define RT3261_DMIC_2_EN_MASK (0x1 << 14)
+#define RT3261_DMIC_2_EN_SFT 14
+#define RT3261_DMIC_2_DIS (0x0 << 14)
+#define RT3261_DMIC_2_EN (0x1 << 14)
+#define RT3261_DMIC_1L_LH_MASK (0x1 << 13)
+#define RT3261_DMIC_1L_LH_SFT 13
+#define RT3261_DMIC_1L_LH_FALLING (0x0 << 13)
+#define RT3261_DMIC_1L_LH_RISING (0x1 << 13)
+#define RT3261_DMIC_1R_LH_MASK (0x1 << 12)
+#define RT3261_DMIC_1R_LH_SFT 12
+#define RT3261_DMIC_1R_LH_FALLING (0x0 << 12)
+#define RT3261_DMIC_1R_LH_RISING (0x1 << 12)
+#define RT3261_DMIC_1_DP_MASK (0x1 << 11)
+#define RT3261_DMIC_1_DP_SFT 11
+#define RT3261_DMIC_1_DP_GPIO3 (0x0 << 11)
+#define RT3261_DMIC_1_DP_IN1P (0x1 << 11)
+#define RT3261_DMIC_2_DP_MASK (0x1 << 10)
+#define RT3261_DMIC_2_DP_SFT 10
+#define RT3261_DMIC_2_DP_GPIO4 (0x0 << 10)
+#define RT3261_DMIC_2_DP_IN1N (0x1 << 10)
+#define RT3261_DMIC_2L_LH_MASK (0x1 << 9)
+#define RT3261_DMIC_2L_LH_SFT 9
+#define RT3261_DMIC_2L_LH_FALLING (0x0 << 9)
+#define RT3261_DMIC_2L_LH_RISING (0x1 << 9)
+#define RT3261_DMIC_2R_LH_MASK (0x1 << 8)
+#define RT3261_DMIC_2R_LH_SFT 8
+#define RT3261_DMIC_2R_LH_FALLING (0x0 << 8)
+#define RT3261_DMIC_2R_LH_RISING (0x1 << 8)
+#define RT3261_DMIC_CLK_MASK (0x7 << 5)
+#define RT3261_DMIC_CLK_SFT 5
+
+/* Global Clock Control (0x80) */
+#define RT3261_SCLK_SRC_MASK (0x3 << 14)
+#define RT3261_SCLK_SRC_SFT 14
+#define RT3261_SCLK_SRC_MCLK (0x0 << 14)
+#define RT3261_SCLK_SRC_PLL1 (0x1 << 14)
+#define RT3261_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
+#define RT3261_PLL1_SRC_MASK (0x3 << 12)
+#define RT3261_PLL1_SRC_SFT 12
+#define RT3261_PLL1_SRC_MCLK (0x0 << 12)
+#define RT3261_PLL1_SRC_BCLK1 (0x1 << 12)
+#define RT3261_PLL1_SRC_BCLK2 (0x2 << 12)
+#define RT3261_PLL1_SRC_BCLK3 (0x3 << 12)
+#define RT3261_PLL1_PD_MASK (0x1 << 3)
+#define RT3261_PLL1_PD_SFT 3
+#define RT3261_PLL1_PD_1 (0x0 << 3)
+#define RT3261_PLL1_PD_2 (0x1 << 3)
+
+#define RT3261_PLL_INP_MAX 40000000
+#define RT3261_PLL_INP_MIN 256000
+/* PLL M/N/K Code Control 1 (0x81) */
+#define RT3261_PLL_N_MAX 0x1ff
+#define RT3261_PLL_N_MASK (RT3261_PLL_N_MAX << 7)
+#define RT3261_PLL_N_SFT 7
+#define RT3261_PLL_K_MAX 0x1f
+#define RT3261_PLL_K_MASK (RT3261_PLL_K_MAX)
+#define RT3261_PLL_K_SFT 0
+
+/* PLL M/N/K Code Control 2 (0x82) */
+#define RT3261_PLL_M_MAX 0xf
+#define RT3261_PLL_M_MASK (RT3261_PLL_M_MAX << 12)
+#define RT3261_PLL_M_SFT 12
+#define RT3261_PLL_M_BP (0x1 << 11)
+#define RT3261_PLL_M_BP_SFT 11
+
+/* ASRC Control 1 (0x83) */
+#define RT3261_STO_T_MASK (0x1 << 15)
+#define RT3261_STO_T_SFT 15
+#define RT3261_STO_T_SCLK (0x0 << 15)
+#define RT3261_STO_T_LRCK1 (0x1 << 15)
+#define RT3261_M1_T_MASK (0x1 << 14)
+#define RT3261_M1_T_SFT 14
+#define RT3261_M1_T_I2S2 (0x0 << 14)
+#define RT3261_M1_T_I2S2_D3 (0x1 << 14)
+#define RT3261_I2S2_F_MASK (0x1 << 12)
+#define RT3261_I2S2_F_SFT 12
+#define RT3261_I2S2_F_I2S2_D2 (0x0 << 12)
+#define RT3261_I2S2_F_I2S1_TCLK (0x1 << 12)
+#define RT3261_DMIC_1_M_MASK (0x1 << 9)
+#define RT3261_DMIC_1_M_SFT 9
+#define RT3261_DMIC_1_M_NOR (0x0 << 9)
+#define RT3261_DMIC_1_M_ASYN (0x1 << 9)
+#define RT3261_DMIC_2_M_MASK (0x1 << 8)
+#define RT3261_DMIC_2_M_SFT 8
+#define RT3261_DMIC_2_M_NOR (0x0 << 8)
+#define RT3261_DMIC_2_M_ASYN (0x1 << 8)
+
+/* ASRC Control 2 (0x84) */
+#define RT3261_MDA_L_M_MASK (0x1 << 15)
+#define RT3261_MDA_L_M_SFT 15
+#define RT3261_MDA_L_M_NOR (0x0 << 15)
+#define RT3261_MDA_L_M_ASYN (0x1 << 15)
+#define RT3261_MDA_R_M_MASK (0x1 << 14)
+#define RT3261_MDA_R_M_SFT 14
+#define RT3261_MDA_R_M_NOR (0x0 << 14)
+#define RT3261_MDA_R_M_ASYN (0x1 << 14)
+#define RT3261_MAD_L_M_MASK (0x1 << 13)
+#define RT3261_MAD_L_M_SFT 13
+#define RT3261_MAD_L_M_NOR (0x0 << 13)
+#define RT3261_MAD_L_M_ASYN (0x1 << 13)
+#define RT3261_MAD_R_M_MASK (0x1 << 12)
+#define RT3261_MAD_R_M_SFT 12
+#define RT3261_MAD_R_M_NOR (0x0 << 12)
+#define RT3261_MAD_R_M_ASYN (0x1 << 12)
+#define RT3261_ADC_M_MASK (0x1 << 11)
+#define RT3261_ADC_M_SFT 11
+#define RT3261_ADC_M_NOR (0x0 << 11)
+#define RT3261_ADC_M_ASYN (0x1 << 11)
+#define RT3261_STO_DAC_M_MASK (0x1 << 5)
+#define RT3261_STO_DAC_M_SFT 5
+#define RT3261_STO_DAC_M_NOR (0x0 << 5)
+#define RT3261_STO_DAC_M_ASYN (0x1 << 5)
+#define RT3261_I2S1_R_D_MASK (0x1 << 4)
+#define RT3261_I2S1_R_D_SFT 4
+#define RT3261_I2S1_R_D_DIS (0x0 << 4)
+#define RT3261_I2S1_R_D_EN (0x1 << 4)
+#define RT3261_I2S2_R_D_MASK (0x1 << 3)
+#define RT3261_I2S2_R_D_SFT 3
+#define RT3261_I2S2_R_D_DIS (0x0 << 3)
+#define RT3261_I2S2_R_D_EN (0x1 << 3)
+#define RT3261_PRE_SCLK_MASK (0x3)
+#define RT3261_PRE_SCLK_SFT 0
+#define RT3261_PRE_SCLK_512 (0x0)
+#define RT3261_PRE_SCLK_1024 (0x1)
+#define RT3261_PRE_SCLK_2048 (0x2)
+
+/* ASRC Control 3 (0x85) */
+#define RT3261_I2S1_RATE_MASK (0xf << 12)
+#define RT3261_I2S1_RATE_SFT 12
+#define RT3261_I2S2_RATE_MASK (0xf << 8)
+#define RT3261_I2S2_RATE_SFT 8
+
+/* ASRC Control 4 (0x89) */
+#define RT3261_I2S1_PD_MASK (0x7 << 12)
+#define RT3261_I2S1_PD_SFT 12
+#define RT3261_I2S2_PD_MASK (0x7 << 8)
+#define RT3261_I2S2_PD_SFT 8
+
+/* HPOUT Over Current Detection (0x8b) */
+#define RT3261_HP_OVCD_MASK (0x1 << 10)
+#define RT3261_HP_OVCD_SFT 10
+#define RT3261_HP_OVCD_DIS (0x0 << 10)
+#define RT3261_HP_OVCD_EN (0x1 << 10)
+#define RT3261_HP_OC_TH_MASK (0x3 << 8)
+#define RT3261_HP_OC_TH_SFT 8
+#define RT3261_HP_OC_TH_90 (0x0 << 8)
+#define RT3261_HP_OC_TH_105 (0x1 << 8)
+#define RT3261_HP_OC_TH_120 (0x2 << 8)
+#define RT3261_HP_OC_TH_135 (0x3 << 8)
+
+/* Class D Over Current Control (0x8c) */
+#define RT3261_CLSD_OC_MASK (0x1 << 9)
+#define RT3261_CLSD_OC_SFT 9
+#define RT3261_CLSD_OC_PU (0x0 << 9)
+#define RT3261_CLSD_OC_PD (0x1 << 9)
+#define RT3261_AUTO_PD_MASK (0x1 << 8)
+#define RT3261_AUTO_PD_SFT 8
+#define RT3261_AUTO_PD_DIS (0x0 << 8)
+#define RT3261_AUTO_PD_EN (0x1 << 8)
+#define RT3261_CLSD_OC_TH_MASK (0x3f)
+#define RT3261_CLSD_OC_TH_SFT 0
+
+/* Class D Output Control (0x8d) */
+#define RT3261_CLSD_RATIO_MASK (0xf << 12)
+#define RT3261_CLSD_RATIO_SFT 12
+#define RT3261_CLSD_OM_MASK (0x1 << 11)
+#define RT3261_CLSD_OM_SFT 11
+#define RT3261_CLSD_OM_MONO (0x0 << 11)
+#define RT3261_CLSD_OM_STO (0x1 << 11)
+#define RT3261_CLSD_SCH_MASK (0x1 << 10)
+#define RT3261_CLSD_SCH_SFT 10
+#define RT3261_CLSD_SCH_L (0x0 << 10)
+#define RT3261_CLSD_SCH_S (0x1 << 10)
+
+/* Depop Mode Control 1 (0x8e) */
+#define RT3261_SMT_TRIG_MASK (0x1 << 15)
+#define RT3261_SMT_TRIG_SFT 15
+#define RT3261_SMT_TRIG_DIS (0x0 << 15)
+#define RT3261_SMT_TRIG_EN (0x1 << 15)
+#define RT3261_HP_L_SMT_MASK (0x1 << 9)
+#define RT3261_HP_L_SMT_SFT 9
+#define RT3261_HP_L_SMT_DIS (0x0 << 9)
+#define RT3261_HP_L_SMT_EN (0x1 << 9)
+#define RT3261_HP_R_SMT_MASK (0x1 << 8)
+#define RT3261_HP_R_SMT_SFT 8
+#define RT3261_HP_R_SMT_DIS (0x0 << 8)
+#define RT3261_HP_R_SMT_EN (0x1 << 8)
+#define RT3261_HP_CD_PD_MASK (0x1 << 7)
+#define RT3261_HP_CD_PD_SFT 7
+#define RT3261_HP_CD_PD_DIS (0x0 << 7)
+#define RT3261_HP_CD_PD_EN (0x1 << 7)
+#define RT3261_RSTN_MASK (0x1 << 6)
+#define RT3261_RSTN_SFT 6
+#define RT3261_RSTN_DIS (0x0 << 6)
+#define RT3261_RSTN_EN (0x1 << 6)
+#define RT3261_RSTP_MASK (0x1 << 5)
+#define RT3261_RSTP_SFT 5
+#define RT3261_RSTP_DIS (0x0 << 5)
+#define RT3261_RSTP_EN (0x1 << 5)
+#define RT3261_HP_CO_MASK (0x1 << 4)
+#define RT3261_HP_CO_SFT 4
+#define RT3261_HP_CO_DIS (0x0 << 4)
+#define RT3261_HP_CO_EN (0x1 << 4)
+#define RT3261_HP_CP_MASK (0x1 << 3)
+#define RT3261_HP_CP_SFT 3
+#define RT3261_HP_CP_PD (0x0 << 3)
+#define RT3261_HP_CP_PU (0x1 << 3)
+#define RT3261_HP_SG_MASK (0x1 << 2)
+#define RT3261_HP_SG_SFT 2
+#define RT3261_HP_SG_DIS (0x0 << 2)
+#define RT3261_HP_SG_EN (0x1 << 2)
+#define RT3261_HP_DP_MASK (0x1 << 1)
+#define RT3261_HP_DP_SFT 1
+#define RT3261_HP_DP_PD (0x0 << 1)
+#define RT3261_HP_DP_PU (0x1 << 1)
+#define RT3261_HP_CB_MASK (0x1)
+#define RT3261_HP_CB_SFT 0
+#define RT3261_HP_CB_PD (0x0)
+#define RT3261_HP_CB_PU (0x1)
+
+/* Depop Mode Control 2 (0x8f) */
+#define RT3261_DEPOP_MASK (0x1 << 13)
+#define RT3261_DEPOP_SFT 13
+#define RT3261_DEPOP_AUTO (0x0 << 13)
+#define RT3261_DEPOP_MAN (0x1 << 13)
+#define RT3261_RAMP_MASK (0x1 << 12)
+#define RT3261_RAMP_SFT 12
+#define RT3261_RAMP_DIS (0x0 << 12)
+#define RT3261_RAMP_EN (0x1 << 12)
+#define RT3261_BPS_MASK (0x1 << 11)
+#define RT3261_BPS_SFT 11
+#define RT3261_BPS_DIS (0x0 << 11)
+#define RT3261_BPS_EN (0x1 << 11)
+#define RT3261_FAST_UPDN_MASK (0x1 << 10)
+#define RT3261_FAST_UPDN_SFT 10
+#define RT3261_FAST_UPDN_DIS (0x0 << 10)
+#define RT3261_FAST_UPDN_EN (0x1 << 10)
+#define RT3261_MRES_MASK (0x3 << 8)
+#define RT3261_MRES_SFT 8
+#define RT3261_MRES_15MO (0x0 << 8)
+#define RT3261_MRES_25MO (0x1 << 8)
+#define RT3261_MRES_35MO (0x2 << 8)
+#define RT3261_MRES_45MO (0x3 << 8)
+#define RT3261_VLO_MASK (0x1 << 7)
+#define RT3261_VLO_SFT 7
+#define RT3261_VLO_3V (0x0 << 7)
+#define RT3261_VLO_32V (0x1 << 7)
+#define RT3261_DIG_DP_MASK (0x1 << 6)
+#define RT3261_DIG_DP_SFT 6
+#define RT3261_DIG_DP_DIS (0x0 << 6)
+#define RT3261_DIG_DP_EN (0x1 << 6)
+#define RT3261_DP_TH_MASK (0x3 << 4)
+#define RT3261_DP_TH_SFT 4
+
+/* Depop Mode Control 3 (0x90) */
+#define RT3261_CP_SYS_MASK (0x7 << 12)
+#define RT3261_CP_SYS_SFT 12
+#define RT3261_CP_FQ1_MASK (0x7 << 8)
+#define RT3261_CP_FQ1_SFT 8
+#define RT3261_CP_FQ2_MASK (0x7 << 4)
+#define RT3261_CP_FQ2_SFT 4
+#define RT3261_CP_FQ3_MASK (0x7)
+#define RT3261_CP_FQ3_SFT 0
+#define RT3261_CP_FQ_1_5_KHZ 0
+#define RT3261_CP_FQ_3_KHZ 1
+#define RT3261_CP_FQ_6_KHZ 2
+#define RT3261_CP_FQ_12_KHZ 3
+#define RT3261_CP_FQ_24_KHZ 4
+#define RT3261_CP_FQ_48_KHZ 5
+#define RT3261_CP_FQ_96_KHZ 6
+#define RT3261_CP_FQ_192_KHZ 7
+
+/* HPOUT charge pump (0x91) */
+#define RT3261_OSW_L_MASK (0x1 << 11)
+#define RT3261_OSW_L_SFT 11
+#define RT3261_OSW_L_DIS (0x0 << 11)
+#define RT3261_OSW_L_EN (0x1 << 11)
+#define RT3261_OSW_R_MASK (0x1 << 10)
+#define RT3261_OSW_R_SFT 10
+#define RT3261_OSW_R_DIS (0x0 << 10)
+#define RT3261_OSW_R_EN (0x1 << 10)
+#define RT3261_PM_HP_MASK (0x3 << 8)
+#define RT3261_PM_HP_SFT 8
+#define RT3261_PM_HP_LV (0x0 << 8)
+#define RT3261_PM_HP_MV (0x1 << 8)
+#define RT3261_PM_HP_HV (0x2 << 8)
+#define RT3261_IB_HP_MASK (0x3 << 6)
+#define RT3261_IB_HP_SFT 6
+#define RT3261_IB_HP_125IL (0x0 << 6)
+#define RT3261_IB_HP_25IL (0x1 << 6)
+#define RT3261_IB_HP_5IL (0x2 << 6)
+#define RT3261_IB_HP_1IL (0x3 << 6)
+
+/* PV detection and SPK gain control (0x92) */
+#define RT3261_PVDD_DET_MASK (0x1 << 15)
+#define RT3261_PVDD_DET_SFT 15
+#define RT3261_PVDD_DET_DIS (0x0 << 15)
+#define RT3261_PVDD_DET_EN (0x1 << 15)
+#define RT3261_SPK_AG_MASK (0x1 << 14)
+#define RT3261_SPK_AG_SFT 14
+#define RT3261_SPK_AG_DIS (0x0 << 14)
+#define RT3261_SPK_AG_EN (0x1 << 14)
+
+/* Micbias Control (0x93) */
+#define RT3261_MIC1_BS_MASK (0x1 << 15)
+#define RT3261_MIC1_BS_SFT 15
+#define RT3261_MIC1_BS_9AV (0x0 << 15)
+#define RT3261_MIC1_BS_75AV (0x1 << 15)
+#define RT3261_MIC2_BS_MASK (0x1 << 14)
+#define RT3261_MIC2_BS_SFT 14
+#define RT3261_MIC2_BS_9AV (0x0 << 14)
+#define RT3261_MIC2_BS_75AV (0x1 << 14)
+#define RT3261_MIC1_CLK_MASK (0x1 << 13)
+#define RT3261_MIC1_CLK_SFT 13
+#define RT3261_MIC1_CLK_DIS (0x0 << 13)
+#define RT3261_MIC1_CLK_EN (0x1 << 13)
+#define RT3261_MIC2_CLK_MASK (0x1 << 12)
+#define RT3261_MIC2_CLK_SFT 12
+#define RT3261_MIC2_CLK_DIS (0x0 << 12)
+#define RT3261_MIC2_CLK_EN (0x1 << 12)
+#define RT3261_MIC1_OVCD_MASK (0x1 << 11)
+#define RT3261_MIC1_OVCD_SFT 11
+#define RT3261_MIC1_OVCD_DIS (0x0 << 11)
+#define RT3261_MIC1_OVCD_EN (0x1 << 11)
+#define RT3261_MIC1_OVTH_MASK (0x3 << 9)
+#define RT3261_MIC1_OVTH_SFT 9
+#define RT3261_MIC1_OVTH_600UA (0x0 << 9)
+#define RT3261_MIC1_OVTH_1500UA (0x1 << 9)
+#define RT3261_MIC1_OVTH_2000UA (0x2 << 9)
+#define RT3261_MIC2_OVCD_MASK (0x1 << 8)
+#define RT3261_MIC2_OVCD_SFT 8
+#define RT3261_MIC2_OVCD_DIS (0x0 << 8)
+#define RT3261_MIC2_OVCD_EN (0x1 << 8)
+#define RT3261_MIC2_OVTH_MASK (0x3 << 6)
+#define RT3261_MIC2_OVTH_SFT 6
+#define RT3261_MIC2_OVTH_600UA (0x0 << 6)
+#define RT3261_MIC2_OVTH_1500UA (0x1 << 6)
+#define RT3261_MIC2_OVTH_2000UA (0x2 << 6)
+#define RT3261_PWR_MB_MASK (0x1 << 5)
+#define RT3261_PWR_MB_SFT 5
+#define RT3261_PWR_MB_PD (0x0 << 5)
+#define RT3261_PWR_MB_PU (0x1 << 5)
+#define RT3261_PWR_CLK25M_MASK (0x1 << 4)
+#define RT3261_PWR_CLK25M_SFT 4
+#define RT3261_PWR_CLK25M_PD (0x0 << 4)
+#define RT3261_PWR_CLK25M_PU (0x1 << 4)
+
+/* EQ Control 1 (0xb0) */
+#define RT3261_EQ_SRC_MASK (0x1 << 15)
+#define RT3261_EQ_SRC_SFT 15
+#define RT3261_EQ_SRC_DAC (0x0 << 15)
+#define RT3261_EQ_SRC_ADC (0x1 << 15)
+#define RT3261_EQ_UPD (0x1 << 14)
+#define RT3261_EQ_UPD_BIT 14
+#define RT3261_EQ_CD_MASK (0x1 << 13)
+#define RT3261_EQ_CD_SFT 13
+#define RT3261_EQ_CD_DIS (0x0 << 13)
+#define RT3261_EQ_CD_EN (0x1 << 13)
+#define RT3261_EQ_DITH_MASK (0x3 << 8)
+#define RT3261_EQ_DITH_SFT 8
+#define RT3261_EQ_DITH_NOR (0x0 << 8)
+#define RT3261_EQ_DITH_LSB (0x1 << 8)
+#define RT3261_EQ_DITH_LSB_1 (0x2 << 8)
+#define RT3261_EQ_DITH_LSB_2 (0x3 << 8)
+
+/* EQ Control 2 (0xb1) */
+#define RT3261_EQ_HPF1_M_MASK (0x1 << 8)
+#define RT3261_EQ_HPF1_M_SFT 8
+#define RT3261_EQ_HPF1_M_HI (0x0 << 8)
+#define RT3261_EQ_HPF1_M_1ST (0x1 << 8)
+#define RT3261_EQ_LPF1_M_MASK (0x1 << 7)
+#define RT3261_EQ_LPF1_M_SFT 7
+#define RT3261_EQ_LPF1_M_LO (0x0 << 7)
+#define RT3261_EQ_LPF1_M_1ST (0x1 << 7)
+#define RT3261_EQ_HPF2_MASK (0x1 << 6)
+#define RT3261_EQ_HPF2_SFT 6
+#define RT3261_EQ_HPF2_DIS (0x0 << 6)
+#define RT3261_EQ_HPF2_EN (0x1 << 6)
+#define RT3261_EQ_HPF1_MASK (0x1 << 5)
+#define RT3261_EQ_HPF1_SFT 5
+#define RT3261_EQ_HPF1_DIS (0x0 << 5)
+#define RT3261_EQ_HPF1_EN (0x1 << 5)
+#define RT3261_EQ_BPF4_MASK (0x1 << 4)
+#define RT3261_EQ_BPF4_SFT 4
+#define RT3261_EQ_BPF4_DIS (0x0 << 4)
+#define RT3261_EQ_BPF4_EN (0x1 << 4)
+#define RT3261_EQ_BPF3_MASK (0x1 << 3)
+#define RT3261_EQ_BPF3_SFT 3
+#define RT3261_EQ_BPF3_DIS (0x0 << 3)
+#define RT3261_EQ_BPF3_EN (0x1 << 3)
+#define RT3261_EQ_BPF2_MASK (0x1 << 2)
+#define RT3261_EQ_BPF2_SFT 2
+#define RT3261_EQ_BPF2_DIS (0x0 << 2)
+#define RT3261_EQ_BPF2_EN (0x1 << 2)
+#define RT3261_EQ_BPF1_MASK (0x1 << 1)
+#define RT3261_EQ_BPF1_SFT 1
+#define RT3261_EQ_BPF1_DIS (0x0 << 1)
+#define RT3261_EQ_BPF1_EN (0x1 << 1)
+#define RT3261_EQ_LPF_MASK (0x1)
+#define RT3261_EQ_LPF_SFT 0
+#define RT3261_EQ_LPF_DIS (0x0)
+#define RT3261_EQ_LPF_EN (0x1)
+#define RT3261_EQ_CTRL_MASK (0x7f)
+
+/* Memory Test (0xb2) */
+#define RT3261_MT_MASK (0x1 << 15)
+#define RT3261_MT_SFT 15
+#define RT3261_MT_DIS (0x0 << 15)
+#define RT3261_MT_EN (0x1 << 15)
+
+/* DRC/AGC Control 1 (0xb4) */
+#define RT3261_DRC_AGC_P_MASK (0x1 << 15)
+#define RT3261_DRC_AGC_P_SFT 15
+#define RT3261_DRC_AGC_P_DAC (0x0 << 15)
+#define RT3261_DRC_AGC_P_ADC (0x1 << 15)
+#define RT3261_DRC_AGC_MASK (0x1 << 14)
+#define RT3261_DRC_AGC_SFT 14
+#define RT3261_DRC_AGC_DIS (0x0 << 14)
+#define RT3261_DRC_AGC_EN (0x1 << 14)
+#define RT3261_DRC_AGC_UPD (0x1 << 13)
+#define RT3261_DRC_AGC_UPD_BIT 13
+#define RT3261_DRC_AGC_AR_MASK (0x1f << 8)
+#define RT3261_DRC_AGC_AR_SFT 8
+#define RT3261_DRC_AGC_R_MASK (0x7 << 5)
+#define RT3261_DRC_AGC_R_SFT 5
+#define RT3261_DRC_AGC_R_48K (0x1 << 5)
+#define RT3261_DRC_AGC_R_96K (0x2 << 5)
+#define RT3261_DRC_AGC_R_192K (0x3 << 5)
+#define RT3261_DRC_AGC_R_441K (0x5 << 5)
+#define RT3261_DRC_AGC_R_882K (0x6 << 5)
+#define RT3261_DRC_AGC_R_1764K (0x7 << 5)
+#define RT3261_DRC_AGC_RC_MASK (0x1f)
+#define RT3261_DRC_AGC_RC_SFT 0
+
+/* DRC/AGC Control 2 (0xb5) */
+#define RT3261_DRC_AGC_POB_MASK (0x3f << 8)
+#define RT3261_DRC_AGC_POB_SFT 8
+#define RT3261_DRC_AGC_CP_MASK (0x1 << 7)
+#define RT3261_DRC_AGC_CP_SFT 7
+#define RT3261_DRC_AGC_CP_DIS (0x0 << 7)
+#define RT3261_DRC_AGC_CP_EN (0x1 << 7)
+#define RT3261_DRC_AGC_CPR_MASK (0x3 << 5)
+#define RT3261_DRC_AGC_CPR_SFT 5
+#define RT3261_DRC_AGC_CPR_1_1 (0x0 << 5)
+#define RT3261_DRC_AGC_CPR_1_2 (0x1 << 5)
+#define RT3261_DRC_AGC_CPR_1_3 (0x2 << 5)
+#define RT3261_DRC_AGC_CPR_1_4 (0x3 << 5)
+#define RT3261_DRC_AGC_PRB_MASK (0x1f)
+#define RT3261_DRC_AGC_PRB_SFT 0
+
+/* DRC/AGC Control 3 (0xb6) */
+#define RT3261_DRC_AGC_NGB_MASK (0xf << 12)
+#define RT3261_DRC_AGC_NGB_SFT 12
+#define RT3261_DRC_AGC_TAR_MASK (0x1f << 7)
+#define RT3261_DRC_AGC_TAR_SFT 7
+#define RT3261_DRC_AGC_NG_MASK (0x1 << 6)
+#define RT3261_DRC_AGC_NG_SFT 6
+#define RT3261_DRC_AGC_NG_DIS (0x0 << 6)
+#define RT3261_DRC_AGC_NG_EN (0x1 << 6)
+#define RT3261_DRC_AGC_NGH_MASK (0x1 << 5)
+#define RT3261_DRC_AGC_NGH_SFT 5
+#define RT3261_DRC_AGC_NGH_DIS (0x0 << 5)
+#define RT3261_DRC_AGC_NGH_EN (0x1 << 5)
+#define RT3261_DRC_AGC_NGT_MASK (0x1f)
+#define RT3261_DRC_AGC_NGT_SFT 0
+
+/* ANC Control 1 (0xb8) */
+#define RT3261_ANC_M_MASK (0x1 << 15)
+#define RT3261_ANC_M_SFT 15
+#define RT3261_ANC_M_NOR (0x0 << 15)
+#define RT3261_ANC_M_REV (0x1 << 15)
+#define RT3261_ANC_MASK (0x1 << 14)
+#define RT3261_ANC_SFT 14
+#define RT3261_ANC_DIS (0x0 << 14)
+#define RT3261_ANC_EN (0x1 << 14)
+#define RT3261_ANC_MD_MASK (0x3 << 12)
+#define RT3261_ANC_MD_SFT 12
+#define RT3261_ANC_MD_DIS (0x0 << 12)
+#define RT3261_ANC_MD_67MS (0x1 << 12)
+#define RT3261_ANC_MD_267MS (0x2 << 12)
+#define RT3261_ANC_MD_1067MS (0x3 << 12)
+#define RT3261_ANC_SN_MASK (0x1 << 11)
+#define RT3261_ANC_SN_SFT 11
+#define RT3261_ANC_SN_DIS (0x0 << 11)
+#define RT3261_ANC_SN_EN (0x1 << 11)
+#define RT3261_ANC_CLK_MASK (0x1 << 10)
+#define RT3261_ANC_CLK_SFT 10
+#define RT3261_ANC_CLK_ANC (0x0 << 10)
+#define RT3261_ANC_CLK_REG (0x1 << 10)
+#define RT3261_ANC_ZCD_MASK (0x3 << 8)
+#define RT3261_ANC_ZCD_SFT 8
+#define RT3261_ANC_ZCD_DIS (0x0 << 8)
+#define RT3261_ANC_ZCD_T1 (0x1 << 8)
+#define RT3261_ANC_ZCD_T2 (0x2 << 8)
+#define RT3261_ANC_ZCD_WT (0x3 << 8)
+#define RT3261_ANC_CS_MASK (0x1 << 7)
+#define RT3261_ANC_CS_SFT 7
+#define RT3261_ANC_CS_DIS (0x0 << 7)
+#define RT3261_ANC_CS_EN (0x1 << 7)
+#define RT3261_ANC_SW_MASK (0x1 << 6)
+#define RT3261_ANC_SW_SFT 6
+#define RT3261_ANC_SW_NOR (0x0 << 6)
+#define RT3261_ANC_SW_AUTO (0x1 << 6)
+#define RT3261_ANC_CO_L_MASK (0x3f)
+#define RT3261_ANC_CO_L_SFT 0
+
+/* ANC Control 2 (0xb6) */
+#define RT3261_ANC_FG_R_MASK (0xf << 12)
+#define RT3261_ANC_FG_R_SFT 12
+#define RT3261_ANC_FG_L_MASK (0xf << 8)
+#define RT3261_ANC_FG_L_SFT 8
+#define RT3261_ANC_CG_R_MASK (0xf << 4)
+#define RT3261_ANC_CG_R_SFT 4
+#define RT3261_ANC_CG_L_MASK (0xf)
+#define RT3261_ANC_CG_L_SFT 0
+
+/* ANC Control 3 (0xb6) */
+#define RT3261_ANC_CD_MASK (0x1 << 6)
+#define RT3261_ANC_CD_SFT 6
+#define RT3261_ANC_CD_BOTH (0x0 << 6)
+#define RT3261_ANC_CD_IND (0x1 << 6)
+#define RT3261_ANC_CO_R_MASK (0x3f)
+#define RT3261_ANC_CO_R_SFT 0
+
+/* Jack Detect Control (0xbb) */
+#define RT3261_JD_MASK (0x7 << 13)
+#define RT3261_JD_SFT 13
+#define RT3261_JD_DIS (0x0 << 13)
+#define RT3261_JD_GPIO1 (0x1 << 13)
+#define RT3261_JD_JD1_IN4P (0x2 << 13)
+#define RT3261_JD_JD2_IN4N (0x3 << 13)
+#define RT3261_JD_GPIO2 (0x4 << 13)
+#define RT3261_JD_GPIO3 (0x5 << 13)
+#define RT3261_JD_GPIO4 (0x6 << 13)
+#define RT3261_JD_HP_MASK (0x1 << 11)
+#define RT3261_JD_HP_SFT 11
+#define RT3261_JD_HP_DIS (0x0 << 11)
+#define RT3261_JD_HP_EN (0x1 << 11)
+#define RT3261_JD_HP_TRG_MASK (0x1 << 10)
+#define RT3261_JD_HP_TRG_SFT 10
+#define RT3261_JD_HP_TRG_LO (0x0 << 10)
+#define RT3261_JD_HP_TRG_HI (0x1 << 10)
+#define RT3261_JD_SPL_MASK (0x1 << 9)
+#define RT3261_JD_SPL_SFT 9
+#define RT3261_JD_SPL_DIS (0x0 << 9)
+#define RT3261_JD_SPL_EN (0x1 << 9)
+#define RT3261_JD_SPL_TRG_MASK (0x1 << 8)
+#define RT3261_JD_SPL_TRG_SFT 8
+#define RT3261_JD_SPL_TRG_LO (0x0 << 8)
+#define RT3261_JD_SPL_TRG_HI (0x1 << 8)
+#define RT3261_JD_SPR_MASK (0x1 << 7)
+#define RT3261_JD_SPR_SFT 7
+#define RT3261_JD_SPR_DIS (0x0 << 7)
+#define RT3261_JD_SPR_EN (0x1 << 7)
+#define RT3261_JD_SPR_TRG_MASK (0x1 << 6)
+#define RT3261_JD_SPR_TRG_SFT 6
+#define RT3261_JD_SPR_TRG_LO (0x0 << 6)
+#define RT3261_JD_SPR_TRG_HI (0x1 << 6)
+#define RT3261_JD_MO_MASK (0x1 << 5)
+#define RT3261_JD_MO_SFT 5
+#define RT3261_JD_MO_DIS (0x0 << 5)
+#define RT3261_JD_MO_EN (0x1 << 5)
+#define RT3261_JD_MO_TRG_MASK (0x1 << 4)
+#define RT3261_JD_MO_TRG_SFT 4
+#define RT3261_JD_MO_TRG_LO (0x0 << 4)
+#define RT3261_JD_MO_TRG_HI (0x1 << 4)
+#define RT3261_JD_LO_MASK (0x1 << 3)
+#define RT3261_JD_LO_SFT 3
+#define RT3261_JD_LO_DIS (0x0 << 3)
+#define RT3261_JD_LO_EN (0x1 << 3)
+#define RT3261_JD_LO_TRG_MASK (0x1 << 2)
+#define RT3261_JD_LO_TRG_SFT 2
+#define RT3261_JD_LO_TRG_LO (0x0 << 2)
+#define RT3261_JD_LO_TRG_HI (0x1 << 2)
+#define RT3261_JD1_IN4P_MASK (0x1 << 1)
+#define RT3261_JD1_IN4P_SFT 1
+#define RT3261_JD1_IN4P_DIS (0x0 << 1)
+#define RT3261_JD1_IN4P_EN (0x1 << 1)
+#define RT3261_JD2_IN4N_MASK (0x1)
+#define RT3261_JD2_IN4N_SFT 0
+#define RT3261_JD2_IN4N_DIS (0x0)
+#define RT3261_JD2_IN4N_EN (0x1)
+
+/* Jack detect for ANC (0xbc) */
+#define RT3261_ANC_DET_MASK (0x3 << 4)
+#define RT3261_ANC_DET_SFT 4
+#define RT3261_ANC_DET_DIS (0x0 << 4)
+#define RT3261_ANC_DET_MB1 (0x1 << 4)
+#define RT3261_ANC_DET_MB2 (0x2 << 4)
+#define RT3261_ANC_DET_JD (0x3 << 4)
+#define RT3261_AD_TRG_MASK (0x1 << 3)
+#define RT3261_AD_TRG_SFT 3
+#define RT3261_AD_TRG_LO (0x0 << 3)
+#define RT3261_AD_TRG_HI (0x1 << 3)
+#define RT3261_ANCM_DET_MASK (0x3 << 4)
+#define RT3261_ANCM_DET_SFT 4
+#define RT3261_ANCM_DET_DIS (0x0 << 4)
+#define RT3261_ANCM_DET_MB1 (0x1 << 4)
+#define RT3261_ANCM_DET_MB2 (0x2 << 4)
+#define RT3261_ANCM_DET_JD (0x3 << 4)
+#define RT3261_AMD_TRG_MASK (0x1 << 3)
+#define RT3261_AMD_TRG_SFT 3
+#define RT3261_AMD_TRG_LO (0x0 << 3)
+#define RT3261_AMD_TRG_HI (0x1 << 3)
+
+/* IRQ Control 1 (0xbd) */
+#define RT3261_IRQ_JD_MASK (0x1 << 15)
+#define RT3261_IRQ_JD_SFT 15
+#define RT3261_IRQ_JD_BP (0x0 << 15)
+#define RT3261_IRQ_JD_NOR (0x1 << 15)
+#define RT3261_IRQ_OT_MASK (0x1 << 14)
+#define RT3261_IRQ_OT_SFT 14
+#define RT3261_IRQ_OT_BP (0x0 << 14)
+#define RT3261_IRQ_OT_NOR (0x1 << 14)
+#define RT3261_JD_STKY_MASK (0x1 << 13)
+#define RT3261_JD_STKY_SFT 13
+#define RT3261_JD_STKY_DIS (0x0 << 13)
+#define RT3261_JD_STKY_EN (0x1 << 13)
+#define RT3261_OT_STKY_MASK (0x1 << 12)
+#define RT3261_OT_STKY_SFT 12
+#define RT3261_OT_STKY_DIS (0x0 << 12)
+#define RT3261_OT_STKY_EN (0x1 << 12)
+#define RT3261_JD_P_MASK (0x1 << 11)
+#define RT3261_JD_P_SFT 11
+#define RT3261_JD_P_NOR (0x0 << 11)
+#define RT3261_JD_P_INV (0x1 << 11)
+#define RT3261_OT_P_MASK (0x1 << 10)
+#define RT3261_OT_P_SFT 10
+#define RT3261_OT_P_NOR (0x0 << 10)
+#define RT3261_OT_P_INV (0x1 << 10)
+
+/* IRQ Control 2 (0xbe) */
+#define RT3261_IRQ_MB1_OC_MASK (0x1 << 15)
+#define RT3261_IRQ_MB1_OC_SFT 15
+#define RT3261_IRQ_MB1_OC_BP (0x0 << 15)
+#define RT3261_IRQ_MB1_OC_NOR (0x1 << 15)
+#define RT3261_IRQ_MB2_OC_MASK (0x1 << 14)
+#define RT3261_IRQ_MB2_OC_SFT 14
+#define RT3261_IRQ_MB2_OC_BP (0x0 << 14)
+#define RT3261_IRQ_MB2_OC_NOR (0x1 << 14)
+#define RT3261_MB1_OC_STKY_MASK (0x1 << 11)
+#define RT3261_MB1_OC_STKY_SFT 11
+#define RT3261_MB1_OC_STKY_DIS (0x0 << 11)
+#define RT3261_MB1_OC_STKY_EN (0x1 << 11)
+#define RT3261_MB2_OC_STKY_MASK (0x1 << 10)
+#define RT3261_MB2_OC_STKY_SFT 10
+#define RT3261_MB2_OC_STKY_DIS (0x0 << 10)
+#define RT3261_MB2_OC_STKY_EN (0x1 << 10)
+#define RT3261_MB1_OC_P_MASK (0x1 << 7)
+#define RT3261_MB1_OC_P_SFT 7
+#define RT3261_MB1_OC_P_NOR (0x0 << 7)
+#define RT3261_MB1_OC_P_INV (0x1 << 7)
+#define RT3261_MB2_OC_P_MASK (0x1 << 6)
+#define RT3261_MB2_OC_P_SFT 6
+#define RT3261_MB2_OC_P_NOR (0x0 << 6)
+#define RT3261_MB2_OC_P_INV (0x1 << 6)
+#define RT3261_MB1_OC_CLR (0x1 << 3)
+#define RT3261_MB1_OC_CLR_SFT 3
+#define RT3261_MB2_OC_CLR (0x1 << 2)
+#define RT3261_MB2_OC_CLR_SFT 2
+
+/* GPIO Control 1 (0xc0) */
+#define RT3261_GP1_PIN_MASK (0x1 << 15)
+#define RT3261_GP1_PIN_SFT 15
+#define RT3261_GP1_PIN_GPIO1 (0x0 << 15)
+#define RT3261_GP1_PIN_IRQ (0x1 << 15)
+#define RT3261_GP2_PIN_MASK (0x1 << 14)
+#define RT3261_GP2_PIN_SFT 14
+#define RT3261_GP2_PIN_GPIO2 (0x0 << 14)
+#define RT3261_GP2_PIN_DMIC1_SCL (0x1 << 14)
+#define RT3261_GP3_PIN_MASK (0x3 << 12)
+#define RT3261_GP3_PIN_SFT 12
+#define RT3261_GP3_PIN_GPIO3 (0x0 << 12)
+#define RT3261_GP3_PIN_DMIC1_SDA (0x1 << 12)
+#define RT3261_GP3_PIN_IRQ (0x2 << 12)
+#define RT3261_GP4_PIN_MASK (0x1 << 11)
+#define RT3261_GP4_PIN_SFT 11
+#define RT3261_GP4_PIN_GPIO4 (0x0 << 11)
+#define RT3261_GP4_PIN_DMIC2_SDA (0x1 << 11)
+#define RT3261_DP_SIG_MASK (0x1 << 10)
+#define RT3261_DP_SIG_SFT 10
+#define RT3261_DP_SIG_TEST (0x0 << 10)
+#define RT3261_DP_SIG_AP (0x1 << 10)
+#define RT3261_GPIO_M_MASK (0x1 << 9)
+#define RT3261_GPIO_M_SFT 9
+#define RT3261_GPIO_M_FLT (0x0 << 9)
+#define RT3261_GPIO_M_PH (0x1 << 9)
+
+/* GPIO Control 3 (0xc2) */
+#define RT3261_GP4_PF_MASK (0x1 << 11)
+#define RT3261_GP4_PF_SFT 11
+#define RT3261_GP4_PF_IN (0x0 << 11)
+#define RT3261_GP4_PF_OUT (0x1 << 11)
+#define RT3261_GP4_OUT_MASK (0x1 << 10)
+#define RT3261_GP4_OUT_SFT 10
+#define RT3261_GP4_OUT_LO (0x0 << 10)
+#define RT3261_GP4_OUT_HI (0x1 << 10)
+#define RT3261_GP4_P_MASK (0x1 << 9)
+#define RT3261_GP4_P_SFT 9
+#define RT3261_GP4_P_NOR (0x0 << 9)
+#define RT3261_GP4_P_INV (0x1 << 9)
+#define RT3261_GP3_PF_MASK (0x1 << 8)
+#define RT3261_GP3_PF_SFT 8
+#define RT3261_GP3_PF_IN (0x0 << 8)
+#define RT3261_GP3_PF_OUT (0x1 << 8)
+#define RT3261_GP3_OUT_MASK (0x1 << 7)
+#define RT3261_GP3_OUT_SFT 7
+#define RT3261_GP3_OUT_LO (0x0 << 7)
+#define RT3261_GP3_OUT_HI (0x1 << 7)
+#define RT3261_GP3_P_MASK (0x1 << 6)
+#define RT3261_GP3_P_SFT 6
+#define RT3261_GP3_P_NOR (0x0 << 6)
+#define RT3261_GP3_P_INV (0x1 << 6)
+#define RT3261_GP2_PF_MASK (0x1 << 5)
+#define RT3261_GP2_PF_SFT 5
+#define RT3261_GP2_PF_IN (0x0 << 5)
+#define RT3261_GP2_PF_OUT (0x1 << 5)
+#define RT3261_GP2_OUT_MASK (0x1 << 4)
+#define RT3261_GP2_OUT_SFT 4
+#define RT3261_GP2_OUT_LO (0x0 << 4)
+#define RT3261_GP2_OUT_HI (0x1 << 4)
+#define RT3261_GP2_P_MASK (0x1 << 3)
+#define RT3261_GP2_P_SFT 3
+#define RT3261_GP2_P_NOR (0x0 << 3)
+#define RT3261_GP2_P_INV (0x1 << 3)
+#define RT3261_GP1_PF_MASK (0x1 << 2)
+#define RT3261_GP1_PF_SFT 2
+#define RT3261_GP1_PF_IN (0x0 << 2)
+#define RT3261_GP1_PF_OUT (0x1 << 2)
+#define RT3261_GP1_OUT_MASK (0x1 << 1)
+#define RT3261_GP1_OUT_SFT 1
+#define RT3261_GP1_OUT_LO (0x0 << 1)
+#define RT3261_GP1_OUT_HI (0x1 << 1)
+#define RT3261_GP1_P_MASK (0x1)
+#define RT3261_GP1_P_SFT 0
+#define RT3261_GP1_P_NOR (0x0)
+#define RT3261_GP1_P_INV (0x1)
+
+/* FM34-500 Register Control 1 (0xc4) */
+#define RT3261_DSP_ADD_SFT 0
+
+/* FM34-500 Register Control 2 (0xc5) */
+#define RT3261_DSP_DAT_SFT 0
+
+/* FM34-500 Register Control 3 (0xc6) */
+#define RT3261_DSP_BUSY_MASK (0x1 << 15)
+#define RT3261_DSP_BUSY_BIT 15
+#define RT3261_DSP_DS_MASK (0x1 << 14)
+#define RT3261_DSP_DS_SFT 14
+#define RT3261_DSP_DS_FM3010 (0x1 << 14)
+#define RT3261_DSP_DS_TEMP (0x1 << 14)
+#define RT3261_DSP_CLK_MASK (0x3 << 12)
+#define RT3261_DSP_CLK_SFT 12
+#define RT3261_DSP_CLK_384K (0x0 << 12)
+#define RT3261_DSP_CLK_192K (0x1 << 12)
+#define RT3261_DSP_CLK_96K (0x2 << 12)
+#define RT3261_DSP_CLK_64K (0x3 << 12)
+#define RT3261_DSP_PD_PIN_MASK (0x1 << 11)
+#define RT3261_DSP_PD_PIN_SFT 11
+#define RT3261_DSP_PD_PIN_LO (0x0 << 11)
+#define RT3261_DSP_PD_PIN_HI (0x1 << 11)
+#define RT3261_DSP_RST_PIN_MASK (0x1 << 10)
+#define RT3261_DSP_RST_PIN_SFT 10
+#define RT3261_DSP_RST_PIN_LO (0x0 << 10)
+#define RT3261_DSP_RST_PIN_HI (0x1 << 10)
+#define RT3261_DSP_R_EN (0x1 << 9)
+#define RT3261_DSP_W_EN (0x1 << 8)
+#define RT3261_DSP_CMD_MASK (0xff)
+#define RT3261_DSP_CMD_PE (0x0d) /* Patch Entry */
+#define RT3261_DSP_CMD_MW (0x3b) /* Memory Write */
+#define RT3261_DSP_CMD_MR (0x37) /* Memory Read */
+#define RT3261_DSP_CMD_RR (0x60) /* Register Read */
+#define RT3261_DSP_CMD_RW (0x68) /* Register Write */
+#define RT3261_DSP_REG_DATHI (0x26) /* High Data Addr */
+#define RT3261_DSP_REG_DATLO (0x25) /* Low Data Addr */
+
+/* Programmable Register Array Control 1 (0xc8) */
+#define RT3261_REG_SEQ_MASK (0xf << 12)
+#define RT3261_REG_SEQ_SFT 12
+#define RT3261_SEQ1_ST_MASK (0x1 << 11) /*RO*/
+#define RT3261_SEQ1_ST_SFT 11
+#define RT3261_SEQ1_ST_RUN (0x0 << 11)
+#define RT3261_SEQ1_ST_FIN (0x1 << 11)
+#define RT3261_SEQ2_ST_MASK (0x1 << 10) /*RO*/
+#define RT3261_SEQ2_ST_SFT 10
+#define RT3261_SEQ2_ST_RUN (0x0 << 10)
+#define RT3261_SEQ2_ST_FIN (0x1 << 10)
+#define RT3261_REG_LV_MASK (0x1 << 9)
+#define RT3261_REG_LV_SFT 9
+#define RT3261_REG_LV_MX (0x0 << 9)
+#define RT3261_REG_LV_PR (0x1 << 9)
+#define RT3261_SEQ_2_PT_MASK (0x1 << 8)
+#define RT3261_SEQ_2_PT_BIT 8
+#define RT3261_REG_IDX_MASK (0xff)
+#define RT3261_REG_IDX_SFT 0
+
+/* Programmable Register Array Control 2 (0xc9) */
+#define RT3261_REG_DAT_MASK (0xffff)
+#define RT3261_REG_DAT_SFT 0
+
+/* Programmable Register Array Control 3 (0xca) */
+#define RT3261_SEQ_DLY_MASK (0xff << 8)
+#define RT3261_SEQ_DLY_SFT 8
+#define RT3261_PROG_MASK (0x1 << 7)
+#define RT3261_PROG_SFT 7
+#define RT3261_PROG_DIS (0x0 << 7)
+#define RT3261_PROG_EN (0x1 << 7)
+#define RT3261_SEQ1_PT_RUN (0x1 << 6)
+#define RT3261_SEQ1_PT_RUN_BIT 6
+#define RT3261_SEQ2_PT_RUN (0x1 << 5)
+#define RT3261_SEQ2_PT_RUN_BIT 5
+
+/* Programmable Register Array Control 4 (0xcb) */
+#define RT3261_SEQ1_START_MASK (0xf << 8)
+#define RT3261_SEQ1_START_SFT 8
+#define RT3261_SEQ1_END_MASK (0xf)
+#define RT3261_SEQ1_END_SFT 0
+
+/* Programmable Register Array Control 5 (0xcc) */
+#define RT3261_SEQ2_START_MASK (0xf << 8)
+#define RT3261_SEQ2_START_SFT 8
+#define RT3261_SEQ2_END_MASK (0xf)
+#define RT3261_SEQ2_END_SFT 0
+
+/* Scramble Function (0xcd) */
+#define RT3261_SCB_KEY_MASK (0xff)
+#define RT3261_SCB_KEY_SFT 0
+
+/* Scramble Control (0xce) */
+#define RT3261_SCB_SWAP_MASK (0x1 << 15)
+#define RT3261_SCB_SWAP_SFT 15
+#define RT3261_SCB_SWAP_DIS (0x0 << 15)
+#define RT3261_SCB_SWAP_EN (0x1 << 15)
+#define RT3261_SCB_MASK (0x1 << 14)
+#define RT3261_SCB_SFT 14
+#define RT3261_SCB_DIS (0x0 << 14)
+#define RT3261_SCB_EN (0x1 << 14)
+
+/* Baseback Control (0xcf) */
+#define RT3261_BB_MASK (0x1 << 15)
+#define RT3261_BB_SFT 15
+#define RT3261_BB_DIS (0x0 << 15)
+#define RT3261_BB_EN (0x1 << 15)
+#define RT3261_BB_CT_MASK (0x7 << 12)
+#define RT3261_BB_CT_SFT 12
+#define RT3261_BB_CT_A (0x0 << 12)
+#define RT3261_BB_CT_B (0x1 << 12)
+#define RT3261_BB_CT_C (0x2 << 12)
+#define RT3261_BB_CT_D (0x3 << 12)
+#define RT3261_M_BB_L_MASK (0x1 << 9)
+#define RT3261_M_BB_L_SFT 9
+#define RT3261_M_BB_R_MASK (0x1 << 8)
+#define RT3261_M_BB_R_SFT 8
+#define RT3261_M_BB_HPF_L_MASK (0x1 << 7)
+#define RT3261_M_BB_HPF_L_SFT 7
+#define RT3261_M_BB_HPF_R_MASK (0x1 << 6)
+#define RT3261_M_BB_HPF_R_SFT 6
+#define RT3261_G_BB_BST_MASK (0x3f)
+#define RT3261_G_BB_BST_SFT 0
+
+/* MP3 Plus Control 1 (0xd0) */
+#define RT3261_M_MP3_L_MASK (0x1 << 15)
+#define RT3261_M_MP3_L_SFT 15
+#define RT3261_M_MP3_R_MASK (0x1 << 14)
+#define RT3261_M_MP3_R_SFT 14
+#define RT3261_M_MP3_MASK (0x1 << 13)
+#define RT3261_M_MP3_SFT 13
+#define RT3261_M_MP3_DIS (0x0 << 13)
+#define RT3261_M_MP3_EN (0x1 << 13)
+#define RT3261_EG_MP3_MASK (0x1f << 8)
+#define RT3261_EG_MP3_SFT 8
+#define RT3261_MP3_HLP_MASK (0x1 << 7)
+#define RT3261_MP3_HLP_SFT 7
+#define RT3261_MP3_HLP_DIS (0x0 << 7)
+#define RT3261_MP3_HLP_EN (0x1 << 7)
+#define RT3261_M_MP3_ORG_L_MASK (0x1 << 6)
+#define RT3261_M_MP3_ORG_L_SFT 6
+#define RT3261_M_MP3_ORG_R_MASK (0x1 << 5)
+#define RT3261_M_MP3_ORG_R_SFT 5
+
+/* MP3 Plus Control 2 (0xd1) */
+#define RT3261_MP3_WT_MASK (0x1 << 13)
+#define RT3261_MP3_WT_SFT 13
+#define RT3261_MP3_WT_1_4 (0x0 << 13)
+#define RT3261_MP3_WT_1_2 (0x1 << 13)
+#define RT3261_OG_MP3_MASK (0x1f << 8)
+#define RT3261_OG_MP3_SFT 8
+#define RT3261_HG_MP3_MASK (0x3f)
+#define RT3261_HG_MP3_SFT 0
+
+/* 3D HP Control 1 (0xd2) */
+#define RT3261_3D_CF_MASK (0x1 << 15)
+#define RT3261_3D_CF_SFT 15
+#define RT3261_3D_CF_DIS (0x0 << 15)
+#define RT3261_3D_CF_EN (0x1 << 15)
+#define RT3261_3D_HP_MASK (0x1 << 14)
+#define RT3261_3D_HP_SFT 14
+#define RT3261_3D_HP_DIS (0x0 << 14)
+#define RT3261_3D_HP_EN (0x1 << 14)
+#define RT3261_3D_BT_MASK (0x1 << 13)
+#define RT3261_3D_BT_SFT 13
+#define RT3261_3D_BT_DIS (0x0 << 13)
+#define RT3261_3D_BT_EN (0x1 << 13)
+#define RT3261_3D_1F_MIX_MASK (0x3 << 11)
+#define RT3261_3D_1F_MIX_SFT 11
+#define RT3261_3D_HP_M_MASK (0x1 << 10)
+#define RT3261_3D_HP_M_SFT 10
+#define RT3261_3D_HP_M_SUR (0x0 << 10)
+#define RT3261_3D_HP_M_FRO (0x1 << 10)
+#define RT3261_M_3D_HRTF_MASK (0x1 << 9)
+#define RT3261_M_3D_HRTF_SFT 9
+#define RT3261_M_3D_D2H_MASK (0x1 << 8)
+#define RT3261_M_3D_D2H_SFT 8
+#define RT3261_M_3D_D2R_MASK (0x1 << 7)
+#define RT3261_M_3D_D2R_SFT 7
+#define RT3261_M_3D_REVB_MASK (0x1 << 6)
+#define RT3261_M_3D_REVB_SFT 6
+
+/* Adjustable high pass filter control 1 (0xd3) */
+#define RT3261_2ND_HPF_MASK (0x1 << 15)
+#define RT3261_2ND_HPF_SFT 15
+#define RT3261_2ND_HPF_DIS (0x0 << 15)
+#define RT3261_2ND_HPF_EN (0x1 << 15)
+#define RT3261_HPF_CF_L_MASK (0x7 << 12)
+#define RT3261_HPF_CF_L_SFT 12
+#define RT3261_1ST_HPF_MASK (0x1 << 11)
+#define RT3261_1ST_HPF_SFT 11
+#define RT3261_1ST_HPF_DIS (0x0 << 11)
+#define RT3261_1ST_HPF_EN (0x1 << 11)
+#define RT3261_HPF_CF_R_MASK (0x7 << 8)
+#define RT3261_HPF_CF_R_SFT 8
+#define RT3261_ZD_T_MASK (0x3 << 6)
+#define RT3261_ZD_T_SFT 6
+#define RT3261_ZD_F_MASK (0x3 << 4)
+#define RT3261_ZD_F_SFT 4
+#define RT3261_ZD_F_IM (0x0 << 4)
+#define RT3261_ZD_F_ZC_IM (0x1 << 4)
+#define RT3261_ZD_F_ZC_IOD (0x2 << 4)
+#define RT3261_ZD_F_UN (0x3 << 4)
+
+/* HP calibration control and Amp detection (0xd6) */
+#define RT3261_SI_DAC_MASK (0x1 << 11)
+#define RT3261_SI_DAC_SFT 11
+#define RT3261_SI_DAC_AUTO (0x0 << 11)
+#define RT3261_SI_DAC_TEST (0x1 << 11)
+#define RT3261_DC_CAL_M_MASK (0x1 << 10)
+#define RT3261_DC_CAL_M_SFT 10
+#define RT3261_DC_CAL_M_CAL (0x0 << 10)
+#define RT3261_DC_CAL_M_NOR (0x1 << 10)
+#define RT3261_DC_CAL_MASK (0x1 << 9)
+#define RT3261_DC_CAL_SFT 9
+#define RT3261_DC_CAL_DIS (0x0 << 9)
+#define RT3261_DC_CAL_EN (0x1 << 9)
+#define RT3261_HPD_RCV_MASK (0x7 << 6)
+#define RT3261_HPD_RCV_SFT 6
+#define RT3261_HPD_PS_MASK (0x1 << 5)
+#define RT3261_HPD_PS_SFT 5
+#define RT3261_HPD_PS_DIS (0x0 << 5)
+#define RT3261_HPD_PS_EN (0x1 << 5)
+#define RT3261_CAL_M_MASK (0x1 << 4)
+#define RT3261_CAL_M_SFT 4
+#define RT3261_CAL_M_DEP (0x0 << 4)
+#define RT3261_CAL_M_CAL (0x1 << 4)
+#define RT3261_CAL_MASK (0x1 << 3)
+#define RT3261_CAL_SFT 3
+#define RT3261_CAL_DIS (0x0 << 3)
+#define RT3261_CAL_EN (0x1 << 3)
+#define RT3261_CAL_TEST_MASK (0x1 << 2)
+#define RT3261_CAL_TEST_SFT 2
+#define RT3261_CAL_TEST_DIS (0x0 << 2)
+#define RT3261_CAL_TEST_EN (0x1 << 2)
+#define RT3261_CAL_P_MASK (0x3)
+#define RT3261_CAL_P_SFT 0
+#define RT3261_CAL_P_NONE (0x0)
+#define RT3261_CAL_P_CAL (0x1)
+#define RT3261_CAL_P_DAC_CAL (0x2)
+
+/* Soft volume and zero cross control 1 (0xd9) */
+#define RT3261_SV_MASK (0x1 << 15)
+#define RT3261_SV_SFT 15
+#define RT3261_SV_DIS (0x0 << 15)
+#define RT3261_SV_EN (0x1 << 15)
+#define RT3261_SPO_SV_MASK (0x1 << 14)
+#define RT3261_SPO_SV_SFT 14
+#define RT3261_SPO_SV_DIS (0x0 << 14)
+#define RT3261_SPO_SV_EN (0x1 << 14)
+#define RT3261_OUT_SV_MASK (0x1 << 13)
+#define RT3261_OUT_SV_SFT 13
+#define RT3261_OUT_SV_DIS (0x0 << 13)
+#define RT3261_OUT_SV_EN (0x1 << 13)
+#define RT3261_HP_SV_MASK (0x1 << 12)
+#define RT3261_HP_SV_SFT 12
+#define RT3261_HP_SV_DIS (0x0 << 12)
+#define RT3261_HP_SV_EN (0x1 << 12)
+#define RT3261_ZCD_DIG_MASK (0x1 << 11)
+#define RT3261_ZCD_DIG_SFT 11
+#define RT3261_ZCD_DIG_DIS (0x0 << 11)
+#define RT3261_ZCD_DIG_EN (0x1 << 11)
+#define RT3261_ZCD_MASK (0x1 << 10)
+#define RT3261_ZCD_SFT 10
+#define RT3261_ZCD_PD (0x0 << 10)
+#define RT3261_ZCD_PU (0x1 << 10)
+#define RT3261_M_ZCD_MASK (0x3f << 4)
+#define RT3261_M_ZCD_SFT 4
+#define RT3261_M_ZCD_RM_L (0x1 << 9)
+#define RT3261_M_ZCD_RM_R (0x1 << 8)
+#define RT3261_M_ZCD_SM_L (0x1 << 7)
+#define RT3261_M_ZCD_SM_R (0x1 << 6)
+#define RT3261_M_ZCD_OM_L (0x1 << 5)
+#define RT3261_M_ZCD_OM_R (0x1 << 4)
+#define RT3261_SV_DLY_MASK (0xf)
+#define RT3261_SV_DLY_SFT 0
+
+/* Soft volume and zero cross control 2 (0xda) */
+#define RT3261_ZCD_HP_MASK (0x1 << 15)
+#define RT3261_ZCD_HP_SFT 15
+#define RT3261_ZCD_HP_DIS (0x0 << 15)
+#define RT3261_ZCD_HP_EN (0x1 << 15)
+
+
+/* Codec Private Register definition */
+/* 3D Speaker Control (0x63) */
+#define RT3261_3D_SPK_MASK (0x1 << 15)
+#define RT3261_3D_SPK_SFT 15
+#define RT3261_3D_SPK_DIS (0x0 << 15)
+#define RT3261_3D_SPK_EN (0x1 << 15)
+#define RT3261_3D_SPK_M_MASK (0x3 << 13)
+#define RT3261_3D_SPK_M_SFT 13
+#define RT3261_3D_SPK_CG_MASK (0x1f << 8)
+#define RT3261_3D_SPK_CG_SFT 8
+#define RT3261_3D_SPK_SG_MASK (0x1f)
+#define RT3261_3D_SPK_SG_SFT 0
+
+/* Wind Noise Detection Control 1 (0x6c) */
+#define RT3261_WND_MASK (0x1 << 15)
+#define RT3261_WND_SFT 15
+#define RT3261_WND_DIS (0x0 << 15)
+#define RT3261_WND_EN (0x1 << 15)
+
+/* Wind Noise Detection Control 2 (0x6d) */
+#define RT3261_WND_FC_NW_MASK (0x3f << 10)
+#define RT3261_WND_FC_NW_SFT 10
+#define RT3261_WND_FC_WK_MASK (0x3f << 4)
+#define RT3261_WND_FC_WK_SFT 4
+
+/* Wind Noise Detection Control 3 (0x6e) */
+#define RT3261_HPF_FC_MASK (0x3f << 6)
+#define RT3261_HPF_FC_SFT 6
+#define RT3261_WND_FC_ST_MASK (0x3f)
+#define RT3261_WND_FC_ST_SFT 0
+
+/* Wind Noise Detection Control 4 (0x6f) */
+#define RT3261_WND_TH_LO_MASK (0x3ff)
+#define RT3261_WND_TH_LO_SFT 0
+
+/* Wind Noise Detection Control 5 (0x70) */
+#define RT3261_WND_TH_HI_MASK (0x3ff)
+#define RT3261_WND_TH_HI_SFT 0
+
+/* Wind Noise Detection Control 8 (0x73) */
+#define RT3261_WND_WIND_MASK (0x1 << 13) /* Read-Only */
+#define RT3261_WND_WIND_SFT 13
+#define RT3261_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
+#define RT3261_WND_STRONG_SFT 12
+enum {
+ RT3261_NO_WIND,
+ RT3261_BREEZE,
+ RT3261_STORM,
+};
+
+/* Dipole Speaker Interface (0x75) */
+#define RT3261_DP_ATT_MASK (0x3 << 14)
+#define RT3261_DP_ATT_SFT 14
+#define RT3261_DP_SPK_MASK (0x1 << 10)
+#define RT3261_DP_SPK_SFT 10
+#define RT3261_DP_SPK_DIS (0x0 << 10)
+#define RT3261_DP_SPK_EN (0x1 << 10)
+
+/* EQ Pre Volume Control (0xb3) */
+#define RT3261_EQ_PRE_VOL_MASK (0xffff)
+#define RT3261_EQ_PRE_VOL_SFT 0
+
+/* EQ Post Volume Control (0xb4) */
+#define RT3261_EQ_PST_VOL_MASK (0xffff)
+#define RT3261_EQ_PST_VOL_SFT 0
+
+/* General Control1 (0xfa) */
+#define RT3261_M_MAMIX_L (0x1 << 13)
+#define RT3261_M_MAMIX_R (0x1 << 12)
+
+/* General Control2 (0xfb) */
+#define RT3261_RXDC_SRC_MASK (0x1 << 7)
+#define RT3261_RXDC_SRC_STO (0x0 << 7)
+#define RT3261_RXDC_SRC_MONO (0x1 << 7)
+#define RT3261_RXDC_SRC_SFT (7)
+#define RT3261_RXDP2_SEL_MASK (0x1 << 3)
+#define RT3261_RXDP2_SEL_IF2 (0x0 << 3)
+#define RT3261_RXDP2_SEL_ADC (0x1 << 3)
+#define RT3261_RXDP2_SEL_SFT (3)
+
+
+/* Vendor ID (0xfd) */
+#define RT3261_VER_C 0x2
+#define RT3261_VER_D 0x3
+
+
+/* Volume Rescale */
+#define RT3261_VOL_RSCL_MAX 0x27
+#define RT3261_VOL_RSCL_RANGE 0x1F
+/* Debug String Length */
+#define RT3261_REG_DISP_LEN 10
+
+#define RT3261_NO_JACK BIT(0)
+#define RT3261_HEADSET_DET BIT(1)
+#define RT3261_HEADPHO_DET BIT(2)
+
+int rt3261_headset_detect(struct snd_soc_codec *codec, int jack_insert);
+
+/* System Clock Source */
+enum {
+ RT3261_SCLK_S_MCLK,
+ RT3261_SCLK_S_PLL1,
+ RT3261_SCLK_S_RCCLK,
+};
+
+/* PLL1 Source */
+enum {
+ RT3261_PLL1_S_MCLK,
+ RT3261_PLL1_S_BCLK1,
+ RT3261_PLL1_S_BCLK2,
+ RT3261_PLL1_S_BCLK3,
+};
+
+enum {
+ RT3261_AIF1,
+ RT3261_AIF2,
+ RT3261_AIF3,
+ RT3261_AIFS,
+};
+
+#define RT3261_U_IF1 (0x1)
+#define RT3261_U_IF2 (0x1 << 1)
+#define RT3261_U_IF3 (0x1 << 2)
+
+enum {
+ RT3261_IF_123,
+ RT3261_IF_132,
+ RT3261_IF_312,
+ RT3261_IF_321,
+ RT3261_IF_231,
+ RT3261_IF_213,
+ RT3261_IF_113,
+ RT3261_IF_223,
+ RT3261_IF_ALL,
+};
+
+enum {
+ RT3261_DMIC_DIS,
+ RT3261_DMIC1,
+ RT3261_DMIC2,
+};
+
+struct rt3261_pll_code {
+ bool m_bp; /* Indicates bypass m code or not. */
+ int m_code;
+ int n_code;
+ int k_code;
+};
+
+struct rt3261_priv {
+ struct snd_soc_codec *codec;
+ struct delayed_work patch_work;
+
+ int aif_pu;
+ int sysclk;
+ int sysclk_src;
+ int lrck[RT3261_AIFS];
+ int bclk[RT3261_AIFS];
+ int master[RT3261_AIFS];
+
+ int pll_src;
+ int pll_in;
+ int pll_out;
+
+ int dmic_en;
+ int dsp_sw; /* expected parameter setting */
+ bool dsp_play_pass;
+ bool dsp_rec_pass;
+};
+
+int rt3261_conn_mux_path(struct snd_soc_codec *codec,
+ char *widget_name, char *path_name);
+
+#endif /* __RT3261_H__ */
--- /dev/null
+/*
+ * rt3261_ioctl.h -- RT3261 ALSA SoC audio driver IO control
+ *
+ * Copyright 2012 Realtek Microelectronics
+ * Author: Bard <bardliao@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/spi/spi.h>
+#include <sound/soc.h>
+#include "rt_codec_ioctl.h"
+#include "rt3261_ioctl.h"
+#include "rt3261.h"
+
+hweq_t hweq_param[] = {
+ {/* NORMAL */
+ {0},
+ {0},
+ 0x0000,
+ },
+ {/* CLUB */
+ {0xa0, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xaf},
+ {0x1c10, 0xc1cc, 0x1e5d, 0x0699, 0xcd48, 0x188d, 0x0699, 0xc3b6, 0x1cd0, 0x0699, 0x0436},
+ 0x000e,
+ },
+ {/* DANCE */
+ {0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xae},
+ {0x1f2c, 0x095b, 0xc071, 0x1f95, 0x0616, 0xc96e, 0x1b11, 0xfc91, 0xdcf2, 0x1194, 0xfaf2, 0x0436},
+ 0x000f,
+ },
+ {/* LIVE */
+ {0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xae},
+ {0x1eb5, 0xfcb6, 0xc24a, 0x1df8, 0x0e7c, 0xc883, 0x1c10, 0x0699, 0xda41, 0x1561, 0xd295, 0x0436},
+ 0x000f,
+ },
+ {/* POP */
+ {0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa9, 0xaa, 0xae},
+ {0x1eb5, 0xfcb6, 0xc1d4, 0x1e5d, 0x0e23, 0xd92e, 0x16e6, 0xfcb6, 0x0969, 0xf988, 0x0436},
+ 0x000f,
+ },
+ {/* ROCK */
+ {0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xae},
+ {0x1eb5, 0xfcb6, 0xc071, 0x1f95, 0x0424, 0xc30a, 0x1d27, 0xf900, 0x0c5d, 0x0fc7, 0x0e23, 0x0436},
+ 0x000f,
+ },
+ {/* OPPO */
+ {0xa2, 0xa3, 0xa4, 0xa5, 0xa6},
+ {0xca4a, 0x17f8, 0x0fec, 0xca4a, 0x17f8},
+ 0x000f,
+ },
+ {/* TREBLE */
+ {0xae, 0xaf},
+ {0x188d, 0x1699},
+ 0x0020,
+ },
+ {/* BASS */
+ {0xa0, 0xa1,},
+ {0x1a43, 0x0c00},
+ 0x0001,
+ },
+};
+#define RT3261_HWEQ_LEN ARRAY_SIZE(hweq_param)
+
+static int rt3261_update_eqmode(
+ struct snd_soc_codec *codec, int mode)
+{
+ struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
+ int i;
+
+ if(codec == NULL || mode >= RT3261_HWEQ_LEN)
+ return -EINVAL;
+
+ dev_dbg(codec->dev, "%s(): mode=%d\n", __func__, mode);
+
+ for(i = 0; i <= EQ_REG_NUM; i++) {
+ if(hweq_param[mode].value[i])
+ ioctl_ops->index_write(codec, hweq_param[mode].reg[i],
+ hweq_param[mode].value[i]);
+ else
+ break;
+ }
+ snd_soc_update_bits(codec, RT3261_EQ_CTRL2, RT3261_EQ_CTRL_MASK,
+ hweq_param[mode].ctrl);
+ snd_soc_update_bits(codec, RT3261_EQ_CTRL1,
+ RT3261_EQ_UPD, RT3261_EQ_UPD);
+ snd_soc_update_bits(codec, RT3261_EQ_CTRL1, RT3261_EQ_UPD, 0);
+
+ return 0;
+}
+
+void set_drc_agc_enable(struct snd_soc_codec *codec, int enable, int path)
+{
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_1, RT3261_DRC_AGC_P_MASK |
+ RT3261_DRC_AGC_MASK | RT3261_DRC_AGC_UPD,
+ enable << RT3261_DRC_AGC_SFT | path << RT3261_DRC_AGC_P_SFT |
+ 1 << RT3261_DRC_AGC_UPD_BIT);
+}
+
+void set_drc_agc_parameters(struct snd_soc_codec *codec, int attack_rate,
+ int sample_rate, int recovery_rate, int limit_level)
+{
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_3, RT3261_DRC_AGC_TAR_MASK,
+ limit_level << RT3261_DRC_AGC_TAR_SFT);
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_1, RT3261_DRC_AGC_AR_MASK |
+ RT3261_DRC_AGC_R_MASK | RT3261_DRC_AGC_UPD |
+ RT3261_DRC_AGC_RC_MASK, attack_rate << RT3261_DRC_AGC_AR_SFT |
+ sample_rate << RT3261_DRC_AGC_R_SFT |
+ recovery_rate << RT3261_DRC_AGC_RC_SFT |
+ 0x1 << RT3261_DRC_AGC_UPD_BIT);
+}
+
+void set_digital_boost_gain(struct snd_soc_codec *codec,
+ int post_gain, int pre_gain)
+{
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_2,
+ RT3261_DRC_AGC_POB_MASK | RT3261_DRC_AGC_PRB_MASK,
+ post_gain << RT3261_DRC_AGC_POB_SFT |
+ pre_gain << RT3261_DRC_AGC_PRB_SFT);
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_1,
+ RT3261_DRC_AGC_UPD, 1 << RT3261_DRC_AGC_UPD_BIT);
+}
+
+void set_noise_gate(struct snd_soc_codec *codec, int noise_gate_en,
+ int noise_gate_hold_en, int compression_gain, int noise_gate_th)
+{
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_3,
+ RT3261_DRC_AGC_NGB_MASK | RT3261_DRC_AGC_NG_MASK |
+ RT3261_DRC_AGC_NGH_MASK | RT3261_DRC_AGC_NGT_MASK,
+ noise_gate_en << RT3261_DRC_AGC_NG_SFT |
+ noise_gate_hold_en << RT3261_DRC_AGC_NGH_SFT |
+ compression_gain << RT3261_DRC_AGC_NGB_SFT |
+ noise_gate_th << RT3261_DRC_AGC_NGT_SFT);
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_1,
+ RT3261_DRC_AGC_UPD, 1 << RT3261_DRC_AGC_UPD_BIT);
+}
+
+void set_drc_agc_compression(struct snd_soc_codec *codec,
+ int compression_en, int compression_ratio)
+{
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_2,
+ RT3261_DRC_AGC_CP_MASK | RT3261_DRC_AGC_CPR_MASK,
+ compression_en << RT3261_DRC_AGC_CP_SFT |
+ compression_ratio << RT3261_DRC_AGC_CPR_SFT);
+ snd_soc_update_bits(codec, RT3261_DRC_AGC_1,
+ RT3261_DRC_AGC_UPD, 1 << RT3261_DRC_AGC_UPD_BIT);
+}
+
+void get_drc_agc_enable(struct snd_soc_codec *codec, int *enable, int *path)
+{
+ unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_1);
+
+ *enable = (reg & RT3261_DRC_AGC_MASK) >> RT3261_DRC_AGC_SFT;
+ *path = (reg & RT3261_DRC_AGC_P_MASK) >> RT3261_DRC_AGC_P_SFT;
+}
+
+void get_drc_agc_parameters(struct snd_soc_codec *codec, int *attack_rate,
+ int *sample_rate, int *recovery_rate, int *limit_level)
+{
+ unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_3);
+
+ *limit_level = (reg & RT3261_DRC_AGC_TAR_MASK) >>
+ RT3261_DRC_AGC_TAR_SFT;
+ reg = snd_soc_read(codec, RT3261_DRC_AGC_1);
+ *attack_rate = (reg & RT3261_DRC_AGC_AR_MASK) >> RT3261_DRC_AGC_AR_SFT;
+ *sample_rate = (reg & RT3261_DRC_AGC_R_MASK) >> RT3261_DRC_AGC_R_SFT;
+ *recovery_rate = (reg & RT3261_DRC_AGC_RC_MASK) >>
+ RT3261_DRC_AGC_RC_SFT;
+}
+
+void get_digital_boost_gain(struct snd_soc_codec *codec,
+ int *post_gain, int *pre_gain)
+{
+ unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_2);
+
+ *post_gain = (reg & RT3261_DRC_AGC_POB_MASK) >> RT3261_DRC_AGC_POB_SFT;
+ *pre_gain = (reg & RT3261_DRC_AGC_PRB_MASK) >> RT3261_DRC_AGC_PRB_SFT;
+}
+
+void get_noise_gate(struct snd_soc_codec *codec, int *noise_gate_en,
+ int *noise_gate_hold_en, int *compression_gain, int *noise_gate_th)
+{
+ unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_3);
+
+ printk("get_noise_gate reg=0x%04x\n",reg);
+ *noise_gate_en = (reg & RT3261_DRC_AGC_NG_MASK) >>
+ RT3261_DRC_AGC_NG_SFT;
+ *noise_gate_hold_en = (reg & RT3261_DRC_AGC_NGH_MASK) >>
+ RT3261_DRC_AGC_NGH_SFT;
+ *compression_gain = (reg & RT3261_DRC_AGC_NGB_MASK) >>
+ RT3261_DRC_AGC_NGB_SFT;
+ *noise_gate_th = (reg & RT3261_DRC_AGC_NGT_MASK) >>
+ RT3261_DRC_AGC_NGT_SFT;
+}
+
+void get_drc_agc_compression(struct snd_soc_codec *codec,
+ int *compression_en, int *compression_ratio)
+{
+ unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_2);
+
+ *compression_en = (reg & RT3261_DRC_AGC_CP_MASK) >>
+ RT3261_DRC_AGC_CP_SFT;
+ *compression_ratio = (reg & RT3261_DRC_AGC_CPR_MASK) >>
+ RT3261_DRC_AGC_CPR_SFT;
+}
+
+int rt3261_ioctl_common(struct snd_hwdep *hw, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ struct snd_soc_codec *codec = hw->private_data;
+ struct rt_codec_cmd __user *_rt_codec = (struct rt_codec_cmd *)arg;
+ struct rt_codec_cmd rt_codec;
+ struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
+ int *buf, mask1 = 0, mask2 = 0;
+ static int eq_mode;
+
+ if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec))) {
+ dev_err(codec->dev,"copy_from_user faild\n");
+ return -EFAULT;
+ }
+ dev_dbg(codec->dev, "%s(): rt_codec.number=%d, cmd=%d\n",
+ __func__, rt_codec.number, cmd);
+ buf = kmalloc(sizeof(*buf) * rt_codec.number, GFP_KERNEL);
+ if (buf == NULL)
+ return -ENOMEM;
+ if (copy_from_user(buf, rt_codec.buf, sizeof(*buf) * rt_codec.number)) {
+ goto err;
+ }
+
+ switch (cmd) {
+ case RT_SET_CODEC_HWEQ_IOCTL:
+ if (eq_mode == *buf)
+ break;
+ eq_mode = *buf;
+ rt3261_update_eqmode(codec, eq_mode);
+ break;
+
+ case RT_GET_CODEC_ID:
+ *buf = snd_soc_read(codec, RT3261_VENDOR_ID2);
+ if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_SET_CODEC_SPK_VOL_IOCTL:
+ if(*(buf) <= 0x27) {
+ snd_soc_update_bits(codec, RT3261_SPK_VOL,
+ RT3261_L_VOL_MASK | RT3261_R_VOL_MASK,
+ *(buf) << RT3261_L_VOL_SFT |
+ *(buf) << RT3261_R_VOL_SFT);
+ }
+ break;
+
+ case RT_SET_CODEC_MIC_GAIN_IOCTL:
+ if(*(buf) <= 0x8) {
+ snd_soc_update_bits(codec, RT3261_IN1_IN2,
+ RT3261_BST_MASK1, *(buf) << RT3261_BST_SFT1);
+ snd_soc_update_bits(codec, RT3261_IN3_IN4,
+ RT3261_BST_MASK2, *(buf) << RT3261_BST_SFT2);
+ }
+ break;
+
+ case RT_SET_CODEC_3D_SPK_IOCTL:
+ if(rt_codec.number < 4)
+ break;
+ if (NULL == ioctl_ops->index_update_bits)
+ break;
+
+ mask1 = 0;
+ if(*buf != -1)
+ mask1 |= RT3261_3D_SPK_MASK;
+ if(*(buf + 1) != -1)
+ mask1 |= RT3261_3D_SPK_M_MASK;
+ if(*(buf + 2) != -1)
+ mask1 |= RT3261_3D_SPK_CG_MASK;
+ if(*(buf + 3) != -1)
+ mask1 |= RT3261_3D_SPK_SG_MASK;
+ ioctl_ops->index_update_bits(codec, RT3261_3D_SPK, mask1,
+ *(buf) << RT3261_3D_SPK_SFT |
+ *(buf + 1) << RT3261_3D_SPK_M_SFT |
+ *(buf + 2) << RT3261_3D_SPK_CG_SFT |
+ *(buf + 3) << RT3261_3D_SPK_SG_SFT);
+ break;
+
+ case RT_SET_CODEC_MP3PLUS_IOCTL:
+ if(rt_codec.number < 5)
+ break;
+ mask1 = mask2 = 0;
+ if(*buf != -1)
+ mask1 |= RT3261_M_MP3_MASK;
+ if(*(buf + 1) != -1)
+ mask1 |= RT3261_EG_MP3_MASK;
+ if(*(buf + 2) != -1)
+ mask2 |= RT3261_OG_MP3_MASK;
+ if(*(buf + 3) != -1)
+ mask2 |= RT3261_HG_MP3_MASK;
+ if(*(buf + 4) != -1)
+ mask2 |= RT3261_MP3_WT_MASK;
+
+ snd_soc_update_bits(codec, RT3261_MP3_PLUS1, mask1,
+ *(buf) << RT3261_M_MP3_SFT |
+ *(buf + 1) << RT3261_EG_MP3_SFT);
+ snd_soc_update_bits(codec, RT3261_MP3_PLUS2, mask2,
+ *(buf + 2) << RT3261_OG_MP3_SFT |
+ *(buf + 3) << RT3261_HG_MP3_SFT |
+ *(buf + 4) << RT3261_MP3_WT_SFT);
+ break;
+ case RT_SET_CODEC_3D_HEADPHONE_IOCTL:
+ if(rt_codec.number < 4)
+ break;
+ if (NULL == ioctl_ops->index_update_bits)
+ break;
+
+ mask1 = 0;
+ if(*buf != -1)
+ mask1 |= RT3261_3D_HP_MASK;
+ if(*(buf + 1) != -1)
+ mask1 |= RT3261_3D_BT_MASK;
+ if(*(buf + 2) != -1)
+ mask1 |= RT3261_3D_1F_MIX_MASK;
+ if(*(buf + 3) != -1)
+ mask1 |= RT3261_3D_HP_M_MASK;
+
+ snd_soc_update_bits(codec, RT3261_3D_HP, mask1,
+ *(buf)<<RT3261_3D_HP_SFT |
+ *(buf + 1) << RT3261_3D_BT_SFT |
+ *(buf + 2) << RT3261_3D_1F_MIX_SFT |
+ *(buf + 3) << RT3261_3D_HP_M_SFT);
+ if(*(buf + 4) != -1)
+ ioctl_ops->index_update_bits(codec,
+ 0x59, 0x1f, *(buf+4));
+ break;
+
+ case RT_SET_CODEC_BASS_BACK_IOCTL:
+ if(rt_codec.number < 3)
+ break;
+ mask1 = 0;
+ if(*buf != -1)
+ mask1 |= RT3261_BB_MASK;
+ if(*(buf + 1) != -1)
+ mask1 |= RT3261_BB_CT_MASK;
+ if(*(buf + 2) != -1)
+ mask1 |= RT3261_G_BB_BST_MASK;
+
+ snd_soc_update_bits(codec, RT3261_BASE_BACK, mask1,
+ *(buf) << RT3261_BB_SFT |
+ *(buf + 1) << RT3261_BB_CT_SFT |
+ *(buf + 2) << RT3261_G_BB_BST_SFT);
+ break;
+
+ case RT_SET_CODEC_DIPOLE_SPK_IOCTL:
+ if(rt_codec.number < 2)
+ break;
+ if (NULL == ioctl_ops->index_update_bits)
+ break;
+
+ mask1 = 0;
+ if(*buf != -1)
+ mask1 |= RT3261_DP_SPK_MASK;
+ if(*(buf + 1) != -1)
+ mask1 |= RT3261_DP_ATT_MASK;
+
+ ioctl_ops->index_update_bits(codec, RT3261_DIP_SPK_INF,
+ mask1, *(buf) << RT3261_DP_SPK_SFT |
+ *(buf + 1) << RT3261_DP_ATT_SFT );
+ break;
+
+ case RT_SET_CODEC_DRC_AGC_ENABLE_IOCTL:
+ if(rt_codec.number < 2)
+ break;
+ set_drc_agc_enable(codec, *(buf), *(buf + 1));
+ break;
+
+ case RT_SET_CODEC_DRC_AGC_PAR_IOCTL:
+ if(rt_codec.number < 4)
+ break;
+ set_drc_agc_parameters(codec, *(buf), *(buf + 1),
+ *(buf + 2), *(buf + 3));
+ break;
+
+ case RT_SET_CODEC_DIGI_BOOST_GAIN_IOCTL:
+ if(rt_codec.number < 2)
+ break;
+ set_digital_boost_gain(codec, *(buf), *(buf + 1));
+ break;
+
+ case RT_SET_CODEC_NOISE_GATE_IOCTL:
+ if(rt_codec.number < 4)
+ break;
+ set_noise_gate(codec, *(buf), *(buf + 1),
+ *(buf + 2), *(buf + 3));
+ break;
+
+ case RT_SET_CODEC_DRC_AGC_COMP_IOCTL:
+ if(rt_codec.number < 2)
+ break;
+ set_drc_agc_compression(codec, *(buf), *(buf + 1));
+ break;
+
+ case RT_SET_CODEC_WNR_ENABLE_IOCTL:
+ if (NULL == ioctl_ops->index_update_bits)
+ break;
+
+ ioctl_ops->index_update_bits(codec, RT3261_WND_1,
+ RT3261_WND_MASK, *(buf) << RT3261_WND_SFT );
+ break;
+
+ case RT_GET_CODEC_DRC_AGC_ENABLE_IOCTL:
+ if(rt_codec.number < 2)
+ break;
+ get_drc_agc_enable(codec, (buf), (buf + 1));
+ if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_GET_CODEC_DRC_AGC_PAR_IOCTL:
+ if(rt_codec.number < 4)
+ break;
+ get_drc_agc_parameters(codec, (buf), (buf + 1),
+ (buf + 2), (buf + 3));
+ if (copy_to_user(rt_codec.buf, buf,
+ sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_GET_CODEC_DIGI_BOOST_GAIN_IOCTL:
+ if(rt_codec.number < 2)
+ break;
+ get_digital_boost_gain(codec, (buf), (buf + 1));
+ if (copy_to_user(rt_codec.buf, buf,
+ sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_GET_CODEC_NOISE_GATE_IOCTL:
+ if(rt_codec.number < 4)
+ break;
+ get_noise_gate(codec, (buf), (buf + 1), (buf + 2), (buf + 3));
+ if (copy_to_user(rt_codec.buf, buf,
+ sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_GET_CODEC_DRC_AGC_COMP_IOCTL:
+ if(rt_codec.number < 2)
+ break;
+ get_drc_agc_compression(codec, (buf), (buf + 1));
+ if (copy_to_user(rt_codec.buf, buf,
+ sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_GET_CODEC_SPK_VOL_IOCTL:
+ *buf = (snd_soc_read(codec, RT3261_SPK_VOL) & RT3261_L_VOL_MASK)
+ >> RT3261_L_VOL_SFT;
+ if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_GET_CODEC_MIC_GAIN_IOCTL:
+ *buf = (snd_soc_read(codec, RT3261_IN1_IN2) & RT3261_BST_MASK1)
+ >> RT3261_BST_SFT1;
+ if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_GET_CODEC_HWEQ_IOCTL:
+ case RT_GET_CODEC_3D_SPK_IOCTL:
+ case RT_GET_CODEC_MP3PLUS_IOCTL:
+ case RT_GET_CODEC_3D_HEADPHONE_IOCTL:
+ case RT_GET_CODEC_BASS_BACK_IOCTL:
+ case RT_GET_CODEC_DIPOLE_SPK_IOCTL:
+ default:
+ break;
+ }
+
+ kfree(buf);
+ return 0;
+
+err:
+ kfree(buf);
+ return -EFAULT;
+}
+EXPORT_SYMBOL_GPL(rt3261_ioctl_common);
--- /dev/null
+/*
+ * rt3261_ioctl.h -- RT3261 ALSA SoC audio driver IO control
+ *
+ * Copyright 2012 Realtek Microelectronics
+ * Author: Bard <bardliao@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT3261_IOCTL_H__
+#define __RT3261_IOCTL_H__
+
+#include <sound/hwdep.h>
+#include <linux/ioctl.h>
+
+enum {
+ NORMAL=0,
+ CLUB,
+ DANCE,
+ LIVE,
+ POP,
+ ROCK,
+ OPPO,
+ TREBLE,
+ BASS,
+ MODE_NUM,
+};
+
+#define EQ_REG_NUM 16
+typedef struct hweq_s {
+ unsigned int reg[EQ_REG_NUM];
+ unsigned int value[EQ_REG_NUM];
+ unsigned int ctrl;
+} hweq_t;
+
+int rt3261_ioctl_common(struct snd_hwdep *hw, struct file *file,
+ unsigned int cmd, unsigned long arg);
+
+#endif /* __RT3261_IOCTL_H__ */
--- /dev/null
+/*
+ * rt5623.c -- RT5623 ALSA SoC audio codec driver
+ *
+ * Copyright 2011 Realtek Semiconductor Corp.
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "rt5623.h"
+
+static struct i2c_client *i2c_client;
+
+static int codec_write(struct i2c_client *client, unsigned int reg,
+ unsigned int value)
+{
+ u8 data[3];
+ int ret;
+
+ data[0] = reg;
+ data[1] = (value >> 8) & 0xff;
+ data[2] = value & 0xff;
+
+ //printk("%s: reg=0x%x value=0x%x\n",__func__,reg,value);
+ if (i2c_master_send(client, data, 3) == 3)
+ return 0;
+ else
+ return -EIO;
+}
+
+static unsigned int codec_read(struct i2c_client *client,
+ unsigned int r)
+{
+ struct i2c_msg xfer[2];
+ u8 reg = r;
+ u16 data;
+ int ret;
+
+ /* Write register */
+ xfer[0].addr = client->addr;
+ xfer[0].flags = 0;
+ xfer[0].len = 1;
+ xfer[0].buf = ®
+
+ /* Read data */
+ xfer[1].addr = client->addr;
+ xfer[1].flags = I2C_M_RD;
+ xfer[1].len = 2;
+ xfer[1].buf = (u8 *)&data;
+
+ ret = i2c_transfer(client->adapter, xfer, 2);
+ if (ret != 2) {
+ dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
+ return 0;
+ }
+ //printk("%s: reg=0x%x value=0x%x\n",__func__,reg,(data >> 8) | ((data & 0xff) << 8));
+
+ return (data >> 8) | ((data & 0xff) << 8);
+}
+
+struct rt5623_reg {
+ u8 reg_index;
+ u16 reg_value;
+};
+
+static struct rt5623_reg init_data[] = {
+ {RT5623_PWR_MANAG_ADD3 , 0x8000},
+ {RT5623_PWR_MANAG_ADD2 , 0x2000},
+ {RT5623_LINE_IN_VOL , 0xe808},
+ {RT5623_STEREO_DAC_VOL , 0x6808},
+ {RT5623_OUTPUT_MIXER_CTRL , 0x1400},
+ {RT5623_ADC_REC_GAIN , 0xf58b},
+ {RT5623_ADC_REC_MIXER , 0x6f6f},
+ {RT5623_AUDIO_INTERFACE , 0x8000},
+ {RT5623_STEREO_AD_DA_CLK_CTRL , 0x0a2d},
+ {RT5623_PWR_MANAG_ADD1 , 0x8000},
+ {RT5623_PWR_MANAG_ADD2 , 0x27f3},
+ {RT5623_PWR_MANAG_ADD3 , 0x9c00},
+ {RT5623_SPK_OUT_VOL , 0x0000},
+};
+#define RT5623_INIT_REG_NUM ARRAY_SIZE(init_data)
+
+static int rt5623_reg_init(struct i2c_client *client)
+{
+ int i;
+
+ for (i = 0; i < RT5623_INIT_REG_NUM; i++)
+ codec_write(client, init_data[i].reg_index,
+ init_data[i].reg_value);
+
+ return 0;
+}
+
+static int rt5623_reset(struct i2c_client *client)
+{
+ return codec_write(client, RT5623_RESET, 0);
+}
+
+void rt5623_on(void)
+{
+ printk("enter %s\n",__func__);
+ rt5623_reset(i2c_client);
+ rt5623_reg_init(i2c_client);
+}
+EXPORT_SYMBOL(rt5623_on);
+
+void rt5623_off(void)
+{
+ printk("enter %s\n",__func__);
+ codec_write(i2c_client, RT5623_SPK_OUT_VOL, 0x8080);
+ rt5623_reset(i2c_client);
+ codec_write(i2c_client, RT5623_PWR_MANAG_ADD3, 0x0000);
+ codec_write(i2c_client, RT5623_PWR_MANAG_ADD2, 0x0000);
+ codec_write(i2c_client, RT5623_PWR_MANAG_ADD1, 0x0000);
+}
+EXPORT_SYMBOL(rt5623_off);
+
+static const struct i2c_device_id rt5623_i2c_id[] = {
+ { "rt5623", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, rt5623_i2c_id);
+
+static int __devinit rt5623_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ pr_info("%s(%d)\n", __func__, __LINE__);
+
+ i2c_client = i2c;
+ rt5623_reset(i2c);
+
+ rt5623_on( );
+
+ return 0;
+}
+
+static int __devexit rt5623_i2c_remove(struct i2c_client *i2c)
+{
+ return 0;
+}
+
+struct i2c_driver rt5623_i2c_driver = {
+ .driver = {
+ .name = "rt5623",
+ .owner = THIS_MODULE,
+ },
+ .probe = rt5623_i2c_probe,
+ .remove = __devexit_p(rt5623_i2c_remove),
+ .id_table = rt5623_i2c_id,
+};
+
+static int __init rt5623_modinit(void)
+{
+ return i2c_add_driver(&rt5623_i2c_driver);
+}
+module_init(rt5623_modinit);
+
+static void __exit rt5623_modexit(void)
+{
+ i2c_del_driver(&rt5623_i2c_driver);
+}
+module_exit(rt5623_modexit);
+
+MODULE_DESCRIPTION("ASoC RT5623 driver");
+MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * rt5623.h -- RT5623 ALSA SoC audio driver
+ *
+ * Copyright 2011 Realtek Microelectronics
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT5623_H__
+#define __RT5623_H__
+
+#define RT5623_RESET 0x00
+#define RT5623_SPK_OUT_VOL 0x02
+#define RT5623_HP_OUT_VOL 0x04
+#define RT5623_MONO_AUX_OUT_VOL 0x06
+#define RT5623_AUXIN_VOL 0x08
+#define RT5623_LINE_IN_VOL 0x0a
+#define RT5623_STEREO_DAC_VOL 0x0c
+#define RT5623_MIC_VOL 0x0e
+#define RT5623_MIC_ROUTING_CTRL 0x10
+#define RT5623_ADC_REC_GAIN 0x12
+#define RT5623_ADC_REC_MIXER 0x14
+#define RT5623_SOFT_VOL_CTRL_TIME 0x16
+#define RT5623_OUTPUT_MIXER_CTRL 0x1c
+#define RT5623_MIC_CTRL 0x22
+#define RT5623_AUDIO_INTERFACE 0x34
+#define RT5623_STEREO_AD_DA_CLK_CTRL 0x36
+#define RT5623_COMPANDING_CTRL 0x38
+#define RT5623_PWR_MANAG_ADD1 0x3a
+#define RT5623_PWR_MANAG_ADD2 0x3c
+#define RT5623_PWR_MANAG_ADD3 0x3e
+#define RT5623_ADD_CTRL_REG 0x40
+#define RT5623_GLOBAL_CLK_CTRL_REG 0x42
+#define RT5623_PLL_CTRL 0x44
+#define RT5623_GPIO_OUTPUT_PIN_CTRL 0x4a
+#define RT5623_GPIO_PIN_CONFIG 0x4c
+#define RT5623_GPIO_PIN_POLARITY 0x4e
+#define RT5623_GPIO_PIN_STICKY 0x50
+#define RT5623_GPIO_PIN_WAKEUP 0x52
+#define RT5623_GPIO_PIN_STATUS 0x54
+#define RT5623_GPIO_PIN_SHARING 0x56
+#define RT5623_OVER_TEMP_CURR_STATUS 0x58
+#define RT5623_JACK_DET_CTRL 0x5a
+#define RT5623_MISC_CTRL 0x5e
+#define RT5623_PSEDUEO_SPATIAL_CTRL 0x60
+#define RT5623_EQ_CTRL 0x62
+#define RT5623_EQ_MODE_ENABLE 0x66
+#define RT5623_AVC_CTRL 0x68
+#define RT5623_HID_CTRL_INDEX 0x6a
+#define RT5623_HID_CTRL_DATA 0x6c
+#define RT5623_VENDOR_ID1 0x7c
+#define RT5623_VENDOR_ID2 0x7e
+
+/* global definition */
+#define RT5623_L_MUTE (0x1 << 15)
+#define RT5623_L_MUTE_SFT 15
+#define RT5623_L_ZC (0x1 << 14)
+#define RT5623_L_SM (0x1 << 13)
+#define RT5623_L_VOL_MASK (0x1f << 8)
+#define RT5623_L_VOL_SFT 8
+#define RT5623_ADCL_VOL_SFT 7
+#define RT5623_R_MUTE (0x1 << 7)
+#define RT5623_R_MUTE_SFT 7
+#define RT5623_R_ZC (0x1 << 6)
+#define RT5623_R_VOL_MASK (0x1f)
+#define RT5623_R_VOL_SFT 0
+#define RT5623_M_HPMIX (0x1 << 15)
+#define RT5623_M_SPKMIX (0x1 << 14)
+#define RT5623_M_MONOMIX (0x1 << 13)
+#define RT5623_SPK_CLASS_AB 0
+#define RT5623_SPK_CLASS_D 1
+
+/* AUXIN Volume (0x08) */
+#define RT5623_M_AXI_TO_HPM (0x1 << 15)
+#define RT5623_M_AXI_TO_HPM_SFT 15
+#define RT5623_M_AXI_TO_SPKM (0x1 << 14)
+#define RT5623_M_AXI_TO_SPKM_SFT 14
+#define RT5623_M_AXI_TO_MOM (0x1 << 13)
+#define RT5623_M_AXI_TO_MOM_SFT 13
+
+/* LINE_IN Volume (0x0a) */
+#define RT5623_M_LINEIN_TO_HPM (0x1 << 15)
+#define RT5623_M_LINEIN_TO_HPM_SFT 15
+#define RT5623_M_LINEIN_TO_SPKM (0x1 << 14)
+#define RT5623_M_LINEIN_TO_SPKM_SFT 14
+#define RT5623_M_LINEIN_TO_MOM (0x1 << 13)
+#define RT5623_M_LINEIN_TO_MOM_SFT 13
+
+/* Stereo DAC Volume (0x0c) */
+#define RT5623_M_DAC_TO_HPM (0x1 << 15)
+#define RT5623_M_DAC_TO_HPM_SFT 15
+#define RT5623_M_DAC_TO_SPKM (0x1 << 14)
+#define RT5623_M_DAC_TO_SPKM_SFT 14
+#define RT5623_M_DAC_TO_MOM (0x1 << 13)
+#define RT5623_M_DAC_TO_MOM_SFT 13
+
+/* Mic Routing Control(0x10) */
+#define RT5623_M_MIC1_TO_HP_MIXER (0x1 << 15)
+#define RT5623_M_MIC1_TO_HP_MIXER_SFT 15
+#define RT5623_M_MIC1_TO_SPK_MIXER (0x1 << 14)
+#define RT5623_M_MIC1_TO_SPK_MIXER_SFT 14
+#define RT5623_M_MIC1_TO_MONO_MIXER (0x1 << 13)
+#define RT5623_M_MIC1_TO_MONO_MIXER_SFT 13
+#define RT5623_MIC1_DIFF_INPUT_CTRL (0x1 << 12)
+#define RT5623_MIC1_DIFF_INPUT_CTRL_SFT 12
+#define RT5623_M_MIC2_TO_HP_MIXER (0x1 << 7)
+#define RT5623_M_MIC2_TO_HP_MIXER_SFT 7
+#define RT5623_M_MIC2_TO_SPK_MIXER (0x1 << 6)
+#define RT5623_M_MIC2_TO_SPK_MIXER_SFT 6
+#define RT5623_M_MIC2_TO_MONO_MIXER (0x1 << 5)
+#define RT5623_M_MIC2_TO_MONO_MIXER_SFT 5
+#define RT5623_MIC2_DIFF_INPUT_CTRL (0x1 << 4)
+#define RT5623_MIC2_DIFF_INPUT_CTRL_SFT 4
+
+/* ADC Record Gain (0x12) */
+#define RT5623_M_ADC_L_TO_HP_MIXER (0x1 << 15)
+#define RT5623_M_ADC_L_TO_HP_MIXER_SFT 15
+#define RT5623_M_ADC_R_TO_HP_MIXER (0x1 << 14)
+#define RT5623_M_ADC_R_TO_HP_MIXER_SFT 14
+#define RT5623_M_ADC_L_TO_MONO_MIXER (0x1 << 13)
+#define RT5623_M_ADC_L_TO_MONO_MIXER_SFT 13
+#define RT5623_M_ADC_R_TO_MONO_MIXER (0x1 << 12)
+#define RT5623_M_ADC_R_TO_MONO_MIXER_SFT 12
+#define RT5623_ADC_L_GAIN_MASK (0x1f << 7)
+#define RT5623_ADC_L_ZC_DET (0x1 << 6)
+#define RT5623_ADC_R_ZC_DET (0x1 << 5)
+#define RT5623_ADC_R_GAIN_MASK (0x1f << 0)
+
+/* ADC Input Mixer Control (0x14) */
+#define RT5623_M_MIC1_TO_ADC_L_MIXER (0x1 << 14)
+#define RT5623_M_MIC1_TO_ADC_L_MIXER_SFT 14
+#define RT5623_M_MIC2_TO_ADC_L_MIXER (0x1 << 13)
+#define RT5623_M_MIC2_TO_ADC_L_MIXER_SFT 13
+#define RT5623_M_LINEIN_L_TO_ADC_L_MIXER (0x1 << 12)
+#define RT5623_M_LINEIN_L_TO_ADC_L_MIXER_SFT 12
+#define RT5623_M_AUXIN_L_TO_ADC_L_MIXER (0x1 << 11)
+#define RT5623_M_AUXIN_L_TO_ADC_L_MIXER_SFT 11
+#define RT5623_M_HPMIXER_L_TO_ADC_L_MIXER (0x1 << 10)
+#define RT5623_M_HPMIXER_L_TO_ADC_L_MIXER_SFT 10
+#define RT5623_M_SPKMIXER_L_TO_ADC_L_MIXER (0x1 << 9)
+#define RT5623_M_SPKMIXER_L_TO_ADC_L_MIXER_SFT 9
+#define RT5623_M_MONOMIXER_L_TO_ADC_L_MIXER (0x1 << 8)
+#define RT5623_M_MONOMIXER_L_TO_ADC_L_MIXER_SFT 8
+#define RT5623_M_MIC1_TO_ADC_R_MIXER (0x1 << 6)
+#define RT5623_M_MIC1_TO_ADC_R_MIXER_SFT 6
+#define RT5623_M_MIC2_TO_ADC_R_MIXER (0x1 << 5)
+#define RT5623_M_MIC2_TO_ADC_R_MIXER_SFT 5
+#define RT5623_M_LINEIN_R_TO_ADC_R_MIXER (0x1 << 4)
+#define RT5623_M_LINEIN_R_TO_ADC_R_MIXER_SFT 4
+#define RT5623_M_AUXIN_R_TO_ADC_R_MIXER (0x1 << 3)
+#define RT5623_M_AUXIN_R_TO_ADC_R_MIXER_SFT 3
+#define RT5623_M_HPMIXER_R_TO_ADC_R_MIXER (0x1 << 2)
+#define RT5623_M_HPMIXER_R_TO_ADC_R_MIXER_SFT 2
+#define RT5623_M_SPKMIXER_R_TO_ADC_R_MIXER (0x1 << 1)
+#define RT5623_M_SPKMIXER_R_TO_ADC_R_MIXER_SFT 1
+#define RT5623_M_MONOMIXER_R_TO_ADC_R_MIXER (0x1 << 0)
+#define RT5623_M_MONOMIXER_R_TO_ADC_R_MIXER_SFT 0
+
+/* Output Mixer Control(0x1c) */
+#define RT5623_SPKOUT_N_SOUR_MASK (0x3 << 14)
+#define RT5623_SPKOUT_N_SOUR_SFT 14
+#define RT5623_SPKOUT_N_SOUR_LN (0x2 << 14)
+#define RT5623_SPKOUT_N_SOUR_RP (0x1 << 14)
+#define RT5623_SPKOUT_N_SOUR_RN (0x0 << 14)
+#define RT5623_SPK_OUTPUT_CLASS_MASK (0x1 << 13)
+#define RT5623_SPK_OUTPUT_CLASS_SFT 13
+#define RT5623_SPK_OUTPUT_CLASS_AB (0x0 << 13)
+#define RT5623_SPK_OUTPUT_CLASS_D (0x1 << 13)
+#define RT5623_SPK_CLASS_AB_S_AMP (0x0 << 12)
+#define RT5623_SPK_CALSS_AB_W_AMP (0x1 << 12)
+#define RT5623_SPKOUT_INPUT_SEL_MASK (0x3 << 10)
+#define RT5623_SPKOUT_INPUT_SEL_SFT 10
+#define RT5623_SPKOUT_INPUT_SEL_MONOMIXER (0x3 << 10)
+#define RT5623_SPKOUT_INPUT_SEL_SPKMIXER (0x2 << 10)
+#define RT5623_SPKOUT_INPUT_SEL_HPMIXER (0x1 << 10)
+#define RT5623_SPKOUT_INPUT_SEL_VMID (0x0 << 10)
+#define RT5623_HPL_INPUT_SEL_HPLMIXER_MASK (0x1 << 9)
+#define RT5623_HPL_INPUT_SEL_HPLMIXER_SFT 9
+#define RT5623_HPL_INPUT_SEL_HPLMIXER (0x1 << 9)
+#define RT5623_HPR_INPUT_SEL_HPRMIXER_MASK (0x1 << 8)
+#define RT5623_HPR_INPUT_SEL_HPRMIXER_SFT 8
+#define RT5623_HPR_INPUT_SEL_HPRMIXER (0x1 << 8)
+#define RT5623_MONO_AUX_INPUT_SEL_MASK (0x3 << 6)
+#define RT5623_MONO_AUX_INPUT_SEL_SFT 6
+#define RT5623_MONO_AUX_INPUT_SEL_MONO (0x3 << 6)
+#define RT5623_MONO_AUX_INPUT_SEL_SPK (0x2 << 6)
+#define RT5623_MONO_AUX_INPUT_SEL_HP (0x1 << 6)
+#define RT5623_MONO_AUX_INPUT_SEL_VMID (0x0 << 6)
+
+/* Micphone Control define(0x22) */
+#define RT5623_MIC1 1
+#define RT5623_MIC2 2
+#define RT5623_MIC_BIAS_90_PRECNET_AVDD 1
+#define RT5623_MIC_BIAS_75_PRECNET_AVDD 2
+#define RT5623_MIC1_BOOST_CTRL_MASK (0x3 << 10)
+#define RT5623_MIC1_BOOST_CTRL_SFT 10
+#define RT5623_MIC1_BOOST_CTRL_BYPASS 0x0 << 10)
+#define RT5623_MIC1_BOOST_CTRL_20DB (0x1 << 10)
+#define RT5623_MIC1_BOOST_CTRL_30DB (0x2 << 10)
+#define RT5623_MIC1_BOOST_CTRL_40DB (0x3 << 10)
+#define RT5623_MIC2_BOOST_CTRL_MASK (0x3 << 8)
+#define RT5623_MIC2_BOOST_CTRL_SFT 8
+#define RT5623_MIC2_BOOST_CTRL_BYPASS (0x0 << 8)
+#define RT5623_MIC2_BOOST_CTRL_20DB (0x1 << 8)
+#define RT5623_MIC2_BOOST_CTRL_30DB (0x2 << 8)
+#define RT5623_MIC2_BOOST_CTRL_40DB (0x3 << 8)
+#define RT5623_MICBIAS_VOLT_CTRL_MASK (0x1 << 5)
+#define RT5623_MICBIAS_VOLT_CTRL_90P (0x0 << 5)
+#define RT5623_MICBIAS_VOLT_CTRL_75P (0x1 << 5)
+#define RT5623_MICBIAS_SHORT_CURR_DET_MASK (0x3)
+#define RT5623_MICBIAS_SHORT_CURR_DET_600UA (0x0)
+#define RT5623_MICBIAS_SHORT_CURR_DET_1200UA (0x1)
+#define RT5623_MICBIAS_SHORT_CURR_DET_1800UA (0x2)
+
+/* Audio Interface (0x34) */
+#define RT5623_SDP_MASTER_MODE (0x0 << 15)
+#define RT5623_SDP_SLAVE_MODE (0x1 << 15)
+#define RT5623_I2S_PCM_MODE (0x1 << 14)
+#define RT5623_MAIN_I2S_BCLK_POL_CTRL (0x1 << 7)
+ /* 0:ADC data appear at left phase of LRCK
+ * 1:ADC data appear at right phase of LRCK
+ */
+#define RT5623_ADC_DATA_L_R_SWAP (0x1 << 5)
+ /* 0:DAC data appear at left phase of LRCK
+ * 1:DAC data appear at right phase of LRCK
+ */
+#define RT5623_DAC_DATA_L_R_SWAP (0x1 << 4)
+#define RT5623_I2S_DL_MASK (0x3 << 2)
+#define RT5623_I2S_DL_16 (0x0 << 2)
+#define RT5623_I2S_DL_20 (0x1 << 2)
+#define RT5623_I2S_DL_24 (0x2 << 2)
+#define RT5623_I2S_DL_32 (0x3 << 2)
+#define RT5623_I2S_DF_MASK (0x3)
+#define RT5623_I2S_DF_I2S (0x0)
+#define RT5623_I2S_DF_RIGHT (0x1)
+#define RT5623_I2S_DF_LEFT (0x2)
+#define RT5623_I2S_DF_PCM (0x3)
+
+/* Stereo AD/DA Clock Control(0x36h) */
+#define RT5623_I2S_PRE_DIV_MASK (0x7 << 12)
+#define RT5623_I2S_PRE_DIV_1 (0x0 << 12)
+#define RT5623_I2S_PRE_DIV_2 (0x1 << 12)
+#define RT5623_I2S_PRE_DIV_4 (0x2 << 12)
+#define RT5623_I2S_PRE_DIV_8 (0x3 << 12)
+#define RT5623_I2S_PRE_DIV_16 (0x4 << 12)
+#define RT5623_I2S_PRE_DIV_32 (0x5 << 12)
+#define RT5623_I2S_SCLK_DIV_MASK (0x7 << 9)
+#define RT5623_I2S_SCLK_DIV_1 (0x0 << 9)
+#define RT5623_I2S_SCLK_DIV_2 (0x1 << 9)
+#define RT5623_I2S_SCLK_DIV_3 (0x2 << 9)
+#define RT5623_I2S_SCLK_DIV_4 (0x3 << 9)
+#define RT5623_I2S_SCLK_DIV_6 (0x4 << 9)
+#define RT5623_I2S_SCLK_DIV_8 (0x5 << 9)
+#define RT5623_I2S_SCLK_DIV_12 (0x6 << 9)
+#define RT5623_I2S_SCLK_DIV_16 (0x7 << 9)
+#define RT5623_I2S_WCLK_DIV_PRE_MASK (0xF << 5)
+#define RT5623_I2S_WCLK_PRE_DIV_1 (0x0 << 5)
+#define RT5623_I2S_WCLK_PRE_DIV_2 (0x1 << 5)
+#define RT5623_I2S_WCLK_PRE_DIV_3 (0x2 << 5)
+#define RT5623_I2S_WCLK_PRE_DIV_4 (0x3 << 5)
+#define RT5623_I2S_WCLK_PRE_DIV_5 (0x4 << 5)
+#define RT5623_I2S_WCLK_PRE_DIV_6 (0x5 << 5)
+#define RT5623_I2S_WCLK_PRE_DIV_7 (0x6 << 5)
+#define RT5623_I2S_WCLK_PRE_DIV_8 (0x7 << 5)
+#define RT5623_I2S_WCLK_DIV_MASK (0x7 << 2)
+#define RT5623_I2S_WCLK_DIV_2 (0x0 << 2)
+#define RT5623_I2S_WCLK_DIV_4 (0x1 << 2)
+#define RT5623_I2S_WCLK_DIV_8 (0x2 << 2)
+#define RT5623_I2S_WCLK_DIV_16 (0x3 << 2)
+#define RT5623_I2S_WCLK_DIV_32 (0x4 << 2)
+#define RT5623_ADDA_FILTER_CLK_SEL_256FS (0 << 1)
+#define RT5623_ADDA_FILTER_CLK_SEL_384FS (1 << 1)
+#define RT5623_ADDA_OSR_SEL_64FS (0)
+#define RT5623_ADDA_OSR_SEL_128FS (1)
+
+/* Power managment addition 1 (0x3a) */
+#define RT5623_PWR_MAIN_I2S_EN (0x1 << 15)
+#define RT5623_PWR_MAIN_I2S_EN_BIT 15
+#define RT5623_PWR_ZC_DET_PD_EN (0x1 << 14)
+#define RT5623_PWR_ZC_DET_PD_EN_BIT 14
+#define RT5623_PWR_MIC1_BIAS_EN (0x1 << 11)
+#define RT5623_PWR_MIC1_BIAS_EN_BIT 11
+#define RT5623_PWR_SHORT_CURR_DET_EN (0x1 << 10)
+#define RT5623_PWR_SHORT_CURR_DET_EN_BIT 10
+#define RT5623_PWR_SOFTGEN_EN (0x1 << 8)
+#define RT5623_PWR_SOFTGEN_EN_BIT 8
+#define RT5623_PWR_DEPOP_BUF_HP (0x1 << 6)
+#define RT5623_PWR_DEPOP_BUF_HP_BIT 6
+#define RT5623_PWR_HP_OUT_AMP (0x1 << 5)
+#define RT5623_PWR_HP_OUT_AMP_BIT 5
+#define RT5623_PWR_HP_OUT_ENH_AMP (0x1 << 4)
+#define RT5623_PWR_HP_OUT_ENH_AMP_BIT 4
+#define RT5623_PWR_DEPOP_BUF_AUX (0x1 << 2)
+#define RT5623_PWR_DEPOP_BUF_AUX_BIT 2
+#define RT5623_PWR_AUX_OUT_AMP (0x1 << 1)
+#define RT5623_PWR_AUX_OUT_AMP_BIT 1
+#define RT5623_PWR_AUX_OUT_ENH_AMP (0x1)
+#define RT5623_PWR_AUX_OUT_ENH_AMP_BIT 0
+
+/* Power managment addition 2 (0x3c) */
+#define RT5623_PWR_CLASS_AB (0x1 << 15)
+#define RT5623_PWR_CLASS_AB_BIT 15
+#define RT5623_PWR_CLASS_D (0x1 << 14)
+#define RT5623_PWR_CLASS_D_BIT 14
+#define RT5623_PWR_VREF (0x1 << 13)
+#define RT5623_PWR_VREF_BIT 13
+#define RT5623_PWR_PLL (0x1 << 12)
+#define RT5623_PWR_PLL_BIT 12
+#define RT5623_PWR_DAC_REF_CIR (0x1 << 10)
+#define RT5623_PWR_DAC_REF_CIR_BIT 10
+#define RT5623_PWR_L_DAC_CLK (0x1 << 9)
+#define RT5623_PWR_L_DAC_CLK_BIT 9
+#define RT5623_PWR_R_DAC_CLK (0x1 << 8)
+#define RT5623_PWR_R_DAC_CLK_BIT 8
+#define RT5623_PWR_L_ADC_CLK_GAIN (0x1 << 7)
+#define RT5623_PWR_L_ADC_CLK_GAIN_BIT 7
+#define RT5623_PWR_R_ADC_CLK_GAIN (0x1 << 6)
+#define RT5623_PWR_R_ADC_CLK_GAIN_BIT 6
+#define RT5623_PWR_L_HP_MIXER (0x1 << 5)
+#define RT5623_PWR_L_HP_MIXER_BIT 5
+#define RT5623_PWR_R_HP_MIXER (0x1 << 4)
+#define RT5623_PWR_R_HP_MIXER_BIT 4
+#define RT5623_PWR_SPK_MIXER (0x1 << 3)
+#define RT5623_PWR_SPK_MIXER_BIT 3
+#define RT5623_PWR_MONO_MIXER (0x1 << 2)
+#define RT5623_PWR_MONO_MIXER_BIT 2
+#define RT5623_PWR_L_ADC_REC_MIXER (0x1 << 1)
+#define RT5623_PWR_L_ADC_REC_MIXER_BIT 1
+#define RT5623_PWR_R_ADC_REC_MIXER (0x1)
+#define RT5623_PWR_R_ADC_REC_MIXER_BIT 0
+
+/* Power managment addition 3 (0x3e) */
+#define RT5623_PWR_MAIN_BIAS (0x1 << 15)
+#define RT5623_PWR_MAIN_BIAS_BIT 15
+#define RT5623_PWR_AUXOUT_L_VOL_AMP (0x1 << 14)
+#define RT5623_PWR_AUXOUT_L_VOL_AMP_BIT 14
+#define RT5623_PWR_AUXOUT_R_VOL_AMP (0x1 << 13)
+#define RT5623_PWR_AUXOUT_R_VOL_AMP_BIT 13
+#define RT5623_PWR_SPK_OUT (0x1 << 12)
+#define RT5623_PWR_SPK_OUT_BIT 12
+#define RT5623_PWR_HP_L_OUT_VOL (0x1 << 10)
+#define RT5623_PWR_HP_L_OUT_VOL_BIT 10
+#define RT5623_PWR_HP_R_OUT_VOL (0x1 << 9)
+#define RT5623_PWR_HP_R_OUT_VOL_BIT 9
+#define RT5623_PWR_LINEIN_L_VOL (0x1 << 7)
+#define RT5623_PWR_LINEIN_L_VOL_BIT 7
+#define RT5623_PWR_LINEIN_R_VOL (0x1 << 6)
+#define RT5623_PWR_LINEIN_R_VOL_BIT 6
+#define RT5623_PWR_AUXIN_L_VOL (0x1 << 5)
+#define RT5623_PWR_AUXIN_L_VOL_BIT 5
+#define RT5623_PWR_AUXIN_R_VOL (0x1 << 4)
+#define RT5623_PWR_AUXIN_R_VOL_BIT 4
+#define RT5623_PWR_MIC1_FUN_CTRL (0x1 << 3)
+#define RT5623_PWR_MIC1_FUN_CTRL_BIT 3
+#define RT5623_PWR_MIC2_FUN_CTRL (0x1 << 2)
+#define RT5623_PWR_MIC2_FUN_CTRL_BIT 2
+#define RT5623_PWR_MIC1_BOOST_MIXER (0x1 << 1)
+#define RT5623_PWR_MIC1_BOOST_MIXER_BIT 1
+#define RT5623_PWR_MIC2_BOOST_MIXER (0x1)
+#define RT5623_PWR_MIC2_BOOST_MIXER_BIT 0
+
+/* Additional Control Register (0x40) */
+#define RT5623_AUXOUT_SEL_DIFF (0x1 << 15)
+#define RT5623_AUXOUT_SEL_SE (0x1 << 15)
+#define RT5623_SPK_AB_AMP_CTRL_MASK (0x7 << 12)
+#define RT5623_SPK_AB_AMP_CTRL_RATIO_225 (0x0 << 12)
+#define RT5623_SPK_AB_AMP_CTRL_RATIO_200 (0x1 << 12)
+#define RT5623_SPK_AB_AMP_CTRL_RATIO_175 (0x2 << 12)
+#define RT5623_SPK_AB_AMP_CTRL_RATIO_150 (0x3 << 12)
+#define RT5623_SPK_AB_AMP_CTRL_RATIO_125 (0x4 << 12)
+#define RT5623_SPK_AB_AMP_CTRL_RATIO_100 (0x5 << 12)
+#define RT5623_SPK_D_AMP_CTRL_MASK (0x3 << 10)
+#define RT5623_SPK_D_AMP_CTRL_RATIO_175 (0x0 << 10)
+#define RT5623_SPK_D_AMP_CTRL_RATIO_150 (0x1 << 10)
+#define RT5623_SPK_D_AMP_CTRL_RATIO_125 (0x2 << 10)
+#define RT5623_SPK_D_AMP_CTRL_RATIO_100 (0x3 << 10)
+#define RT5623_STEREO_DAC_HI_PASS_FILTER_EN (0x1 << 9)
+#define RT5623_STEREO_ADC_HI_PASS_FILTER_EN (0x1 << 8)
+#define RT5623_DIG_VOL_BOOST_MASK (0x3 << 4)
+#define RT5623_DIG_VOL_BOOST_0DB (0x0 << 4)
+#define RT5623_DIG_VOL_BOOST_6DB (0x1 << 4)
+#define RT5623_DIG_VOL_BOOST_12DB (0x2 << 4)
+#define RT5623_DIG_VOL_BOOST_18DB (0x3 << 4)
+
+/* Global Clock Control Register (0x42) */
+#define RT5623_SYSCLK_SOUR_SEL_MASK (0x1 << 15)
+#define RT5623_SYSCLK_SOUR_SEL_MCLK (0x0 << 15)
+#define RT5623_SYSCLK_SOUR_SEL_PLL (0x1 << 15)
+#define RT5623_PLLCLK_SOUR_SEL_MCLK (0x0 << 14)
+#define RT5623_PLLCLK_SOUR_SEL_BITCLK (0x1 << 14)
+#define RT5623_PLLCLK_DIV_RATIO_MASK (0x3 << 1)
+#define RT5623_PLLCLK_DIV_RATIO_DIV1 (0x0 << 1)
+#define RT5623_PLLCLK_DIV_RATIO_DIV2 (0x1 << 1)
+#define RT5623_PLLCLK_DIV_RATIO_DIV4 (0x2 << 1)
+#define RT5623_PLLCLK_DIV_RATIO_DIV8 (0x3 << 1)
+#define PLLCLK_PRE_DIV1 (0x0)
+#define PLLCLK_PRE_DIV2 (0x1)
+
+/* GPIO Pin Configuration (0x4c) */
+#define RT5623_GPIO_PIN_MASK (0x1 << 1)
+#define RT5623_GPIO_PIN_SET_INPUT (0x1 << 1)
+#define RT5623_GPIO_PIN_SET_OUTPUT (0x0 << 1)
+
+/* Pin Sharing (0x56) */
+#define RT5623_LINEIN_L_PIN_SHARING (0x1 << 15)
+#define RT5623_LINEIN_L_PIN_AS_LINEIN_L (0x0 << 15)
+#define RT5623_LINEIN_L_PIN_AS_JD1 (0x1 << 15)
+#define RT5623_LINEIN_R_PIN_SHARING (0x1 << 14)
+#define RT5623_LINEIN_R_PIN_AS_LINEIN_R (0x0 << 14)
+#define RT5623_LINEIN_R_PIN_AS_JD2 (0x1 << 14)
+#define RT5623_GPIO_PIN_SHARE (0x3)
+#define RT5623_GPIO_PIN_AS_GPIO (0x0)
+#define RT5623_GPIO_PIN_AS_IRQOUT (0x1)
+#define RT5623_GPIO_PIN_AS_PLLOUT (0x3)
+
+/* Jack Detect Control Register (0x5a) */
+#define RT5623_JACK_DETECT_MASK (0x3 << 14)
+#define RT5623_JACK_DETECT_USE_JD2 (0x3 << 14)
+#define RT5623_JACK_DETECT_USE_JD1 (0x2 << 14)
+#define RT5623_JACK_DETECT_USE_GPIO (0x1 << 14)
+#define RT5623_JACK_DETECT_OFF (0x0 << 14)
+#define RT5623_SPK_EN_IN_HI (0x1 << 11)
+#define RT5623_AUX_R_EN_IN_HI (0x1 << 10)
+#define RT5623_AUX_L_EN_IN_HI (0x1 << 9)
+#define RT5623_HP_EN_IN_HI (0x1 << 8)
+#define RT5623_SPK_EN_IN_LO (0x1 << 7)
+#define RT5623_AUX_R_EN_IN_LO (0x1 << 6)
+#define RT5623_AUX_L_EN_IN_LO (0x1 << 5)
+#define RT5623_HP_EN_IN_LO (0x1 << 4)
+
+/* MISC CONTROL (0x5e) */
+#define RT5623_DISABLE_FAST_VREG (0x1 << 15)
+#define RT5623_SPK_CLASS_AB_OC_PD (0x1 << 13)
+#define RT5623_SPK_CLASS_AB_OC_DET (0x1 << 12)
+#define RT5623_HP_DEPOP_MODE3_EN (0x1 << 10)
+#define RT5623_HP_DEPOP_MODE2_EN (0x1 << 9)
+#define RT5623_HP_DEPOP_MODE1_EN (0x1 << 8)
+#define RT5623_AUXOUT_DEPOP_MODE3_EN (0x1 << 6)
+#define RT5623_AUXOUT_DEPOP_MODE2_EN (0x1 << 5)
+#define RT5623_AUXOUT_DEPOP_MODE1_EN (0x1 << 4)
+#define RT5623_M_DAC_L_INPUT (0x1 << 3)
+#define RT5623_M_DAC_R_INPUT (0x1 << 2)
+#define RT5623_IRQOUT_INV_CTRL (0x1 << 0)
+
+/* Psedueo Stereo & Spatial Effect Block Control (0x60) */
+#define RT5623_SPATIAL_CTRL_EN (0x1 << 15)
+#define RT5623_ALL_PASS_FILTER_EN (0x1 << 14)
+#define RT5623_PSEUDO_STEREO_EN (0x1 << 13)
+#define RT5623_STEREO_EXPENSION_EN (0x1 << 12)
+#define RT5623_GAIN_3D_PARA_L_MASK (0x7 << 9)
+#define RT5623_GAIN_3D_PARA_L_1_00 (0x0 << 9)
+#define RT5623_GAIN_3D_PARA_L_1_25 (0x1 << 9)
+#define RT5623_GAIN_3D_PARA_L_1_50 (0x2 << 9)
+#define RT5623_GAIN_3D_PARA_L_1_75 (0x3 << 9)
+#define RT5623_GAIN_3D_PARA_L_2_00 (0x4 << 9)
+#define RT5623_GAIN_3D_PARA_R_MASK (0x7 << 6)
+#define RT5623_GAIN_3D_PARA_R_1_00 (0x0 << 6)
+#define RT5623_GAIN_3D_PARA_R_1_25 (0x1 << 6)
+#define RT5623_GAIN_3D_PARA_R_1_50 (0x2 << 6)
+#define RT5623_GAIN_3D_PARA_R_1_75 (0x3 << 6)
+#define RT5623_GAIN_3D_PARA_R_2_00 (0x4 << 6)
+#define RT5623_RATIO_3D_L_MASK (0x3 << 4)
+#define RT5623_RATIO_3D_L_0_0 (0x0 << 4)
+#define RT5623_RATIO_3D_L_0_66 (0x1 << 4)
+#define RT5623_RATIO_3D_L_1_0 (0x2 << 4)
+#define RT5623_RATIO_3D_R_MASK (0x3 << 2)
+#define RT5623_RATIO_3D_R_0_0 (0x0 << 2)
+#define RT5623_RATIO_3D_R_0_66 (0x1 << 2)
+#define RT5623_RATIO_3D_R_1_0 (0x2 << 2)
+#define RT5623_APF_MASK (0x3)
+#define RT5623_APF_FOR_48K (0x3)
+#define RT5623_APF_FOR_44_1K (0x2)
+#define RT5623_APF_FOR_32K (0x1)
+
+/* EQ CONTROL (0x62) */
+#define RT5623_EN_HW_EQ_BLK (0x1 << 15)
+#define RT5623_EN_HW_EQ_HPF_MODE (0x1 << 14)
+#define RT5623_EN_HW_EQ_SOUR (0x1 << 11)
+#define RT5623_EN_HW_EQ_HPF (0x1 << 4)
+#define RT5623_EN_HW_EQ_BP3 (0x1 << 3)
+#define RT5623_EN_HW_EQ_BP2 (0x1 << 2)
+#define RT5623_EN_HW_EQ_BP1 (0x1 << 1)
+#define RT5623_EN_HW_EQ_LPF (0x1 << 0)
+
+/* EQ Mode Change Enable (0x66) */
+#define RT5623_EQ_HPF_CHANGE_EN (0x1 << 4)
+#define RT5623_EQ_BP3_CHANGE_EN (0x1 << 3)
+#define RT5623_EQ_BP2_CHANGE_EN (0x1 << 2)
+#define RT5623_EQ_BP1_CHANGE_EN (0x1 << 1)
+#define RT5623_EQ_LPF_CHANGE_EN (0x1 << 0)
+
+/* AVC Control (0x68) */
+#define RT5623_AVC_ENABLE (0x1 << 15)
+#define RT5623_AVC_TARTGET_SEL_MASK (0x1 << 14)
+#define RT5623_AVC_TARTGET_SEL_R (0x1 << 14)
+#define RT5623_AVC_TARTGET_SEL_L (0x0 << 14)
+
+
+#define RT5623_PLL_FR_MCLK 0
+#define RT5623_PLL_FR_BCLK 1
+
+
+#endif /* __RT5623_H__ */
--- /dev/null
+/*
+ * rt_codec_ioctl.h -- RT56XX ALSA SoC audio driver IO control
+ *
+ * Copyright 2012 Realtek Microelectronics
+ * Author: Bard <bardliao@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/spi/spi.h>
+#include <sound/soc.h>
+#include "rt_codec_ioctl.h"
+
+static struct rt_codec_ops rt_codec_ioctl_ops;
+
+#if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
+#define RT_CE_CODEC_HWDEP_NAME "rt_codec hwdep "
+static int rt_codec_hwdep_open(struct snd_hwdep *hw, struct file *file)
+{
+ struct snd_soc_codec *codec = hw->private_data;
+ dev_dbg(codec->dev, "%s()\n", __func__);
+ return 0;
+}
+
+static int rt_codec_hwdep_release(struct snd_hwdep *hw, struct file *file)
+{
+ struct snd_soc_codec *codec = hw->private_data;
+ dev_dbg(codec->dev, "%s()\n", __func__);
+ return 0;
+}
+
+static int rt_codec_hwdep_ioctl_common(struct snd_hwdep *hw,
+ struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct snd_soc_codec *codec = hw->private_data;
+ struct rt_codec_cmd __user *_rt_codec = (struct rt_codec_cmd *)arg;
+ struct rt_codec_cmd rt_codec;
+ int *buf, *p;
+
+ if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec))) {
+ dev_err(codec->dev,"copy_from_user faild\n");
+ return -EFAULT;
+ }
+ dev_dbg(codec->dev, "%s(): rt_codec.number=%d, cmd=%d\n",
+ __func__, rt_codec.number, cmd);
+ buf = kmalloc(sizeof(*buf) * rt_codec.number, GFP_KERNEL);
+ if (buf == NULL)
+ return -ENOMEM;
+ if (copy_from_user(buf, rt_codec.buf, sizeof(*buf) * rt_codec.number)) {
+ goto err;
+ }
+
+ switch (cmd) {
+ case RT_READ_CODEC_REG_IOCTL:
+ for (p = buf; p < buf + rt_codec.number / 2; p++) {
+ *(p + rt_codec.number / 2) = snd_soc_read(codec, *p);
+ }
+ if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_WRITE_CODEC_REG_IOCTL:
+ for (p = buf; p < buf + rt_codec.number / 2; p++)
+ snd_soc_write(codec, *p, *(p + rt_codec.number / 2));
+ break;
+
+ case RT_READ_CODEC_INDEX_IOCTL:
+ if (NULL == rt_codec_ioctl_ops.index_read)
+ goto err;
+
+ for (p = buf; p < buf + rt_codec.number / 2; p++)
+ *(p+rt_codec.number/2) = rt_codec_ioctl_ops.index_read(
+ codec, *p);
+ if (copy_to_user(rt_codec.buf, buf,
+ sizeof(*buf) * rt_codec.number))
+ goto err;
+ break;
+
+ case RT_WRITE_CODEC_INDEX_IOCTL:
+ if (NULL == rt_codec_ioctl_ops.index_write)
+ goto err;
+
+ for (p = buf; p < buf + rt_codec.number / 2; p++)
+ rt_codec_ioctl_ops.index_write(codec, *p,
+ *(p+rt_codec.number/2));
+ break;
+
+ default:
+ if (NULL == rt_codec_ioctl_ops.ioctl_common)
+ goto err;
+
+ rt_codec_ioctl_ops.ioctl_common(hw, file, cmd, arg);
+ break;
+ }
+
+ kfree(buf);
+ return 0;
+
+err:
+ kfree(buf);
+ return -EFAULT;
+}
+
+static int rt_codec_codec_dump_reg(struct snd_hwdep *hw,
+ struct file *file, unsigned long arg)
+{
+ struct snd_soc_codec *codec = hw->private_data;
+ struct rt_codec_cmd __user *_rt_codec =(struct rt_codec_cmd *)arg;
+ struct rt_codec_cmd rt_codec;
+ int i, *buf, number = codec->driver->reg_cache_size;
+
+ dev_dbg(codec->dev, "enter %s, number = %d\n", __func__, number);
+ if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec)))
+ return -EFAULT;
+
+ buf = kmalloc(sizeof(*buf) * number, GFP_KERNEL);
+ if (buf == NULL)
+ return -ENOMEM;
+
+ for (i = 0; i < number/2; i++) {
+ buf[i] = i << 1;
+ buf[i + number / 2] = codec->read(codec, buf[i]);
+ }
+ if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * i))
+ goto err;
+ rt_codec.number = number;
+ if (copy_to_user(_rt_codec, &rt_codec, sizeof(rt_codec)))
+ goto err;
+ kfree(buf);
+ return 0;
+
+err:
+ kfree(buf);
+ return -EFAULT;
+}
+
+static int rt_codec_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ switch (cmd) {
+ case RT_READ_ALL_CODEC_REG_IOCTL:
+ return rt_codec_codec_dump_reg(hw, file, arg);
+
+ default:
+ return rt_codec_hwdep_ioctl_common(hw, file, cmd, arg);
+ }
+
+ return 0;
+}
+
+int realtek_ce_init_hwdep(struct snd_soc_codec *codec)
+{
+ struct snd_hwdep *hw;
+ struct snd_card *card = codec->card->snd_card;
+ int err;
+
+ dev_dbg(codec->dev, "enter %s\n", __func__);
+
+ if ((err = snd_hwdep_new(card, RT_CE_CODEC_HWDEP_NAME, 0, &hw)) < 0)
+ return err;
+
+ strcpy(hw->name, RT_CE_CODEC_HWDEP_NAME);
+ hw->private_data = codec;
+ hw->ops.open = rt_codec_hwdep_open;
+ hw->ops.release = rt_codec_hwdep_release;
+ hw->ops.ioctl = rt_codec_hwdep_ioctl;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(realtek_ce_init_hwdep);
+#endif
+
+struct rt_codec_ops *rt_codec_get_ioctl_ops(void)
+{
+ return &rt_codec_ioctl_ops;
+}
+EXPORT_SYMBOL_GPL(rt_codec_get_ioctl_ops);
--- /dev/null
+/*
+ * rt_codec_ioctl.h -- RT56XX ALSA SoC audio driver IO control
+ *
+ * Copyright 2012 Realtek Microelectronics
+ * Author: Bard <bardliao@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT56XX_IOCTL_H__
+#define __RT56XX_IOCTL_H__
+
+#include <sound/hwdep.h>
+#include <linux/ioctl.h>
+
+struct rt_codec_cmd {
+ size_t number;
+ int __user *buf;
+};
+
+struct rt_codec_ops {
+ int (*index_write)(struct snd_soc_codec *codec,
+ unsigned int reg, unsigned int value);
+ unsigned int (*index_read)(struct snd_soc_codec *codec,
+ unsigned int reg);
+ int (*index_update_bits)(struct snd_soc_codec *codec,
+ unsigned int reg, unsigned int mask, unsigned int value);
+ int (*ioctl_common)(struct snd_hwdep *hw, struct file *file,
+ unsigned int cmd, unsigned long arg);
+};
+
+enum {
+ RT_READ_CODEC_REG_IOCTL = _IOR('R', 0x01, struct rt_codec_cmd),
+ RT_WRITE_CODEC_REG_IOCTL = _IOW('R', 0x01, struct rt_codec_cmd),
+ RT_READ_ALL_CODEC_REG_IOCTL = _IOR('R', 0x02, struct rt_codec_cmd),
+ RT_READ_CODEC_INDEX_IOCTL = _IOR('R', 0x03, struct rt_codec_cmd),
+ RT_WRITE_CODEC_INDEX_IOCTL = _IOW('R', 0x03, struct rt_codec_cmd),
+ RT_READ_CODEC_DSP_IOCTL = _IOR('R', 0x04, struct rt_codec_cmd),
+ RT_WRITE_CODEC_DSP_IOCTL = _IOW('R', 0x04, struct rt_codec_cmd),
+ RT_SET_CODEC_HWEQ_IOCTL = _IOW('R', 0x05, struct rt_codec_cmd),
+ RT_GET_CODEC_HWEQ_IOCTL = _IOR('R', 0x05, struct rt_codec_cmd),
+ RT_SET_CODEC_SPK_VOL_IOCTL = _IOW('R', 0x06, struct rt_codec_cmd),
+ RT_GET_CODEC_SPK_VOL_IOCTL = _IOR('R', 0x06, struct rt_codec_cmd),
+ RT_SET_CODEC_MIC_GAIN_IOCTL = _IOW('R', 0x07, struct rt_codec_cmd),
+ RT_GET_CODEC_MIC_GAIN_IOCTL = _IOR('R', 0x07, struct rt_codec_cmd),
+ RT_SET_CODEC_3D_SPK_IOCTL = _IOW('R', 0x08, struct rt_codec_cmd),
+ RT_GET_CODEC_3D_SPK_IOCTL = _IOR('R', 0x08, struct rt_codec_cmd),
+ RT_SET_CODEC_MP3PLUS_IOCTL = _IOW('R', 0x09, struct rt_codec_cmd),
+ RT_GET_CODEC_MP3PLUS_IOCTL = _IOR('R', 0x09, struct rt_codec_cmd),
+ RT_SET_CODEC_3D_HEADPHONE_IOCTL = _IOW('R', 0x0a, struct rt_codec_cmd),
+ RT_GET_CODEC_3D_HEADPHONE_IOCTL = _IOR('R', 0x0a, struct rt_codec_cmd),
+ RT_SET_CODEC_BASS_BACK_IOCTL = _IOW('R', 0x0b, struct rt_codec_cmd),
+ RT_GET_CODEC_BASS_BACK_IOCTL = _IOR('R', 0x0b, struct rt_codec_cmd),
+ RT_SET_CODEC_DIPOLE_SPK_IOCTL = _IOW('R', 0x0c, struct rt_codec_cmd),
+ RT_GET_CODEC_DIPOLE_SPK_IOCTL = _IOR('R', 0x0c, struct rt_codec_cmd),
+ RT_SET_CODEC_DRC_AGC_ENABLE_IOCTL = _IOW('R', 0x0d, struct rt_codec_cmd),
+ RT_GET_CODEC_DRC_AGC_ENABLE_IOCTL = _IOR('R', 0x0d, struct rt_codec_cmd),
+ RT_SET_CODEC_DSP_MODE_IOCTL = _IOW('R', 0x0e, struct rt_codec_cmd),
+ RT_GET_CODEC_DSP_MODE_IOCTL = _IOR('R', 0x0e, struct rt_codec_cmd),
+ RT_SET_CODEC_WNR_ENABLE_IOCTL = _IOW('R', 0x0f, struct rt_codec_cmd),
+ RT_GET_CODEC_WNR_ENABLE_IOCTL = _IOR('R', 0x0f, struct rt_codec_cmd),
+ RT_SET_CODEC_DRC_AGC_PAR_IOCTL = _IOW('R', 0x10, struct rt_codec_cmd),
+ RT_GET_CODEC_DRC_AGC_PAR_IOCTL = _IOR('R', 0x10, struct rt_codec_cmd),
+ RT_SET_CODEC_DIGI_BOOST_GAIN_IOCTL = _IOW('R', 0x11, struct rt_codec_cmd),
+ RT_GET_CODEC_DIGI_BOOST_GAIN_IOCTL = _IOR('R', 0x11, struct rt_codec_cmd),
+ RT_SET_CODEC_NOISE_GATE_IOCTL = _IOW('R', 0x12, struct rt_codec_cmd),
+ RT_GET_CODEC_NOISE_GATE_IOCTL = _IOR('R', 0x12, struct rt_codec_cmd),
+ RT_SET_CODEC_DRC_AGC_COMP_IOCTL = _IOW('R', 0x13, struct rt_codec_cmd),
+ RT_GET_CODEC_DRC_AGC_COMP_IOCTL = _IOR('R', 0x13, struct rt_codec_cmd),
+ RT_GET_CODEC_ID = _IOR('R', 0x30, struct rt_codec_cmd),
+};
+
+int realtek_ce_init_hwdep(struct snd_soc_codec *codec);
+struct rt_codec_ops *rt_codec_get_ioctl_ops(void);
+
+#endif /* __RT56XX_IOCTL_H__ */
help
Say Y if you want to add support for SoC audio on rockchip
with the rt5621.
+config SND_RK29_SOC_RT5623
+ tristate "SoC I2S Audio support for rockchip - rt5623"
+ depends on SND_RK29_SOC
+ select SND_RK29_SOC_I2S
+ select SND_SOC_RT5623
+ help
+ Say Y if you want to add support for SoC audio on rockchip
+ with the rt5623.
config SND_RK29_SOC_RT5631
tristate "SoC I2S Audio support for rockchip - RT5631"
depends on SND_RK29_SOC
if your codec output hardware connect is spk from spkout, choose it
endchoice
+config SND_RK29_SOC_RT3261
+ tristate "SoC I2S Audio support for rockchip - RT3261"
+ depends on SND_RK29_SOC
+ select SND_RK29_SOC_I2S
+ select SND_SOC_RT3261
+ help
+ Say Y if you want to add support for SoC audio on rockchip
+ with the RT3261.
+
config SND_RK29_SOC_WM8994
tristate "SoC I2S Audio support for rockchip - WM8994"
depends on SND_RK29_SOC && MFD_WM8994
Say Y if you want to add support for SoC audio on rockchip
with the RK610(JETTA).
-if SND_RK29_SOC_WM8988 || SND_RK29_SOC_RK1000 || SND_RK29_SOC_WM8994 || SND_RK29_SOC_WM8900 || SND_RK29_SOC_RT5621 || SND_RK29_SOC_RT5631 || SND_RK29_SOC_RT5625 || SND_RK29_SOC_CS42L52 || SND_RK29_SOC_AIC3111 || SND_RK29_SOC_HDMI || SND_RK29_SOC_RK610 || SND_RK29_SOC_AIC3262
+if SND_RK29_SOC_WM8988 || SND_RK29_SOC_RK1000 || SND_RK29_SOC_WM8994 || SND_RK29_SOC_WM8900 || SND_RK29_SOC_RT5621 || SND_RK29_SOC_RT5631 || SND_RK29_SOC_RT5625 || SND_RK29_SOC_RT3261 || SND_RK29_SOC_CS42L52 || SND_RK29_SOC_AIC3111 || SND_RK29_SOC_HDMI || SND_RK29_SOC_RK610 || SND_RK29_SOC_AIC3262
choice
bool "Set i2s type"
default SND_RK29_CODEC_SOC_SLAVE
snd-soc-rt5621-objs := rk29_rt5621.o
snd-soc-rt5631-objs := rk29_rt5631.o
snd-soc-rt5625-objs := rk29_rt5625.o
+snd-soc-rt3261-objs := rk29_rt3261.o
snd-soc-cs42l52-objs := rk29_cs42l52.o
snd-soc-aic3111-objs := rk29_aic3111.o
snd-soc-wm8988-objs := rk29_wm8988.o
obj-$(CONFIG_SND_RK29_SOC_RT5621) += snd-soc-rt5621.o
obj-$(CONFIG_SND_RK29_SOC_RT5631) += snd-soc-rt5631.o
obj-$(CONFIG_SND_RK29_SOC_RT5625) += snd-soc-rt5625.o
+obj-$(CONFIG_SND_RK29_SOC_RT3261) += snd-soc-rt3261.o
obj-$(CONFIG_SND_RK29_SOC_RK1000) += snd-soc-rk1000.o
obj-$(CONFIG_SND_RK29_SOC_CS42L52) += snd-soc-cs42l52.o
obj-$(CONFIG_SND_RK29_SOC_AIC3111) += snd-soc-aic3111.o
--- /dev/null
+/*\r
+ * rk29_rt5625.c -- SoC audio for rockchip\r
+ *\r
+ * Driver for rockchip rt5625 audio\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License as published by the\r
+ * Free Software Foundation; either version 2 of the License, or (at your\r
+ * option) any later version.\r
+ *\r
+ *\r
+ */\r
+\r
+#include <linux/module.h>\r
+#include <linux/device.h>\r
+#include <sound/core.h>\r
+#include <sound/pcm.h>\r
+#include <sound/soc.h>\r
+#include <sound/soc-dapm.h>\r
+#include <asm/io.h>\r
+#include <mach/hardware.h>\r
+\r
+#include "../codecs/rt3261.h"\r
+#include "rk29_pcm.h"\r
+#include "rk29_i2s.h"\r
+\r
+#if 1\r
+#define DBG(x...) printk(KERN_INFO x)\r
+#else\r
+#define DBG(x...)\r
+#endif\r
+\r
+static int rk29_hw_params(struct snd_pcm_substream *substream,\r
+ struct snd_pcm_hw_params *params)\r
+{\r
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;\r
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;\r
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;\r
+ unsigned int pll_out = 0;\r
+ int ret;\r
+\r
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); \r
+ /*by Vincent Hsiung for EQ Vol Change*/\r
+ #define HW_PARAMS_FLAG_EQVOL_ON 0x21\r
+ #define HW_PARAMS_FLAG_EQVOL_OFF 0x22\r
+ if (codec_dai->driver->ops->hw_params && ((params->flags == HW_PARAMS_FLAG_EQVOL_ON) || (params->flags == HW_PARAMS_FLAG_EQVOL_OFF)))\r
+ {\r
+ ret = codec_dai->driver->ops->hw_params(substream, params, codec_dai); //by Vincent\r
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);\r
+ } else {\r
+ \r
+ /* set codec DAI configuration */\r
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE) \r
+\r
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |\r
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);\r
+ #endif \r
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER) \r
+\r
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |\r
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM ); \r
+ #endif\r
+ if (ret < 0)\r
+ return ret; \r
+\r
+ /* set cpu DAI configuration */\r
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE) \r
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |\r
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);\r
+ #endif \r
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER) \r
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |\r
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); \r
+ #endif \r
+ if (ret < 0)\r
+ return ret;\r
+ }\r
+\r
+ switch(params_rate(params)) {\r
+ case 8000:\r
+ case 16000:\r
+ case 24000:\r
+ case 32000:\r
+ case 48000:\r
+ pll_out = 12288000;\r
+ break;\r
+ case 11025:\r
+ case 22050:\r
+ case 44100:\r
+ pll_out = 11289600;\r
+ break;\r
+ default:\r
+ DBG("Enter:%s, %d, Error rate=%d\n", __FUNCTION__, __LINE__, params_rate(params));\r
+ return -EINVAL;\r
+ break;\r
+ }\r
+\r
+ DBG("Enter:%s, %d, rate=%d\n", __FUNCTION__, __LINE__, params_rate(params));\r
+\r
+ /*Set the system clk for codec*/\r
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN);\r
+ if (ret < 0)\r
+ {\r
+ DBG("rk29_hw_params_rt5625:failed to set the sysclk for codec side\n"); \r
+ return ret;\r
+ }\r
+\r
+ snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);\r
+ snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1);\r
+ snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3);\r
+\r
+ DBG("Enter:%s, %d, pll_out/4/params_rate(params) = %d \n", __FUNCTION__, __LINE__, (pll_out/4)/params_rate(params));\r
+ \r
+ return 0;\r
+}\r
+\r
+static int rt3261_voice_hw_params(struct snd_pcm_substream *substream,\r
+ struct snd_pcm_hw_params *params)\r
+{\r
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;\r
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;\r
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;\r
+ unsigned int pll_out = 0;\r
+ int ret;\r
+\r
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); \r
+ \r
+ /* set codec DAI configuration */\r
+ //#if defined (CONFIG_SND_CODEC_SOC_SLAVE) \r
+ DBG("Enter::%s----codec slave\n",__FUNCTION__);\r
+\r
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A |\r
+ SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS);\r
+ /*#endif\r
+ //#if defined (CONFIG_SND_CODEC_SOC_MASTER) \r
+ DBG("Enter::%s----codec master\n",__FUNCTION__);\r
+\r
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A |\r
+ SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM ); \r
+ #endif*/\r
+\r
+ switch(params_rate(params)) {\r
+ case 8000:\r
+ case 16000:\r
+ case 24000:\r
+ case 32000:\r
+ case 48000:\r
+ pll_out = 12288000;\r
+ break;\r
+ case 11025:\r
+ case 22050:\r
+ case 44100:\r
+ pll_out = 11289600;\r
+ break;\r
+ default:\r
+ DBG("Enter:%s, %d, Error rate=%d\n", __FUNCTION__, __LINE__, params_rate(params));\r
+ return -EINVAL;\r
+ break;\r
+ }\r
+\r
+ //snd_soc_dai_set_pll(codec_dai, RT5625_PLL_MCLK_TO_VSYSCLK, 0, pll_out, 24576000);???????\r
+\r
+ /*Set the system clk for codec*/\r
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, 24576000, SND_SOC_CLOCK_IN);\r
+\r
+ if (ret < 0) {\r
+ printk("rk29_hw_params_rt5625:failed to set the sysclk for codec side\n"); \r
+ return ret;\r
+ }\r
+\r
+ ret = snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);\r
+ \r
+ return 0;\r
+}\r
+\r
+static struct snd_soc_ops rk29_ops = {\r
+ .hw_params = rk29_hw_params,\r
+};\r
+\r
+static struct snd_soc_ops rt3261_voice_ops = {\r
+ .hw_params = rt3261_voice_hw_params,\r
+};\r
+\r
+static struct snd_soc_dai_link rk29_dai[] = {\r
+ {\r
+ .name = "RT3261 I2S1",\r
+ .stream_name = "RT3261 PCM",\r
+ .codec_name = "rt3261.0-001c",\r
+ .platform_name = "rockchip-audio",\r
+ .cpu_dai_name = "rk29_i2s.0",\r
+ .codec_dai_name = "rt3261-aif1",\r
+ .ops = &rk29_ops,\r
+ },\r
+ {\r
+ .name = "RT3261 I2S2",\r
+ .stream_name = "RT3261 PCM",\r
+ .codec_name = "rt3261.0-001c",\r
+ .platform_name = "rockchip-audio",\r
+ .cpu_dai_name = "rk29_i2s.0",\r
+ .codec_dai_name = "rt3261-aif2",\r
+ .ops = &rt3261_voice_ops,\r
+ },\r
+};\r
+\r
+static struct snd_soc_card snd_soc_card_rk29 = {\r
+ .name = "RK29_RT3261",\r
+ .dai_link = rk29_dai,\r
+ .num_links = 2,\r
+};\r
+\r
+static struct platform_device *rk29_snd_device;\r
+\r
+static int __init audio_card_init(void)\r
+{\r
+ int ret =0;\r
+\r
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);\r
+\r
+ rk29_snd_device = platform_device_alloc("soc-audio", -1);\r
+ if (!rk29_snd_device) {\r
+ printk("platform device allocation failed\n");\r
+ return -ENOMEM;\r
+ }\r
+\r
+ platform_set_drvdata(rk29_snd_device, &snd_soc_card_rk29);\r
+ ret = platform_device_add(rk29_snd_device);\r
+ if (ret) {\r
+ printk("platform device add failed\n");\r
+\r
+ platform_device_put(rk29_snd_device);\r
+ return ret;\r
+ }\r
+ \r
+ return ret;\r
+}\r
+\r
+static void __exit audio_card_exit(void)\r
+{\r
+ platform_device_unregister(rk29_snd_device);\r
+}\r
+\r
+module_init(audio_card_init);\r
+module_exit(audio_card_exit);\r
+/* Module information */\r
+MODULE_AUTHOR("rockchip");\r
+MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");\r
+MODULE_LICENSE("GPL");\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff