CONFIG_SPI_FPGA=y
CONFIG_SPI_FPGA_INIT=y
# CONFIG_SPI_FPGA_INIT_DEBUG is not set
-CONFIG_SPI_UART=y
+CONFIG_SPI_FPGA_UART=y
# CONFIG_SPI_UART_DEBUG is not set
+CONFIG_SPI_FPGA_GPIO=y
# CONFIG_SPI_GPIO_DEBUG is not set
-CONFIG_SPI_I2C=y
+CONFIG_SPI_FPGA_I2C=y
# CONFIG_SPI_I2C_DEBUG is not set
-CONFIG_SPI_DPRAM=y
+CONFIG_SPI_FPGA_DPRAM=y
# CONFIG_SPI_DPRAM_DEBUG is not set
#
};
struct pca9554_platform_data rk2818_pca9554_data={
- .gpio_base=GPIOS_EXPANDER_BASE,
+ .gpio_base=GPIO_EXPANDER_BASE,
.gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM,
.gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP,
.irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM,
};
#endif
+/*****************************************************************************************
+ * gsensor devices
+*****************************************************************************************/
+#define GS_IRQ_PIN RK2818_PIN_PE0
+struct rk2818_gs_platform_data rk2818_gs_platdata = {
+ .gsensor_irq_pin = GS_IRQ_PIN,
+};
/*****************************************************************************************
* i2c devices
* spi devices
* author: lhhrock-chips.com
*****************************************************************************************/
-#define SPI_CHIPSELECT_NUM 3
+#define SPI_CHIPSELECT_NUM 2
static int spi_io_init(void)
{
//cs0
rk2818_mux_api_set(GPIOB0_SPI0CSN1_MMC1PCA_NAME, IOMUXA_GPIO0_B0);
//clk
rk2818_mux_api_set(GPIOB_SPI0_MMC0_NAME, IOMUXA_SPI0);
- //cs2
- rk2818_mux_api_set(GPIOF5_APWM3_DPWM3_NAME,IOMUXB_GPIO1_B5);
return 0;
}
rk2818_mux_api_mode_resume(GPIOB4_SPI0CS0_MMC0D4_NAME);
rk2818_mux_api_mode_resume(GPIOB0_SPI0CSN1_MMC1PCA_NAME);
rk2818_mux_api_mode_resume(GPIOB_SPI0_MMC0_NAME);
- rk2818_mux_api_mode_resume(GPIOF5_APWM3_DPWM3_NAME);
return 0;
}
{
.name = "spi cs1",
.cs_gpio = RK2818_PIN_PB0,
- },
- {
- .name = "spi cs2",
- .cs_gpio = RK2818_PIN_PF5,
}
+
};
struct rk2818_spi_platform_data rk2818_spi_platdata = {
* xpt2046 touch panel
* author: dxjrock-chips.com
*****************************************************************************************/
-#define XPT2046_GPIO_INT RK2818_PIN_PE1
+#define XPT2046_GPIO_INT RK2818_PIN_PE3
#define DEBOUNCE_REPTIME 3
#if defined(CONFIG_TOUCHSCREEN_XPT2046_320X480_SPI)
.debounce_max = 7,
.debounce_rep = DEBOUNCE_REPTIME,
.debounce_tol = 20,
-#if defined(CONFIG_MACH_RAHO)
- .gpio_pendown = RK2818_PIN_PE1,
-#else
- .gpio_pendown = RK2818_PIN_PE3,
-#endif
+ .gpio_pendown = XPT2046_GPIO_INT,
+
.penirq_recheck_delay_usecs = 1,
};
#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
.debounce_max = 7,
.debounce_rep = DEBOUNCE_REPTIME,
.debounce_tol = 20,
-#if defined(CONFIG_MACH_RAHO)
- .gpio_pendown = RK2818_PIN_PE1,
-#else
- .gpio_pendown = RK2818_PIN_PE3,
-#endif
+ .gpio_pendown = XPT2046_GPIO_INT,
+
.penirq_recheck_delay_usecs = 1,
};
#endif
i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
ARRAY_SIZE(board_i2c1_devices));
#endif
-#ifdef CONFIG_SPI_I2C
+#ifdef CONFIG_SPI_FPGA_I2C
i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
ARRAY_SIZE(board_i2c2_devices));
i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
};
struct pca9554_platform_data rk2818_pca9554_data={
- .gpio_base=GPIOS_EXPANDER_BASE,
+ .gpio_base=GPIO_EXPANDER_BASE,
.gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM,
.gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP,
.irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM,
i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
ARRAY_SIZE(board_i2c1_devices));
#endif
-#ifdef CONFIG_SPI_I2C
+#ifdef CONFIG_SPI_FPGA_I2C
i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
ARRAY_SIZE(board_i2c2_devices));
i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
};
struct pca9554_platform_data rk2818_pca9554_data={
- .gpio_base=GPIOS_EXPANDER_BASE,
+ .gpio_base=GPIO_EXPANDER_BASE,
.gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM,
.gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP,
.irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM,
i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
ARRAY_SIZE(board_i2c1_devices));
#endif
-#ifdef CONFIG_SPI_I2C
+#ifdef CONFIG_SPI_FPGA_I2C
i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
ARRAY_SIZE(board_i2c2_devices));
i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
};
struct pca9554_platform_data rk2818_pca9554_data={
- .gpio_base=GPIOS_EXPANDER_BASE,
+ .gpio_base=GPIO_EXPANDER_BASE,
.gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM,
.gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP,
.irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM,
.debounce_max = 7,
.debounce_rep = DEBOUNCE_REPTIME,
.debounce_tol = 20,
-#if defined(CONFIG_MACH_RAHO)
- .gpio_pendown = RK2818_PIN_PE1,
-#else
- .gpio_pendown = RK2818_PIN_PE3,
-#endif
+ .gpio_pendown = XPT2046_GPIO_INT,
+
.penirq_recheck_delay_usecs = 1,
};
#elif defined(CONFIG_TOUCHSCREEN_XPT2046_CBN_SPI)
.debounce_max = 7,
.debounce_rep = DEBOUNCE_REPTIME,
.debounce_tol = 20,
-#if defined(CONFIG_MACH_RAHO)
- .gpio_pendown = RK2818_PIN_PE1,
-#else
- .gpio_pendown = RK2818_PIN_PE3,
-#endif
+ .gpio_pendown = XPT2046_GPIO_INT,
+
.penirq_recheck_delay_usecs = 1,
};
#endif
i2c_register_board_info(default_i2c1_data.bus_num, board_i2c1_devices,
ARRAY_SIZE(board_i2c1_devices));
#endif
-#ifdef CONFIG_SPI_I2C
+#ifdef CONFIG_SPI_FPGA_I2C
i2c_register_board_info(default_i2c2_data.bus_num, board_i2c2_devices,
ARRAY_SIZE(board_i2c2_devices));
i2c_register_board_info(default_i2c3_data.bus_num, board_i2c3_devices,
#define MAX_GPIO_BANKS 8//¶¨ÒåRK2818ÄÚ²¿GPIO×ܹ²Óм¸×飬ÏÖÔÚ¶¨Îª8×飬¼´GPIO0_A~ GPIO0_D£¬GPIO1_A~ GPIO1_D¡£
#define SPI_FPGA_EXPANDER_BASE (PIN_BASE+NUM_GROUP*MAX_GPIO_BANKS)
-#if defined (CONFIG_SPI_GPIO)
+#if defined (CONFIG_SPI_FPGA_GPIO)
#define GPIO_EXPANDER_BASE (PIN_BASE+NUM_GROUP*MAX_GPIO_BANKS+CONFIG_SPI_FPGA_GPIO_NUM)
#else
#define GPIO_EXPANDER_BASE (PIN_BASE+NUM_GROUP*MAX_GPIO_BANKS)
#define RK2818_PIN_PH7 (PIN_BASE + 7*NUM_GROUP + 7)
/***********************define extern gpio pin num******************************/
-#if defined(CONFIG_SPI_GPIO)
+#if defined(CONFIG_SPI_FPGA_GPIO)
#define FPGA_PIO0_00 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 0)
#define FPGA_PIO0_01 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 1)
#define FPGA_PIO0_02 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 2)
{
return (RK2818_PIN_PE0 + (irq - __gpio_to_irq(RK2818_PIN_PE0)));
}
-#if defined(CONFIG_SPI_GPIO)
+#if defined(CONFIG_SPI_FPGA_GPIO)
else if((irq - __gpio_to_irq(FPGA_PIO0_00)) <2*NUM_GROUP)
{
return (FPGA_PIO0_00 + (irq - __gpio_to_irq(FPGA_PIO0_00)));
struct work_struct fpga_irq_work; \r
struct timer_list fpga_timer;\r
/*spi2uart*/\r
-#ifdef CONFIG_SPI_UART\r
+#ifdef CONFIG_SPI_FPGA_UART\r
struct spi_uart uart;\r
#endif\r
/*spi2gpio*/\r
-#ifdef CONFIG_SPI_GPIO\r
+#ifdef CONFIG_SPI_FPGA_GPIO\r
struct spi_gpio gpio;\r
#endif\r
/*spi2i2c*/\r
-#ifdef CONFIG_SPI_I2C\r
+#ifdef CONFIG_SPI_FPGA_I2C\r
struct spi_i2c i2c;\r
#endif\r
/*spi2dpram*/\r
-#ifdef CONFIG_SPI_DPRAM\r
+#ifdef CONFIG_SPI_FPGA_DPRAM\r
struct spi_dpram dpram;\r
#endif\r
\r
extern unsigned int spi_in(struct spi_fpga_port *port, int reg, int type);\r
extern void spi_out(struct spi_fpga_port *port, int reg, int value, int type);\r
\r
-#if defined(CONFIG_SPI_UART)\r
+#if defined(CONFIG_SPI_FPGA_UART)\r
extern void spi_uart_handle_irq(struct spi_device *spi);\r
extern int spi_uart_register(struct spi_fpga_port *port);\r
extern int spi_uart_unregister(struct spi_fpga_port *port);\r
#endif\r
-#if defined(CONFIG_SPI_GPIO)\r
+#if defined(CONFIG_SPI_FPGA_GPIO)\r
extern int spi_gpio_int_sel(eSpiGpioPinNum_t PinNum,eSpiGpioTypeSel_t type);\r
extern int spi_gpio_set_pindirection(eSpiGpioPinNum_t PinNum,eSpiGpioPinDirection_t direction);\r
extern int spi_gpio_set_pinlevel(eSpiGpioPinNum_t PinNum, eSpiGpioPinLevel_t PinLevel);\r
extern int spi_gpio_register(struct spi_fpga_port *port);\r
extern int spi_gpio_unregister(struct spi_fpga_port *port);\r
#endif\r
-#if defined(CONFIG_SPI_I2C)\r
+#if defined(CONFIG_SPI_FPGA_I2C)\r
extern int spi_i2c_handle_irq(struct spi_fpga_port *port,unsigned char channel);\r
extern int spi_i2c_register(struct spi_fpga_port *port,int num);\r
extern int spi_i2c_unregister(struct spi_fpga_port *port);\r
#endif\r
-#if defined(CONFIG_SPI_DPRAM)\r
+#if defined(CONFIG_SPI_FPGA_DPRAM)\r
extern int spi_dpram_handle_irq(struct spi_device *spi);\r
extern int spi_dpram_register(struct spi_fpga_port *port);\r
extern int spi_dpram_unregister(struct spi_fpga_port *port);\r
endif\r
\r
if SPI_FPGA_INIT\r
-config SPI_UART\r
+config SPI_FPGA_UART\r
tristate "spi to uart support"\r
depends on SPI && SPIM_RK2818\r
help\r
fpga driver for spi to uart.\r
\r
-if SPI_UART\r
+if SPI_FPGA_UART\r
config SPI_UART_DEBUG\r
boolean "Debug support for spi to uart drivers"\r
depends on DEBUG_KERNEL\r
Say "yes" to enable debug messaging in spi to uart drivers.\r
endif\r
\r
-config SPI_GPIO\r
+config SPI_FPGA_GPIO\r
tristate "spi to gpio support"\r
depends on SPI && SPIM_RK2818\r
help\r
fpga driver for spi to gpio.\r
\r
-if SPI_GPIO\r
+if SPI_FPGA_GPIO\r
config SPI_GPIO_DEBUG\r
boolean "Debug support for spi to gpio drivers"\r
depends on DEBUG_KERNEL\r
Say "yes" to enable debug messaging in spi to gpio drivers.\r
endif\r
\r
-config SPI_I2C\r
+config SPI_FPGA_I2C\r
tristate "spi to i2c support"\r
depends on SPI && SPIM_RK2818\r
help\r
fpga driver for spi to i2c.\r
\r
-if SPI_I2C\r
+if SPI_FPGA_I2C\r
config SPI_I2C_DEBUG\r
boolean "Debug support for spi to i2c drivers"\r
depends on DEBUG_KERNEL\r
Say "yes" to enable debug messaging in spi to i2c drivers.\r
endif\r
\r
-config SPI_DPRAM\r
+config SPI_FPGA_DPRAM\r
tristate "spi to dpram support"\r
depends on SPI && SPIM_RK2818\r
help\r
fpga driver for spi to dpram.\r
\r
-if SPI_DPRAM\r
+if SPI_FPGA_DPRAM\r
config SPI_DPRAM_DEBUG\r
boolean "Debug support for spi to dpram drivers"\r
depends on DEBUG_KERNEL\r
\r
# fpga drivers\r
obj-$(CONFIG_SPI_FPGA_INIT) += spi_fpga_init.o\r
-obj-$(CONFIG_SPI_UART) += spi_uart.o\r
-obj-$(CONFIG_SPI_GPIO) += spi_gpio.o\r
-obj-$(CONFIG_SPI_I2C) += spi_i2c.o\r
-obj-$(CONFIG_SPI_DPRAM) += spi_dpram.o
\ No newline at end of file
+obj-$(CONFIG_SPI_FPGA_UART) += spi_uart.o\r
+obj-$(CONFIG_SPI_FPGA_GPIO) += spi_gpio.o\r
+obj-$(CONFIG_SPI_FPGA_I2C) += spi_i2c.o\r
+obj-$(CONFIG_SPI_FPGA_DPRAM) += spi_dpram.o
\ No newline at end of file
\r
switch(type)\r
{\r
-#if defined(CONFIG_SPI_UART)\r
+#if defined(CONFIG_SPI_FPGA_UART)\r
case SEL_UART:\r
index = port->uart.index;\r
reg = (((reg) | ICE_SEL_UART) | ICE_SEL_READ | ICE_SEL_UART_CH(index));\r
break;\r
#endif\r
\r
-#if defined(CONFIG_SPI_GPIO)\r
+#if defined(CONFIG_SPI_FPGA_GPIO)\r
case SEL_GPIO:\r
reg = (((reg) | ICE_SEL_GPIO) | ICE_SEL_READ );\r
tx_buf[0] = reg & 0xff;\r
break;\r
#endif\r
\r
-#if defined(CONFIG_SPI_I2C)\r
+#if defined(CONFIG_SPI_FPGA_I2C)\r
case SEL_I2C:\r
reg = (((reg) | ICE_SEL_I2C) | ICE_SEL_READ );\r
tx_buf[0] = reg & 0xff;\r
break;\r
#endif\r
\r
-#if defined(CONFIG_SPI_DPRAM)\r
+#if defined(CONFIG_SPI_FPGA_DPRAM)\r
case SEL_DPRAM:\r
reg = (((reg) | ICE_SEL_DPRAM) & ICE_SEL_DPRAM_READ );\r
tx_buf[0] = reg & 0xff;\r
//printk("index2=%d,",index);\r
switch(type)\r
{\r
-#if defined(CONFIG_SPI_UART)\r
+#if defined(CONFIG_SPI_FPGA_UART)\r
case SEL_UART:\r
index = port->uart.index;\r
reg = ((((reg) | ICE_SEL_UART) & ICE_SEL_WRITE) | ICE_SEL_UART_CH(index));\r
break;\r
#endif\r
\r
-#if defined(CONFIG_SPI_GPIO)\r
+#if defined(CONFIG_SPI_FPGA_GPIO)\r
case SEL_GPIO:\r
reg = (((reg) | ICE_SEL_GPIO) & ICE_SEL_WRITE );\r
tx_buf[0] = reg & 0xff;\r
break;\r
#endif\r
\r
-#if defined(CONFIG_SPI_I2C)\r
+#if defined(CONFIG_SPI_FPGA_I2C)\r
case SEL_I2C:\r
reg = (((reg) | ICE_SEL_I2C) & ICE_SEL_WRITE);\r
tx_buf[0] = reg & 0xff;\r
break;\r
#endif\r
\r
-#if defined(CONFIG_SPI_DPRAM)\r
+#if defined(CONFIG_SPI_FPGA_DPRAM)\r
case SEL_DPRAM:\r
reg = (((reg) | ICE_SEL_DPRAM) | ICE_SEL_DPRAM_WRITE );\r
tx_buf[0] = reg & 0xff;\r
ret = spi_in(port, ICE_SEL_READ_INT_TYPE, READ_TOP_INT);\r
if((ret | ICE_INT_TYPE_UART0) == ICE_INT_TYPE_UART0)\r
{\r
-#if defined(CONFIG_SPI_UART)\r
+#if defined(CONFIG_SPI_FPGA_UART)\r
DBG("%s:ICE_INT_TYPE_UART0 ret=0x%x\n",__FUNCTION__,ret);\r
port->uart.index = uart_ch;\r
spi_uart_handle_irq(spi);\r
}\r
else if((ret | ICE_INT_TYPE_GPIO) == ICE_INT_TYPE_GPIO)\r
{\r
-#if defined(CONFIG_SPI_GPIO)\r
+#if defined(CONFIG_SPI_FPGA_GPIO)\r
DBG("%s:ICE_INT_TYPE_GPIO ret=0x%x\n",__FUNCTION__,ret);\r
spi_gpio_handle_irq(spi);\r
#endif\r
}\r
else if((ret | ICE_INT_TYPE_I2C2) == ICE_INT_TYPE_I2C2)\r
{\r
-#if defined(CONFIG_SPI_I2C)\r
+#if defined(CONFIG_SPI_FPGA_I2C)\r
DBG("%s:ICE_INT_TYPE_I2C2 ret=0x%x\n",__FUNCTION__,ret);\r
spi_i2c_handle_irq(port,I2C_CH2);\r
#endif\r
}\r
else if((ret | ICE_INT_TYPE_I2C3) == ICE_INT_TYPE_I2C3)\r
{\r
-#if defined(CONFIG_SPI_I2C)\r
+#if defined(CONFIG_SPI_FPGA_I2C)\r
DBG("%s:ICE_INT_TYPE_I2C3 ret=0x%x\n",__FUNCTION__,ret);\r
spi_i2c_handle_irq(port,I2C_CH3);\r
#endif\r
}\r
else if((ret | ICE_INT_TYPE_DPRAM) == ICE_INT_TYPE_DPRAM)\r
{\r
-#if defined(CONFIG_SPI_DPRAM)\r
+#if defined(CONFIG_SPI_FPGA_DPRAM)\r
DBG("%s:ICE_INT_TYPE_DPRAM ret=0x%x\n",__FUNCTION__,ret);\r
spi_dpram_handle_irq(spi);\r
#endif\r
}\r
INIT_WORK(&port->fpga_irq_work, spi_fpga_irq_work_handler);\r
\r
-#if defined(CONFIG_SPI_UART)\r
+#if defined(CONFIG_SPI_FPGA_UART)\r
ret = spi_uart_register(port);\r
if(ret)\r
{\r
return ret;\r
}\r
#endif\r
-#if defined(CONFIG_SPI_GPIO)\r
+#if defined(CONFIG_SPI_FPGA_GPIO)\r
ret = spi_gpio_register(port);\r
if(ret)\r
{\r
return ret;\r
}\r
#endif\r
-#if defined(CONFIG_SPI_I2C)\r
+#if defined(CONFIG_SPI_FPGA_I2C)\r
\r
DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
spin_lock_init(&port->i2c.i2c_lock);\r
}\r
#endif\r
\r
-#if defined(CONFIG_SPI_DPRAM)\r
+#if defined(CONFIG_SPI_FPGA_DPRAM)\r
ret = spi_dpram_register(port);\r
if(ret)\r
{\r
DBG("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
pFpgaPort = port;\r
\r
-#if defined(CONFIG_SPI_GPIO)\r
+#if defined(CONFIG_SPI_FPGA_GPIO)\r
spi_gpio_init();\r
#endif\r
\r
{\r
if(((gpio_iir & (1 << i)) == 0) && ((state & (1 << i)) != 0))\r
{\r
- irq = i + GPIOS_EXPANDER_BASE;\r
+ irq = i + SPI_FPGA_EXPANDER_BASE;\r
desc = irq_to_desc(irq);\r
if(desc->action->handler)\r
desc->action->handler(irq,desc->action->dev_id);\r
#elif (FPGA_TYPE == ICE_CC196)\r
for(i=4;i<81;i++)\r
{\r
- gpio_direction_output(GPIOS_EXPANDER_BASE+i,TestGpioPinLevel);\r
+ gpio_direction_output(SPI_FPGA_EXPANDER_BASE+i,TestGpioPinLevel);\r
//ret = gpio_direction_input(GPIOS_EXPANDER_BASE+i);\r
//if (ret) {\r
// printk("%s:failed to set GPIO[%d] input\n",__FUNCTION__,GPIOS_EXPANDER_BASE+i);\r
//}\r
udelay(1);\r
- ret = gpio_get_value (GPIOS_EXPANDER_BASE+i);\r
+ ret = gpio_get_value (SPI_FPGA_EXPANDER_BASE+i);\r
if(ret != TestGpioPinLevel)\r
{\r
#if SPI_FPGA_TEST_DEBUG\r
/************³éÏóGPIO½Ó¿Úº¯ÊýʵÏÖ²¿·Ö************************/\r
static int spi_gpiolib_direction_input(struct gpio_chip *chip, unsigned offset)\r
{\r
- int pinnum = offset + chip->base -GPIOS_EXPANDER_BASE;\r
+ int pinnum = offset + chip->base -SPI_FPGA_EXPANDER_BASE;\r
DBG("%s:pinnum=%d\n",__FUNCTION__,pinnum);\r
if(pinnum < 16)\r
spi_gpio_int_sel(pinnum,SPI_GPIO0_IS_GPIO);\r
\r
static int spi_gpiolib_direction_output(struct gpio_chip *chip, unsigned offset, int val)\r
{\r
- int pinnum = offset + chip->base -GPIOS_EXPANDER_BASE;\r
+ int pinnum = offset + chip->base -SPI_FPGA_EXPANDER_BASE;\r
if(pinnum < 16)\r
spi_gpio_int_sel(pinnum,SPI_GPIO0_IS_GPIO);\r
DBG("%s:pinnum=%d\n",__FUNCTION__,pinnum);\r
\r
static int spi_gpiolib_get_pinlevel(struct gpio_chip *chip, unsigned int offset)\r
{\r
- int pinnum = offset + chip->base -GPIOS_EXPANDER_BASE;\r
+ int pinnum = offset + chip->base -SPI_FPGA_EXPANDER_BASE;\r
DBG("%s:pinnum=%d\n",__FUNCTION__,pinnum);\r
return spi_gpio_get_pinlevel(pinnum);\r
}\r
\r
static void spi_gpiolib_set_pinlevel(struct gpio_chip *chip, unsigned int offset, int val)\r
{\r
- int pinnum = offset + chip->base -GPIOS_EXPANDER_BASE;\r
+ int pinnum = offset + chip->base -SPI_FPGA_EXPANDER_BASE;\r
DBG("%s:pinnum=%d\n",__FUNCTION__,pinnum);\r
if(GPIO_HIGH == val)\r
spi_gpio_set_pinlevel(pinnum,SPI_GPIO_HIGH);\r
}\r
\r
static struct fpga_gpio_chip spi_gpio_chip[] = {\r
- SPI_GPIO_CHIP_DEF("PIO0", GPIOS_EXPANDER_BASE+0*NUM_GROUP*2, NUM_GROUP<<1),\r
- SPI_GPIO_CHIP_DEF("PIO1", GPIOS_EXPANDER_BASE+1*NUM_GROUP*2, NUM_GROUP<<1),\r
- SPI_GPIO_CHIP_DEF("PIO2", GPIOS_EXPANDER_BASE+2*NUM_GROUP*2, NUM_GROUP<<1),\r
- SPI_GPIO_CHIP_DEF("PIO3", GPIOS_EXPANDER_BASE+3*NUM_GROUP*2, NUM_GROUP<<1),\r
- SPI_GPIO_CHIP_DEF("PIO4", GPIOS_EXPANDER_BASE+4*NUM_GROUP*2, NUM_GROUP<<1),\r
- SPI_GPIO_CHIP_DEF("PIO5", GPIOS_EXPANDER_BASE+5*NUM_GROUP*2, NUM_GROUP<<1),\r
+ SPI_GPIO_CHIP_DEF("PIO0", SPI_FPGA_EXPANDER_BASE+0*NUM_GROUP*2, NUM_GROUP<<1),\r
+ SPI_GPIO_CHIP_DEF("PIO1", SPI_FPGA_EXPANDER_BASE+1*NUM_GROUP*2, NUM_GROUP<<1),\r
+ SPI_GPIO_CHIP_DEF("PIO2", SPI_FPGA_EXPANDER_BASE+2*NUM_GROUP*2, NUM_GROUP<<1),\r
+ SPI_GPIO_CHIP_DEF("PIO3", SPI_FPGA_EXPANDER_BASE+3*NUM_GROUP*2, NUM_GROUP<<1),\r
+ SPI_GPIO_CHIP_DEF("PIO4", SPI_FPGA_EXPANDER_BASE+4*NUM_GROUP*2, NUM_GROUP<<1),\r
+ SPI_GPIO_CHIP_DEF("PIO5", SPI_FPGA_EXPANDER_BASE+5*NUM_GROUP*2, NUM_GROUP<<1),\r
};\r
\r
\r
\r
static void _spi_gpio_irq_enable(unsigned irq)\r
{\r
- int gpio = irq_to_gpio(irq) - GPIOS_EXPANDER_BASE;\r
+ int gpio = irq_to_gpio(irq) - SPI_FPGA_EXPANDER_BASE;\r
DBG("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio);\r
if(gpio < 16)\r
spi_gpio_int_sel(gpio,SPI_GPIO0_IS_INT);\r
\r
static void _spi_gpio_irq_disable(unsigned irq)\r
{\r
- int gpio = irq_to_gpio(irq) - GPIOS_EXPANDER_BASE;\r
+ int gpio = irq_to_gpio(irq) - SPI_FPGA_EXPANDER_BASE;\r
DBG("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio);\r
if(gpio < 16)\r
spi_gpio_int_sel(gpio,SPI_GPIO0_IS_INT);\r
\r
static int _spi_gpio_irq_set_type(unsigned int irq, unsigned int type)\r
{\r
- int gpio = irq_to_gpio(irq) - GPIOS_EXPANDER_BASE;\r
+ int gpio = irq_to_gpio(irq) - SPI_FPGA_EXPANDER_BASE;\r
int int_type = 0;\r
DBG("%s:line=%d,irq=%d,type=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,type,gpio);\r
if(gpio < 16)\r
\r
for(i=0;i<81;i++)\r
{\r
- gpio = GPIOS_EXPANDER_BASE+i;\r
+ gpio = SPI_FPGA_EXPANDER_BASE+i;\r
ret = gpio_request(gpio, NULL);\r
if (ret) {\r
printk("%s:failed to request GPIO[%d]\n",__FUNCTION__,gpio);\r
\r
for(i=0;i<4;i++)\r
{\r
- gpio = GPIOS_EXPANDER_BASE+i;\r
+ gpio = SPI_FPGA_EXPANDER_BASE+i;\r
irq = gpio_to_irq(gpio);\r
printk("%s:line=%d,irq=%d,gpio=%d\n",__FUNCTION__,__LINE__,irq,gpio);\r
switch(i)\r
set_irq_flags(pin+j, IRQF_VALID);\r
}\r
\r
- printk("%s: %d gpio irqs in %d banks\n", __FUNCTION__, pin+j-GPIOS_EXPANDER_BASE, spi_gpio_banks);\r
+ printk("%s: %d gpio irqs in %d banks\n", __FUNCTION__, pin+j-SPI_FPGA_EXPANDER_BASE, spi_gpio_banks);\r
\r
spi_gpio_test_gpio_irq_init();\r
\r