rk29: timer: disable write buffer

sometime, rk29_timer_set_next_event may take long time (10ms ~ 40ms)
to finish because of write buffer.

diff --git a/arch/arm/mach-rk29/timer.c b/arch/arm/mach-rk29/timer.c
index c390129d268f41083621333ba7640f951e994835..a0d0596832c47cce6d39bc29e2a097b54f9f8637 100644 (file)
--- a/arch/arm/mach-rk29/timer.c
+++ b/arch/arm/mach-rk29/timer.c
@@ -35,13 +35,15 @@
 #define TIMER_ENABLE                   3
 #define TIMER_ENABLE_FREE_RUNNING      5
 
+#define timer_writel(v, addr)          do { writel(v, addr); readl(addr); } while (0)
+
 #if 1  /* by default, use periph sync timer */
 
-#define RK_TIMER_ENABLE(n)             writel(TIMER_ENABLE, RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_CONTROL_REG)
-#define RK_TIMER_ENABLE_FREE_RUNNING(n)        writel(TIMER_ENABLE_FREE_RUNNING, RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_CONTROL_REG)
-#define RK_TIMER_DISABLE(n)            writel(TIMER_DISABLE, RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_CONTROL_REG)
+#define RK_TIMER_ENABLE(n)             timer_writel(TIMER_ENABLE, RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_CONTROL_REG)
+#define RK_TIMER_ENABLE_FREE_RUNNING(n)        timer_writel(TIMER_ENABLE_FREE_RUNNING, RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_CONTROL_REG)
+#define RK_TIMER_DISABLE(n)            timer_writel(TIMER_DISABLE, RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_CONTROL_REG)
 
-#define RK_TIMER_SETCOUNT(n, count)    writel(count, RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_LOAD_COUNT)
+#define RK_TIMER_SETCOUNT(n, count)    timer_writel(count, RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_LOAD_COUNT)
 #define RK_TIMER_GETCOUNT(n)           readl(RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_LOAD_COUNT)
 
 #define RK_TIMER_READVALUE(n)          readl(RK29_TIMER2_BASE + 0x4000 * (n - 2) + TIMER_CUR_VALUE)
@@ -59,11 +61,11 @@
 
 #else
 
-#define RK_TIMER_ENABLE(n)             writel(TIMER_ENABLE, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
-#define RK_TIMER_ENABLE_FREE_RUNNING(n)        writel(TIMER_ENABLE_FREE_RUNNING, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
-#define RK_TIMER_DISABLE(n)            writel(TIMER_DISABLE, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
+#define RK_TIMER_ENABLE(n)             timer_writel(TIMER_ENABLE, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
+#define RK_TIMER_ENABLE_FREE_RUNNING(n)        timer_writel(TIMER_ENABLE_FREE_RUNNING, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
+#define RK_TIMER_DISABLE(n)            timer_writel(TIMER_DISABLE, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
 
-#define RK_TIMER_SETCOUNT(n, count)    writel(count, RK29_TIMER0_BASE + 0x2000 * n + TIMER_LOAD_COUNT)
+#define RK_TIMER_SETCOUNT(n, count)    timer_writel(count, RK29_TIMER0_BASE + 0x2000 * n + TIMER_LOAD_COUNT)
 #define RK_TIMER_GETCOUNT(n)           readl(RK29_TIMER0_BASE + 0x2000 * n + TIMER_LOAD_COUNT)
 
 #define RK_TIMER_READVALUE(n)          readl(RK29_TIMER0_BASE + 0x2000 * n + TIMER_CUR_VALUE)