clk: vt8500: Fix device clock divisor calculations
authorTony Prisk <linux@prisktech.co.nz>
Thu, 27 Dec 2012 00:14:30 +0000 (13:14 +1300)
committerMike Turquette <mturquette@linaro.org>
Wed, 16 Jan 2013 00:16:24 +0000 (16:16 -0800)
When calculating device clock divisor values in set_rate and
round_rate, we do a simple integer divide. If parent_rate / rate
has a fraction, this is dropped which results in the device clock
being set too high.

This patch corrects the problem by adding 1 to the calculated
divisor if the division would have had a decimal result.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/clk-vt8500.c

index 0cb26bef427dd98af0ca54c64448bb7cf7ea3fdf..3306c2b1906c46e85f391e6150890453f4692d81 100644 (file)
@@ -123,6 +123,10 @@ static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
        struct clk_device *cdev = to_clk_device(hw);
        u32 divisor = *prate / rate;
 
+       /* If prate / rate would be decimal, incr the divisor */
+       if (rate * divisor < *prate)
+               divisor++;
+
        /*
         * If this is a request for SDMMC we have to adjust the divisor
         * when >31 to use the fixed predivisor
@@ -141,6 +145,10 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
        u32 divisor = parent_rate / rate;
        unsigned long flags = 0;
 
+       /* If prate / rate would be decimal, incr the divisor */
+       if (rate * divisor < *prate)
+               divisor++;
+
        if (divisor == cdev->div_mask + 1)
                divisor = 0;