ARM: tegra: clock: Don't restore PLLP registers

The PLLP registers are now being restored by the low-level resume code,
and the CPU may be running off PLLP, so don't touch them during clock
resume.

Change-Id: Ida248a929c8b59f2e51f43dbbef1cd792ef68737
Signed-off-by: Colin Cross <ccross@android.com>

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 4a9e3e0b7f2e90d865d51be0b9c6a004e4a09a7b..253de093a8ef89ef490e273d78c221957019c284 100644 (file)
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2053,7 +2053,7 @@ void __init tegra2_init_clocks(void)
 
 #ifdef CONFIG_PM
 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
-                          PERIPH_CLK_SOURCE_NUM + 19];
+                          PERIPH_CLK_SOURCE_NUM + 15];
 
 void tegra_clk_suspend(void)
 {
@@ -2061,16 +2061,12 @@ void tegra_clk_suspend(void)
        u32 *ctx = clk_rst_suspend;
 
        *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
-       *ctx++ = clk_readl(tegra_pll_p.reg + PLL_BASE);
-       *ctx++ = clk_readl(tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
        *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
        *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
        *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
        *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
 
        *ctx++ = clk_readl(tegra_pll_m_out1.reg);
-       *ctx++ = clk_readl(tegra_pll_p_out1.reg);
-       *ctx++ = clk_readl(tegra_pll_p_out3.reg);
        *ctx++ = clk_readl(tegra_pll_a_out0.reg);
        *ctx++ = clk_readl(tegra_pll_c_out1.reg);
 
@@ -2110,8 +2106,6 @@ void tegra_clk_resume(void)
        val |= *ctx++;
        clk_writel(val, OSC_CTRL);
 
-       clk_writel(*ctx++, tegra_pll_p.reg + PLL_BASE);
-       clk_writel(*ctx++, tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
        clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
        clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
        clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
@@ -2119,8 +2113,6 @@ void tegra_clk_resume(void)
        udelay(300);
 
        clk_writel(*ctx++, tegra_pll_m_out1.reg);
-       clk_writel(*ctx++, tegra_pll_p_out1.reg);
-       clk_writel(*ctx++, tegra_pll_p_out3.reg);
        clk_writel(*ctx++, tegra_pll_a_out0.reg);
        clk_writel(*ctx++, tegra_pll_c_out1.reg);