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camera: rockchip: camsys driver 0.0x21.5
authordalon.zhang <dalon.zhang@rock-chips.com>
Wed, 24 Aug 2016 11:10:49 +0000 (19:10 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Mon, 29 Aug 2016 03:36:54 +0000 (11:36 +0800)
Change-Id: I4855b2e31fff158ae4690781ccc8e0ab0a20273c
Signed-off-by: dalon.zhang <dalon.zhang@rock-chips.com>
drivers/media/video/rk_camsys/camsys_internal.h patch | blob | history
drivers/media/video/rk_camsys/camsys_soc_rk3368.c patch | blob | history
drivers/media/video/rk_camsys/camsys_soc_rk3399.c patch | blob | history

diff --git a/drivers/media/video/rk_camsys/camsys_internal.h b/drivers/media/video/rk_camsys/camsys_internal.h
index 6d0c891b19331925c329c87df2cb0afd1e363f45..37fc222ef488ce385eeec85d4be35200da00a1ce 100644 (file)
--- a/drivers/media/video/rk_camsys/camsys_internal.h
+++ b/drivers/media/video/rk_camsys/camsys_internal.h
@@ -138,8 +138,11 @@
                1) some modifications.
 *v0.0x21.4:
                1) modify for rk3399.
+*v0.0x21.5:
+               1) modify for mipiphy hsfreqrange.
+
 */
-#define CAMSYS_DRIVER_VERSION                   KERNEL_VERSION(0, 0x21, 4)
+#define CAMSYS_DRIVER_VERSION                   KERNEL_VERSION(0, 0x21, 5)
 
 #define CAMSYS_PLATFORM_DRV_NAME                "RockChip-CamSys"
 #define CAMSYS_PLATFORM_MARVIN_NAME             "Platform_MarvinDev"
diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3368.c b/drivers/media/video/rk_camsys/camsys_soc_rk3368.c
index d7c05d3d5573d5cfa5c7bab37af9c6487b1f37e8..89fc8ef86604c962dc3e9e49dbb74eeb716cb3a8 100644 (file)
--- a/drivers/media/video/rk_camsys/camsys_soc_rk3368.c
+++ b/drivers/media/video/rk_camsys/camsys_soc_rk3368.c
@@ -10,21 +10,45 @@ struct mipiphy_hsfreqrange_s {
 };
 
 static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
-       {80, 110, 0x00},
-       {110, 150, 0x01},
-       {150, 200, 0x02},
-       {200, 250, 0x03},
-       {250, 300, 0x04},
-       {300, 400, 0x05},
-       {400, 500, 0x06},
-       {500, 600, 0x07},
-       {600, 700, 0x08},
-       {700, 800, 0x09},
-       {800, 1000, 0x10},
-       {1000, 1200, 0x11},
-       {1200, 1400, 0x12},
-       {1400, 1600, 0x13},
-       {1600, 1800, 0x14}
+       {80, 90, 0x00},
+       {90, 100, 0x10},
+       {100, 110, 0x20},
+       {110, 130, 0x01},
+       {130, 140, 0x11},
+       {140, 150, 0x21},
+       {150, 170, 0x02},
+       {170, 180, 0x12},
+       {180, 200, 0x22},
+       {200, 220, 0x03},
+       {220, 240, 0x13},
+       {240, 250, 0x23},
+       {250, 270, 0x04},
+       {270, 300, 0x14},
+       {300, 330, 0x05},
+       {330, 360, 0x15},
+       {360, 400, 0x25},
+       {400, 450, 0x06},
+       {450, 500, 0x16},
+       {500, 550, 0x07},
+       {550, 600, 0x17},
+       {600, 650, 0x08},
+       {650, 700, 0x18},
+       {700, 750, 0x09},
+       {750, 800, 0x19},
+       {800, 850, 0x29},
+       {850, 900, 0x39},
+       {900, 950, 0x0a},
+       {950, 1000, 0x1a},
+       {1000, 1050, 0x2a},
+       {1100, 1150, 0x3a},
+       {1150, 1200, 0x0b},
+       {1200, 1250, 0x1b},
+       {1250, 1300, 0x2b},
+       {1300, 1350, 0x0c},
+       {1350, 1400, 0x1c},
+       {1400, 1450, 0x2c},
+       {1450, 1500, 0x3c}
+
 };
 
 #if 0
diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3399.c b/drivers/media/video/rk_camsys/camsys_soc_rk3399.c
index a0d0a936d46de6990b2ab2c7be7872c8c836d7c3..b7d001c48e9de7116a75ecf2f7d2c4381406de75 100644 (file)
--- a/drivers/media/video/rk_camsys/camsys_soc_rk3399.c
+++ b/drivers/media/video/rk_camsys/camsys_soc_rk3399.c
@@ -9,29 +9,62 @@ struct mipiphy_hsfreqrange_s {
 };
 
 static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
-       {80, 110, 0x00},
-       {110, 150, 0x01},
-       {150, 200, 0x02},
-       {200, 250, 0x03},
-       {250, 300, 0x04},
-       {300, 400, 0x05},
-       {400, 500, 0x06},
-       {500, 600, 0x07},
-       {600, 700, 0x08},
-       {700, 800, 0x09},
-       {800, 1000, 0x10},
-       {1000, 1200, 0x11},
-       {1200, 1400, 0x12},
-       {1400, 1600, 0x13},
-       {1600, 1800, 0x14}
+       {80, 90, 0x00},
+       {90, 100, 0x10},
+       {100, 110, 0x20},
+       {110, 130, 0x01},
+       {130, 140, 0x11},
+       {140, 150, 0x21},
+       {150, 170, 0x02},
+       {170, 180, 0x12},
+       {180, 200, 0x22},
+       {200, 220, 0x03},
+       {220, 240, 0x13},
+       {240, 250, 0x23},
+       {250, 270, 0x04},
+       {270, 300, 0x14},
+       {300, 330, 0x05},
+       {330, 360, 0x15},
+       {360, 400, 0x25},
+       {400, 450, 0x06},
+       {450, 500, 0x16},
+       {500, 550, 0x07},
+       {550, 600, 0x17},
+       {600, 650, 0x08},
+       {650, 700, 0x18},
+       {700, 750, 0x09},
+       {750, 800, 0x19},
+       {800, 850, 0x29},
+       {850, 900, 0x39},
+       {900, 950, 0x0a},
+       {950, 1000, 0x1a},
+       {1000, 1050, 0x2a},
+       {1100, 1150, 0x3a},
+       {1150, 1200, 0x0b},
+       {1200, 1250, 0x1b},
+       {1250, 1300, 0x2b},
+       {1300, 1350, 0x0c},
+       {1350, 1400, 0x1c},
+       {1400, 1450, 0x2c},
+       {1450, 1500, 0x3c}
 };
 
-#if 0
-static int camsys_rk3399_mipiphy0_rd_reg(unsigned char addr)
+static char camsys_rk3399_mipiphy0_rd_reg(camsys_mipiphy_soc_para_t *para, unsigned char addr)
 {
-    return read_grf_reg(0x0e2a4);
+       /*TESTCLK=1*/
+       write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
+                               (1 << DPHY_RX0_TESTCLK_BIT));
+       /*TESTEN =1,TESTDIN=addr*/
+       write_grf_reg(GRF_SOC_CON25_OFFSET,
+                               ((addr << DPHY_RX0_TESTDIN_BIT) |
+                               DPHY_RX0_TESTDIN_MASK |
+                               (1 << DPHY_RX0_TESTEN_BIT) |
+                               DPHY_RX0_TESTEN_MASK));
+       /*TESTCLK=0*/
+       write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
+
+    return read_grf_reg(GRF_SOC_STATUS1)&0xff;
 }
-#endif
 
 static int camsys_rk3399_mipiphy0_wr_reg
 (camsys_mipiphy_soc_para_t *para, unsigned char addr, unsigned char data)
@@ -62,7 +95,7 @@ static int camsys_rk3399_mipiphy0_wr_reg
        return 0;
 }
 
-static int camsys_rk3399_mipiphy1_wr_reg
+static char camsys_rk3399_mipiphy1_wr_reg
 (unsigned long dsiphy_virt, unsigned char addr, unsigned char data)
 {
        /*TESTEN =1,TESTDIN=addr*/
@@ -76,12 +109,15 @@ static int camsys_rk3399_mipiphy1_wr_reg
 
        return 0;
 }
-/*
-static int camsys_rk3399_mipiphy1_rd_reg
-(unsigned long dsiphy_virt,unsigned char addr)
+
+static int camsys_rk3399_mipiphy1_rd_reg(unsigned long dsiphy_virt, unsigned char addr)
 {
-    return (read_dsihost_reg(((DSIHOST_PHY_TEST_CTRL1)&0xff00))>>8);
-}*/
+       /*TESTEN =1,TESTDIN=addr*/
+       write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
+       /*TESTCLK=0*/
+       write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
+    return (read_dsihost_reg(DSIHOST_PHY_TEST_CTRL1)>>8);
+}
 
 static int camsys_rk3399_mipihpy_cfg
 (camsys_mipiphy_soc_para_t *para)
@@ -93,6 +129,9 @@ static int camsys_rk3399_mipihpy_cfg
        unsigned long csiphy_virt;
        unsigned long dsiphy_virt;
        unsigned long vir_base = 0;
+       unsigned char settle_bypass = 0;
+       unsigned char settle_en = 0;
+       unsigned char manu_hsfreqrange = 0x04;
 
        phy_index = para->phy->phy_index;
        if (para->camsys_dev->mipiphy[phy_index].reg != NULL) {
@@ -189,24 +228,21 @@ static int camsys_rk3399_mipihpy_cfg
                        write_grf_reg(GRF_SOC_CON25_OFFSET,
                                DPHY_RX0_TESTCLR_MASK);
                        udelay(100);
-
                        /*set clock lane*/
                        camsys_rk3399_mipiphy0_wr_reg
-                               (para, 0x34, 0x15);
-
-                       if (para->phy->data_en_bit >= 0x00) {
-                               camsys_rk3399_mipiphy0_wr_reg
-                                       (para, 0x44, hsfreqrange);
-                       }
-                       if (para->phy->data_en_bit >= 0x01)
-                               camsys_rk3399_mipiphy0_wr_reg
-                               (para, 0x54, hsfreqrange);
-                       if (para->phy->data_en_bit >= 0x04) {
-                               camsys_rk3399_mipiphy0_wr_reg
-                                       (para, 0x84, hsfreqrange);
-                               camsys_rk3399_mipiphy0_wr_reg
-                                       (para, 0x94, hsfreqrange);
-                       }
+                               (para, 0x34, settle_bypass);
+                       /*HS hsfreqrange & lane 0  settle bypass*/
+                       camsys_rk3399_mipiphy0_wr_reg
+                               (para, 0x44, hsfreqrange | settle_bypass);
+                       camsys_rk3399_mipiphy0_wr_reg
+                               (para, 0x54, settle_bypass);
+                       camsys_rk3399_mipiphy0_wr_reg
+                               (para, 0x84, settle_bypass);
+                       camsys_rk3399_mipiphy0_wr_reg
+                               (para, 0x94, settle_bypass);
+                       camsys_rk3399_mipiphy0_wr_reg
+                               (para, 0x75, (settle_en << 7) | manu_hsfreqrange);
+                       camsys_rk3399_mipiphy0_rd_reg(para, 0x75);
                        /*Normal operation*/
                        camsys_rk3399_mipiphy0_wr_reg(para, 0x0, -1);
                        write_grf_reg(GRF_SOC_CON25_OFFSET,
@@ -243,7 +279,6 @@ static int camsys_rk3399_mipihpy_cfg
                        (0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
                        DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
 
-
                /*      set lane num*/
                write_grf_reg(GRF_SOC_CON23_OFFSET,
                        DPHY_TX1RX1_ENABLE_MASK |
@@ -261,15 +296,13 @@ static int camsys_rk3399_mipihpy_cfg
                        (0x0 << DPHY_TX1RX1_TURNREQUEST_BIT));
                /*phy1 start*/
                {
-                       int res_val = 0;
+                       char res_val = 0;
                        res_val = read_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ);
                        res_val &= 0xfffffffe;
                        /*SHUTDOWNZ=0*/
                        write_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ, res_val);
-
                        vir_base = (unsigned long)ioremap(0xff910000, 0x10000);
                        /*__raw_writel(0x60000, (void*)(0x1c00+vir_base));*/
-
                        res_val = 0;
                        res_val = read_dsihost_reg(DSIHOST_DPHY_RSTZ);
                        res_val &= 0xfffffffd;
@@ -283,24 +316,21 @@ static int camsys_rk3399_mipihpy_cfg
                        /*TESTCLR=0 TESTCLK=1*/
                        write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
                        udelay(100);
-
                        /*set clock lane*/
                        camsys_rk3399_mipiphy1_wr_reg
-                               (dsiphy_virt, 0x34, 0x15);
-                       if (para->phy->data_en_bit >= 0x00)
-                               camsys_rk3399_mipiphy1_wr_reg
-                               (dsiphy_virt, 0x44, hsfreqrange);
-                       if (para->phy->data_en_bit >= 0x01)
-                               camsys_rk3399_mipiphy1_wr_reg
-                               (dsiphy_virt, 0x54, hsfreqrange);
-                       if (para->phy->data_en_bit >= 0x04) {
-                               camsys_rk3399_mipiphy1_wr_reg
-                                       (dsiphy_virt, 0x84, hsfreqrange);
-                               camsys_rk3399_mipiphy1_wr_reg
-                                       (dsiphy_virt, 0x94, hsfreqrange);
-                       }
-
-                       /*camsys_rk3399_mipiphy1_rd_reg(dsiphy_virt,0x0);*/
+                               (dsiphy_virt, 0x34, settle_bypass);
+                       /*HS hsfreqrange & lane 0  settle bypass*/
+                       camsys_rk3399_mipiphy1_wr_reg
+                               (dsiphy_virt, 0x44, hsfreqrange | settle_bypass);
+                       camsys_rk3399_mipiphy1_wr_reg
+                               (dsiphy_virt, 0x54, settle_bypass);
+                       camsys_rk3399_mipiphy1_wr_reg
+                               (dsiphy_virt, 0x84, settle_bypass);
+                       camsys_rk3399_mipiphy1_wr_reg
+                               (dsiphy_virt, 0x94, settle_bypass);
+                       camsys_rk3399_mipiphy1_wr_reg
+                               (dsiphy_virt, 0x75, (settle_en << 7) | manu_hsfreqrange);
+                       camsys_rk3399_mipiphy1_rd_reg(dsiphy_virt, 0x75);
                        /*TESTCLK=1*/
                        write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
                        /*TESTEN =0*/
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