The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.

rdar://10418009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144213 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 23629e76675fa056a7893e0dc7bd5fd18f9742a9..44c88aa7fd7ea8319bcbe18bd38f674c14264e04 100644 (file)
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -846,9 +846,17 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
   switch (VT.getSimpleVT().SimpleTy) {
     default:
       assert(false && "Unhandled load/store type!");
+    case MVT::i16:
+      if (isThumb2)
+        // Integer loads/stores handle 12-bit offsets.
+        needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
+      else
+        // ARM i16 integer loads/stores handle +/-imm8 offsets.
+        if (Addr.Offset > 255 || Addr.Offset < -255)
+          needsLowering = true;
+      break;
     case MVT::i1:
     case MVT::i8:
-    case MVT::i16:
     case MVT::i32:
       // Integer loads/stores handle 12-bit offsets.
       needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
@@ -932,14 +940,14 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
   switch (VT.getSimpleVT().SimpleTy) {
     // This is mostly going to be Neon/vector support.
     default: return false;
-    case MVT::i16:
-      Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
-      RC = ARM::GPRRegisterClass;
-      break;
     case MVT::i8:
       Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12;
       RC = ARM::GPRRegisterClass;
       break;
+    case MVT::i16:
+      Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
+      RC = ARM::GPRRegisterClass;
+      break;
     case MVT::i32:
       Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
       RC = ARM::GPRRegisterClass;