add:ddr reg dump,resume code data align

diff --git a/arch/arm/mach-rockchip/pm-rk3288.c b/arch/arm/mach-rockchip/pm-rk3288.c
index 86fe55a9eca2fd8e4de63b7d58b45a394491e1c7..850cf0edf6842c4b0a1c260d258d71f59126b40e 100755 (executable)
--- a/arch/arm/mach-rockchip/pm-rk3288.c
+++ b/arch/arm/mach-rockchip/pm-rk3288.c
@@ -1269,14 +1269,22 @@ static void rkpm_save_setting_resume_first(void)
 
 static void rkpm_save_setting(u32 ctrbits)
 {
-        rk3288_powermode=rkpm_slp_mode_set(ctrbits);
-        if(rk3288_powermode&BIT(pmu_pwr_mode_en))
-       {
-                sram_code_data_save(rk3288_powermode);   
-                rkpm_peri_save(rk3288_powermode);                
-        }
-        else
-             return ;
+
+#if 0
+    rkpm_ddr_regs_dump(RK_DDR_VIRT,0,0x3fc);
+    rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE,0,0x294);
+
+    rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE+RK3288_DDR_PUBL_SIZE,0,0x3fc);
+    rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE*2+RK3288_DDR_PUBL_SIZE,0,0x294);
+#endif
+    rk3288_powermode=rkpm_slp_mode_set(ctrbits);
+    if(rk3288_powermode&BIT(pmu_pwr_mode_en))
+    {
+            sram_code_data_save(rk3288_powermode);   
+            rkpm_peri_save(rk3288_powermode);                
+    }
+    else
+         return ;
 
 }
 static void rkpm_save_setting_resume(void)

diff --git a/arch/arm/mach-rockchip/sleep.S b/arch/arm/mach-rockchip/sleep.S
index 1839b5d598b9d266961e9fa46efe34bfbe8ba8a4..40e3c8c463035d63766373bac0195bd6c9b3782a 100755 (executable)
--- a/arch/arm/mach-rockchip/sleep.S
+++ b/arch/arm/mach-rockchip/sleep.S
@@ -18,7 +18,8 @@ ldmfd sp!, { r3 - r12, pc }
 
 ENDPROC(rkpm_slp_cpu_while_tst)
 
-
+.data
+.align
 //65 A   48 0  97 a
 ENTRY(rkpm_slp_cpu_resume)
 9:     mov r1,r1