stack and rpcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25369 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 8a77c14f13ff402a9c37555c19d5a274b63b8724..e74dfd5865a1a6e4b73bc95d4ab78202e7f78adc 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -163,37 +163,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
   case ISD::TAILCALL:
   case ISD::CALL: return SelectCALL(Op);
 
-  case ISD::DYNAMIC_STACKALLOC: {
-    if (!isa<ConstantSDNode>(N->getOperand(2)) ||
-        cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
-      std::cerr << "Cannot allocate stack object with greater alignment than"
-                << " the stack alignment yet!";
-      abort();
-    }
-
-    SDOperand Chain = Select(N->getOperand(0));
-    SDOperand Amt   = Select(N->getOperand(1));
-    SDOperand Reg = CurDAG->getRegister(Alpha::R30, MVT::i64);
-    SDOperand Val = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
-    Chain = Val.getValue(1);
-    
-    // Subtract the amount (guaranteed to be a multiple of the stack alignment)
-    // from the stack pointer, giving us the result pointer.
-    SDOperand Result = CurDAG->getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt);
-    
-    // Copy this result back into R30.
-    Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
-    
-    // Copy this result back out of R30 to make sure we're not using the stack
-    // space without decrementing the stack pointer.
-    Result = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
-  
-    // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
-    CodeGenMap[Op.getValue(0)] = Result;
-    CodeGenMap[Op.getValue(1)] = Result.getValue(1);
-    return SDOperand(Result.Val, Op.ResNo);
-  }
-
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
@@ -218,6 +187,11 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
     return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
   }
 
+  case ISD::READCYCLECOUNTER: {
+    SDOperand Chain = Select(N->getOperand(0)); //Select chain
+    return CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
+  }
+
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
     SDOperand InFlag;

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 67e49c54f2d4998aee6aa3a3aaece2d24e8eab55..7429416a2a9a59d2c157dca0041924387bcc9eca 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -112,7 +112,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
   // Not implemented yet.
   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 
   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
-  
+  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
   // We want to legalize GlobalAddress and ConstantPool and
   // ExternalSymbols nodes into the appropriate instructions to
   // materialize the address.
@@ -120,6 +121,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
   setOperationAction(ISD::ConstantPool,   MVT::i64, Custom);
   setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
 
+  setStackPointerRegisterToSaveRestore(Alpha::R30);
+
   addLegalFPImmediate(+0.0); //F31
   addLegalFPImmediate(-0.0); //-F31
 

diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td
index 922482393205903da2073b6546292a3bf1854111..88a405c509b86488fcfc3886a1887a3208d62164 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrFormats.td
+++ b/lib/Target/Alpha/AlphaInstrFormats.td
@@ -65,12 +65,11 @@ class MFormAlt<bits<6> opcode, string asmstr>
   let Inst{15-0} = disp;
 }
 class MfcForm<bits<6> opcode, bits<16> fc, string asmstr> 
-        : InstAlpha<opcode, (ops GPRC:$RA, GPRC:$RB), asmstr> {
+        : InstAlpha<opcode, (ops GPRC:$RA), asmstr> {
   bits<5> Ra;
-  bits<5> Rb;
 
   let Inst{25-21} = Ra;
-  let Inst{20-16} = Rb;
+  let Inst{20-16} = 0;
   let Inst{15-0} = fc;
 }