Strange as it may sound, we'll not use LDD/STD to store longs. For reasons of

representational consistency, we want to address the halves of each 64-bit value
separately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14356 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/InstSelectSimple.cpp b/lib/Target/Sparc/InstSelectSimple.cpp
index e25a73c6ae28bd0f1d90c4315fa6a8b6505702c2..bef5002160e55ce4c7cb2c28038b653b966adc64 100644 (file)
--- a/lib/Target/Sparc/InstSelectSimple.cpp
+++ b/lib/Target/Sparc/InstSelectSimple.cpp
@@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
     BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
     return;
    case cLong:
-    BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
     return;
    default:
     std::cerr << "Load instruction not handled: " << I;
@@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
     BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
     return;
    case cLong:
-    BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
     return;
    default:
     std::cerr << "Store instruction not handled: " << I;

diff --git a/lib/Target/Sparc/SparcV8ISelSimple.cpp b/lib/Target/Sparc/SparcV8ISelSimple.cpp
index e25a73c6ae28bd0f1d90c4315fa6a8b6505702c2..bef5002160e55ce4c7cb2c28038b653b966adc64 100644 (file)
--- a/lib/Target/Sparc/SparcV8ISelSimple.cpp
+++ b/lib/Target/Sparc/SparcV8ISelSimple.cpp
@@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
     BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
     return;
    case cLong:
-    BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
     return;
    default:
     std::cerr << "Load instruction not handled: " << I;
@@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
     BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
     return;
    case cLong:
-    BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
     return;
    default:
     std::cerr << "Store instruction not handled: " << I;

diff --git a/lib/Target/SparcV8/InstSelectSimple.cpp b/lib/Target/SparcV8/InstSelectSimple.cpp
index e25a73c6ae28bd0f1d90c4315fa6a8b6505702c2..bef5002160e55ce4c7cb2c28038b653b966adc64 100644 (file)
--- a/lib/Target/SparcV8/InstSelectSimple.cpp
+++ b/lib/Target/SparcV8/InstSelectSimple.cpp
@@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
     BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
     return;
    case cLong:
-    BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
     return;
    default:
     std::cerr << "Load instruction not handled: " << I;
@@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
     BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
     return;
    case cLong:
-    BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
     return;
    default:
     std::cerr << "Store instruction not handled: " << I;

diff --git a/lib/Target/SparcV8/SparcV8ISelSimple.cpp b/lib/Target/SparcV8/SparcV8ISelSimple.cpp
index e25a73c6ae28bd0f1d90c4315fa6a8b6505702c2..bef5002160e55ce4c7cb2c28038b653b966adc64 100644 (file)
--- a/lib/Target/SparcV8/SparcV8ISelSimple.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelSimple.cpp
@@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
     BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
     return;
    case cLong:
-    BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
     return;
    default:
     std::cerr << "Load instruction not handled: " << I;
@@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
     BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
     return;
    case cLong:
-    BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
     return;
    default:
     std::cerr << "Store instruction not handled: " << I;