1. due to cx2072x only support playback samplerate 48K
2. set_clk_rate called from codec side will make the clock
tree correct, otherwise mclk will be closed from
i2s_runtime_suspend unexpected
Change-Id: Iaa748bb27635e21f7c2d2997823228cdf7308fe8
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
if (PTR_ERR(cx2072x->mclk_clock) == -EPROBE_DEFER)
return -EPROBE_DEFER;
+ ret = clk_set_rate(cx2072x->mclk_clock, CX2072X_RATES_MCLK);
+ if (ret) {
+ dev_err(codec->dev, "clk_set_rate is fail!\n");
+ return ret;
+ }
+
ret = clk_prepare_enable(cx2072x->mclk_clock);
- if (ret)
+ if (ret) {
dev_err(codec->dev, "clk_prepare_enable is fail!\n");
+ return ret;
+ }
dev_dbg(codec->dev, "codec version: 4.4.20\n");
regmap_read(cx2072x->regmap, CX2072X_VENDOR_ID, &ven_id);
#define CX2072X_RATES SNDRV_PCM_RATE_8000_192000
#define CX2072X_RATES_DSP SNDRV_PCM_RATE_48000
+#define CX2072X_RATES_MCLK 12288000
#define CX2072X_REG_MAX 0x8a3c
#define AUDDRV_VERSION(major0, major1, minor, build) \