arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.

Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.

There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]

[1] https://lkml.org/lkml/2014/7/30/514

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
[dinguyen] cleaned-up commit header and remove version history.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644 (file)
index 0000000..d0ce01d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+The EDAC accesses a range of registers in the SDRAM controller.
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- altr,sdr-syscon : phandle of the sdr module
+- interrupts : Should contain the SDRAM ECC IRQ in the
+       appropriate format for the IRQ controller.
+
+Example:
+       sdramedac {
+               compatible = "altr,sdram-edac";
+               altr,sdr-syscon = <&sdr>;
+               interrupts = <0 39 4>;
+       };

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4d77ad690ed54d93bb863ded9f8b088b47f9ae9f..45fce2cf6fede0a11ce2aca2d1de31aa70147ecf 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -607,6 +607,17 @@
                        };
                };
 
+               sdr: sdr@ffc25000 {
+                       compatible = "syscon";
+                       reg = <0xffc25000 0x1000>;
+               };
+
+               sdramedac {
+                       compatible = "altr,sdram-edac";
+                       altr,sdr-syscon = <&sdr>;
+                       interrupts = <0 39 4>;
+               };
+
                L2: l2-cache@fffef000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xfffef000 0x1000>;