pdma0: pdma@ff600000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff600000 0x0 0x4000>;
+ clocks = <&clk_gates12 11>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
+
};
pdma1: pdma@ff250000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff250000 0x0 0x4000>;
+ clocks = <&clk_gates19 3>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
int ret;
do {
- //ret = amba_get_enable_pclk(pcdev);
- //if (ret)
- // break;
+ ret = amba_get_enable_pclk(pcdev);
+ if (ret)
+ break;
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_set_suspended(dev);
pm_runtime_put_noidle(dev);
- //amba_put_disable_pclk(pcdev);
+ amba_put_disable_pclk(pcdev);
} while (0);
return ret;
goto err_release;
}
-// ret = amba_get_enable_pclk(dev);
+ ret = amba_get_enable_pclk(dev);
ret = 0;
if (ret == 0) {
u32 pid, cid;
cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) <<
(i * 8);
-// amba_put_disable_pclk(dev);
+ amba_put_disable_pclk(dev);
if (cid == AMBA_CID || cid == CORESIGHT_CID)
dev->periphid = pid;