fix store issue and an FP conversion (segfault) issue

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20066 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index a173fa3793d0d64d0576ee8ed5a89daa73163265..ccc10d3fdeaea031ac9c98c6b3416575a31d31bd 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1164,14 +1164,16 @@ unsigned ISel::SelectExpr(SDOperand N) {
 
 void ISel::Select(SDOperand N) {
   unsigned Tmp1, Tmp2, Opc;
+  unsigned opcode = N.getOpcode();
 
   // FIXME: Disable for our current expansion model!
   if (/*!N->hasOneUse() &&*/ !ExprMap.insert(std::make_pair(N, notIn)).second)
     return;  // Already selected.
 
   SDNode *Node = N.Val;
+  
 
-  switch (N.getOpcode()) {
+  switch (opcode) {
 
   default:
     Node->dump(); std::cerr << "\n";
@@ -1267,16 +1269,24 @@ void ISel::Select(SDOperand N) {
       Select(Chain);
 
       Tmp1 = SelectExpr(Value); //value
-      switch(Value.getValueType()) {
-      default: assert(0 && "unknown Type in store");
-      case MVT::i64: Opc = Alpha::STQ; break;
-      case MVT::f64: Opc = Alpha::STT; break;
-      case MVT::f32: Opc = Alpha::STS; break;
-      case MVT::i1: //FIXME: DAG does not promote this load
-      case MVT::i8: Opc = Alpha::STB; break;
-      case MVT::i16: Opc = Alpha::STW; break;
-      case MVT::i32: Opc = Alpha::STL; break;
+
+      if (opcode == ISD::STORE) {
+        switch(Value.getValueType()) {
+        default: assert(0 && "unknown Type in store");
+        case MVT::i64: Opc = Alpha::STQ; break;
+        case MVT::f64: Opc = Alpha::STT; break;
+        case MVT::f32: Opc = Alpha::STS; break;
+        }
+      } else { //ISD::TRUNCSTORE
+        switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+        default: assert(0 && "unknown Type in store");
+        case MVT::i1: //FIXME: DAG does not promote this load
+        case MVT::i8: Opc = Alpha::STB; break;
+        case MVT::i16: Opc = Alpha::STW; break;
+        case MVT::i32: Opc = Alpha::STL; break;
+        }
       }
+
       if (Address.getOpcode() == ISD::GlobalAddress)
         {
           AlphaLowering.restoreGP(BB);

diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index 6c0c3440e7b69dc7709d0afb065dab359c7fa83e..d5062eabee134c00e6ee719a2d291becd704b86f 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -358,7 +358,7 @@ def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //In
 //CVTQL F-P 17.030 Convert quadword to longword
 def CVTQS : FPForm<0x16, 0x0BC,  (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating
 def CVTQT : FPForm<0x16, 0x0BE,  (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating
-def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtst $RA,$RC">; //Convert S_floating to T_floating
+def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtsts $RA,$RC">; //Convert S_floating to T_floating (use completion, may not have function code for that set right)
 def CVTTQ : FPForm<0x16, 0x0AF,  (ops FPRC:$RC, FPRC:$RA), "cvttq $RA,$RC">; //Convert T_floating to quadword
 def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts $RA,$RC">; //Convert T_floating to S_floating