backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980
91177308-0d34-0410-b5e6-
96231b3b80d8
SrcReg = MI->getOperand(0).getReg();
CmpValue = MI->getOperand(1).getImm();
return true;
- case ARM::TSTri: {
- if (&*MI->getParent()->begin() == MI)
- return false;
- const MachineInstr *AND = llvm::prior(MI);
- if (AND->getOpcode() != ARM::ANDri)
- return false;
- if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
- MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
- SrcReg = AND->getOperand(0).getReg();
- CmpValue = 0;
- return true;
- }
- }
- break;
}
return false;
switch (MI->getOpcode()) {
default: break;
case ARM::ADDri:
- case ARM::ANDri:
- case ARM::t2ANDri:
case ARM::SUBri:
case ARM::t2ADDri:
case ARM::t2SUBri:
%tmp2 = load i8** %scevgep5
%0 = ptrtoint i8* %tmp2 to i32
-; CHECK: ands r12, r12, #3
+; CHECK: and lr, r12, #3
+; CHECK-NEXT: tst r12, #3
; CHECK-NEXT: beq LBB0_4
; T2: movs r5, #3