hasExtraDefRegAllocReq = 1 in
def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
- IndexModeUpd, LdStMulFrm, IIC_Br,
+ IndexModeUpd, LdStMulFrm, IIC_iLoadmBr,
"ldm${addr:submode}${p}\t$addr!, $dsts",
"$addr.addr = $wb", []>;
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in
def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
- reglist:$dsts, variable_ops), IIC_Br,
+ reglist:$dsts, variable_ops),
+ IIC_iLoadmBr,
"ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
"$addr.addr = $wb", []> {
let Inst{31-27} = 0b11101;
def IIC_iLoadru : InstrItinClass;
def IIC_iLoadsiu : InstrItinClass;
def IIC_iLoadm : InstrItinClass;
+def IIC_iLoadmBr : InstrItinClass;
def IIC_iStorei : InstrItinClass;
def IIC_iStorer : InstrItinClass;
def IIC_iStoresi : InstrItinClass;
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_LdSt0]>]>,
+ //
+ // Load multiple plus branch
+ InstrItinData<IIC_iLoadmBr , [InstrStage<2, [A8_Issue], 0>,
+ InstrStage<2, [A8_Pipe0], 0>,
+ InstrStage<2, [A8_Pipe1]>,
+ InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrStage<1, [A8_LdSt0]>,
+ InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
+
// Integer store pipeline
//
// use A8_Issue to enforce the 1 load/store per cycle limit
InstrItinData<IIC_iLoadm , [InstrStage<1, [A9_Pipe1]>,
InstrStage<1, [A9_LSPipe]>]>,
+ //
+ // Load multiple plus branch
+ InstrItinData<IIC_iLoadmBr , [InstrStage<1, [A9_Pipe1]>,
+ InstrStage<1, [A9_LSPipe]>,
+ InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
+
// Integer store pipeline
///
// Immediate offset