add dts node clock name for hevc vpu and iep

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 9029bed215ca4c0412d7ed9bd5632f3674f76f2d..1891c5fe5de3a22fa9f9552f161c3fb63e241bf4 100755 (executable)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -607,8 +607,8 @@
                reg = <0xff9a0000 0x800>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "irq_enc", "irq_dec";
-               /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
-               clock-names = "aclk_vcodec", "hclk_vcodec"; */
+               
+               clock-names = "aclk_vcodec", "hclk_vcodec";
                name = "vpu_service";
                status = "disabled";
        };
@@ -618,8 +618,8 @@
                reg = <0xff9c0000 0x800>;
                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "irq_dec";
-               /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
-               clock-names = "aclk_vcodec", "hclk_vcodec";*/
+
+                clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
                name = "hevc_service";
                status = "disabled";
        };
@@ -628,8 +628,8 @@
                compatible = "rockchip,iep";
                reg = <0xff900000 0x800>;
                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-               /*clocks = <&clk_gate3 9>, <&clk_gate3 10>;
-               clock_names = "aclk_iep", "hclk_iep";*/
+               
+               clock_names = "aclk_iep", "hclk_iep";
                status = "disabled";
        };
 

diff --git a/arch/arm/mach-rockchip/vcodec_service.c b/arch/arm/mach-rockchip/vcodec_service.c
index 24567074c3b52169fa087eec2c3d9f0f1ade131c..e2983a0b2745423203700ce2804e5f785aea961b 100755 (executable)
--- a/arch/arm/mach-rockchip/vcodec_service.c
+++ b/arch/arm/mach-rockchip/vcodec_service.c
@@ -39,6 +39,10 @@
 #include <asm/cacheflush.h>\r
 #include <asm/uaccess.h>\r
 \r
+#if defined(CONFIG_ION_ROCKCHIP)\r
+#include <linux/rockchip_ion.h>\r
+#endif\r
+\r
 #ifdef CONFIG_DEBUG_FS\r
 #include <linux/debugfs.h>\r
 #endif\r
@@ -50,7 +54,7 @@
 #include "vcodec_service.h"\r
 \r
 #define HEVC_TEST_ENABLE    0\r
-#define HEVC_SIM_ENABLE                0\r
+#define HEVC_SIM_ENABLE                1\r
 \r
 typedef enum {\r
        VPU_DEC_ID_9190         = 0x6731,\r
@@ -261,6 +265,7 @@ typedef struct vpu_service_info {
     struct dentry   *debugfs_file_regs;\r
 \r
     u32 irq_status;\r
+       struct ion_client * ion_client;\r
 \r
     struct delayed_work simulate_work;\r
 } vpu_service_info;\r
@@ -499,6 +504,68 @@ static inline bool reg_check_interlace(vpu_reg *reg)
        return (type > 0);\r
 }\r
 \r
+#if defined(CONFIG_VCODEC_MMU)\r
+static u8 table_vpu_dec[] = {\r
+       12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
+};\r
+\r
+static u8 table_vpu_enc[] = {\r
+       5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
+};\r
+\r
+static u8 table_hevc_dec[1] = {\r
+\r
+};\r
+\r
+static int reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
+{\r
+       VPU_HW_ID hw_id;\r
+       int i;\r
+\r
+       hw_id = pservice->hw_info->hw_id;\r
+\r
+    if (hw_id == HEVC_ID) {\r
+\r
+    } else {\r
+        if (reg->type == VPU_DEC) {\r
+            for (i=0; i<sizeof(table_vpu_dec); i++) {\r
+                               int usr_fd;\r
+                               struct ion_handle *hdl;\r
+                               ion_phys_addr_t phy_addr;\r
+                               size_t len;\r
+                               int offset;\r
+\r
+#if 0\r
+                               if (copy_from_user(&usr_fd, &reg->reg[table_vpu_dec[i]], sizeof(usr_fd)))\r
+                                       return -EFAULT;\r
+#else\r
+                               usr_fd = reg->reg[table_vpu_dec[i]] & 0xFF;\r
+                               offset = reg->reg[table_vpu_dec[i]] >> 8;\r
+#endif\r
+                if (usr_fd != 0) {\r
+\r
+                                       hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
+                    if (IS_ERR(hdl)) {\r
+                                               pr_err("import dma-buf from fd %d failed\n", usr_fd);\r
+                                               return ERR_PTR(hdl);\r
+                    }\r
+\r
+                                       ion_phys(pservice->ion_client, hdl, &phy_addr, &len);\r
+\r
+                                       reg->reg[table_vpu_dec[i]] = phy_addr + offset;\r
+\r
+                                       ion_free(pservice->ion_client, hdl);\r
+                }\r
+            }\r
+        } else if (reg->type == VPU_ENC) {\r
+\r
+        }\r
+       }\r
+\r
+       return 0;\r
+}\r
+#endif\r
+\r
 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 {\r
        vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
@@ -525,6 +592,14 @@ static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session
                return NULL;\r
        }\r
 \r
+#if defined(CONFIG_VCODEC_MMU)\r
+    if (0 > reg_address_translate(pservice, reg)) {\r
+               pr_err("error: translate reg address failed\n");\r
+               kfree(reg);\r
+               return NULL;\r
+    }\r
+#endif\r
+\r
        mutex_lock(&pservice->lock);\r
        list_add_tail(&reg->status_link, &pservice->waiting);\r
        list_add_tail(&reg->session_link, &session->waiting);\r
@@ -972,7 +1047,7 @@ static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
        volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
        u32 enc_id = *tmp;\r
 \r
-#if 0\r
+#if HEVC_SIM_ENABLE\r
     /// temporary, hevc driver test.\r
     if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
         p->hw_info = &vpu_hw_set[2];\r
@@ -1091,6 +1166,9 @@ static void simulate_start(struct vpu_service_info *pservice)
 #if HEVC_TEST_ENABLE\r
 static int hevc_test_case0(vpu_service_info *pservice);\r
 #endif\r
+#if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
+extern struct ion_client *rockchip_ion_client_create(const char * name);\r
+#endif\r
 static int vcodec_probe(struct platform_device *pdev)\r
 {\r
     int ret = 0;\r
@@ -1238,6 +1316,16 @@ static int vcodec_probe(struct platform_device *pdev)
     vpu_service_power_off(pservice);\r
     pr_info("init success\n");\r
 \r
+#if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
+       pservice->ion_client = rockchip_ion_client_create("vpu");\r
+       if (IS_ERR(pservice->ion_client)) {\r
+               dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
+               return PTR_ERR(pservice->ion_client);\r
+       } else {\r
+               dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
+       }\r
+#endif\r
+\r
 #if HEVC_SIM_ENABLE\r
     if (pservice->hw_info->hw_id == HEVC_ID) {\r
         simulate_init(pservice);\r
@@ -1317,7 +1405,7 @@ static int vcodec_remove(struct platform_device *pdev)
 \r
 #if defined(CONFIG_OF)\r
 static const struct of_device_id vcodec_service_dt_ids[] = {\r
-       //{.compatible = "vpu_service",},\r
+       {.compatible = "vpu_service",},\r
        {.compatible = "rockchip,hevc_service",},\r
     {},\r
 };\r