} else if (devpriv->res_owner[i] != owner) {
for (b = 1, i = 0; claimed != 0; b <<= 1, i++) {
if ((claimed & b) != 0) {
- devpriv->res_owner[i]
- = OWNER_NONE;
+ devpriv->res_owner[i] =
+ OWNER_NONE;
claimed &= ~b;
}
}
gainshift = chan & ~1;
adccon |= PCI230_ADC_IM_SE;
}
- devpriv->adcg = (devpriv->adcg & ~(3 << gainshift))
- | (pci230_ai_gain[range] << gainshift);
+ devpriv->adcg = (devpriv->adcg & ~(3 << gainshift)) |
+ (pci230_ai_gain[range] << gainshift);
if (devpriv->ai_bipolar)
adccon |= PCI230_ADC_IR_BIP;
else
* The only flags allowed are CR_EDGE and CR_INVERT.
* The CR_EDGE flag is ignored.
*/
- if ((cmd->scan_begin_arg
- & (CR_FLAGS_MASK & ~(CR_EDGE | CR_INVERT))) != 0) {
+ if ((cmd->scan_begin_arg &
+ (CR_FLAGS_MASK & ~(CR_EDGE | CR_INVERT))) != 0) {
cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
CR_FLAGS_MASK &
~(CR_EDGE | CR_INVERT));
* disable FIFO.
*/
devpriv->daccon &= PCI230_DAC_OR_MASK;
- outw(devpriv->daccon | PCI230P2_DAC_FIFO_RESET
- | PCI230P2_DAC_FIFO_UNDERRUN_CLEAR,
+ outw(devpriv->daccon | PCI230P2_DAC_FIFO_RESET |
+ PCI230P2_DAC_FIFO_UNDERRUN_CLEAR,
dev->iobase + PCI230_DACCON);
}
/* Release resources. */
* to FIFO. Set FIFO interrupt trigger level
* to 'empty'.
*/
- devpriv->daccon = (devpriv->daccon
- &
- ~PCI230P2_DAC_INT_FIFO_MASK)
- | PCI230P2_DAC_INT_FIFO_EMPTY;
+ devpriv->daccon =
+ (devpriv->daccon &
+ ~PCI230P2_DAC_INT_FIFO_MASK) |
+ PCI230P2_DAC_INT_FIFO_EMPTY;
outw(devpriv->daccon,
dev->iobase + PCI230_DACCON);
}
events |= COMEDI_CB_OVERFLOW | COMEDI_CB_ERROR;
}
}
- if ((events & (COMEDI_CB_EOA | COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW))
- != 0) {
+ if ((events &
+ (COMEDI_CB_EOA | COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW)) != 0) {
/* Stopping AO due to completion or error. */
pci230_ao_stop(dev, s);
running = 0;
scantrig = PCI230P2_DAC_TRIG_NONE;
break;
}
- devpriv->daccon = (devpriv->daccon
- & ~PCI230P2_DAC_TRIG_MASK) |
+ devpriv->daccon =
+ (devpriv->daccon & ~PCI230P2_DAC_TRIG_MASK) |
scantrig;
outw(devpriv->daccon, dev->iobase + PCI230_DACCON);
}
*
* N.B. DAC FIFO interrupts are currently disabled.
*/
- daccon |= PCI230P2_DAC_FIFO_EN | PCI230P2_DAC_FIFO_RESET
- | PCI230P2_DAC_FIFO_UNDERRUN_CLEAR
- | PCI230P2_DAC_TRIG_NONE | PCI230P2_DAC_INT_FIFO_NHALF;
+ daccon |= PCI230P2_DAC_FIFO_EN | PCI230P2_DAC_FIFO_RESET |
+ PCI230P2_DAC_FIFO_UNDERRUN_CLEAR |
+ PCI230P2_DAC_TRIG_NONE | PCI230P2_DAC_INT_FIFO_NHALF;
}
/* Set DACCON. */
outw(daccon, dev->iobase + PCI230_DACCON);
/* Preserve most of DACCON apart from write-only, transient bits. */
- devpriv->daccon = daccon
- & ~(PCI230P2_DAC_FIFO_RESET | PCI230P2_DAC_FIFO_UNDERRUN_CLEAR);
+ devpriv->daccon = daccon & ~(PCI230P2_DAC_FIFO_RESET |
+ PCI230P2_DAC_FIFO_UNDERRUN_CLEAR);
if (cmd->scan_begin_src == TRIG_TIMER) {
/*
* The only flags allowed are CR_INVERT and CR_EDGE.
* CR_EDGE is required.
*/
- if ((cmd->convert_arg & (CR_FLAGS_MASK & ~CR_INVERT))
- != CR_EDGE) {
+ if ((cmd->convert_arg &
+ (CR_FLAGS_MASK & ~CR_INVERT)) != CR_EDGE) {
/* Set CR_EDGE, preserve CR_INVERT. */
cmd->convert_arg = COMBINE(cmd->start_arg,
(CR_EDGE | 0),
scanlen >= PCI230_ADC_FIFOLEVEL_HALFFULL) {
wake = PCI230_ADC_FIFOLEVEL_HALFFULL;
} else {
- wake = (devpriv->ai_scan_count * scanlen)
- - devpriv->ai_scan_pos;
+ wake = (devpriv->ai_scan_count * scanlen) -
+ devpriv->ai_scan_pos;
}
}
if (wake >= PCI230_ADC_FIFOLEVEL_HALFFULL) {
* Reset FIFO, disable FIFO and set start conversion source to none.
* Keep se/diff and bip/uni settings.
*/
- devpriv->adccon = (devpriv->adccon & (PCI230_ADC_IR_MASK
- | PCI230_ADC_IM_MASK)) |
+ devpriv->adccon =
+ (devpriv->adccon & (PCI230_ADC_IR_MASK | PCI230_ADC_IM_MASK)) |
PCI230_ADC_TRIG_NONE;
outw(devpriv->adccon | PCI230_ADC_FIFO_RESET,
dev->iobase + PCI230_ADCCON);
conv = PCI230_ADC_TRIG_Z2CT2;
break;
}
- devpriv->adccon = (devpriv->adccon & ~PCI230_ADC_TRIG_MASK)
- | conv;
+ devpriv->adccon =
+ (devpriv->adccon & ~PCI230_ADC_TRIG_MASK) | conv;
outw(devpriv->adccon, dev->iobase + PCI230_ADCCON);
if (cmd->convert_src == TRIG_INT)
async->inttrig = pci230_ai_inttrig_convert;
* gated on to start counting.
*/
zgat = GAT_CONFIG(1, GAT_VCC);
- outb(zgat, devpriv->iobase1
- + PCI230_ZGAT_SCE);
+ outb(zgat, devpriv->iobase1 +
+ PCI230_ZGAT_SCE);
break;
case TRIG_INT:
async->inttrig =
(scanlen > PCI230_ADC_FIFOLEVEL_HALFFULL)) {
todo = PCI230_ADC_FIFOLEVEL_HALFFULL;
} else {
- todo = (devpriv->ai_scan_count * scanlen)
- - devpriv->ai_scan_pos;
+ todo = (devpriv->ai_scan_count * scanlen) -
+ devpriv->ai_scan_pos;
if (todo > PCI230_ADC_FIFOLEVEL_HALFFULL)
todo = PCI230_ADC_FIFOLEVEL_HALFFULL;
}
/* FIFO not empty. */
if (devpriv->hwver > 0) {
/* Read PCI230+/260+ ADC FIFO level. */
- fifoamount = inw(dev->iobase
- + PCI230P_ADCFFLEV);
+ fifoamount =
+ inw(dev->iobase + PCI230P_ADCFFLEV);
if (fifoamount == 0) {
/* Shouldn't happen. */
break;
gainshift = (chan & ~1);
adcen |= 1 << chan;
}
- devpriv->adcg = (devpriv->adcg & ~(3 << gainshift))
- | (pci230_ai_gain[range] << gainshift);
+ devpriv->adcg = (devpriv->adcg & ~(3 << gainshift)) |
+ (pci230_ai_gain[range] << gainshift);
}
/* Set channel scan list. */
zgat = GAT_CONFIG(0, GAT_VCC);
outb(zgat, devpriv->iobase1 + PCI230_ZGAT_SCE);
pci230_ct_setup_ns_mode(dev, 0, I8254_MODE1,
- ((uint64_t) cmd->convert_arg
- * cmd->scan_end_arg),
+ ((uint64_t)cmd->convert_arg *
+ cmd->scan_end_arg),
TRIG_ROUND_UP);
if (cmd->scan_begin_src == TRIG_TIMER) {
/*
* Temporarily enable DAC FIFO, reset it and disable
* FIFO wraparound.
*/
- outw(devpriv->daccon | PCI230P2_DAC_FIFO_EN
- | PCI230P2_DAC_FIFO_RESET,
+ outw(devpriv->daccon | PCI230P2_DAC_FIFO_EN |
+ PCI230P2_DAC_FIFO_RESET,
dev->iobase + PCI230_DACCON);
/* Clear DAC FIFO channel enable register. */
outw(0, dev->iobase + PCI230P2_DACEN);
outb(0, devpriv->iobase1 + PCI230_INT_SCE);
/* Set ADC to a reasonable state. */
devpriv->adcg = 0;
- devpriv->adccon = PCI230_ADC_TRIG_NONE | PCI230_ADC_IM_SE
- | PCI230_ADC_IR_BIP;
+ devpriv->adccon = PCI230_ADC_TRIG_NONE | PCI230_ADC_IM_SE |
+ PCI230_ADC_IR_BIP;
outw(1 << 0, dev->iobase + PCI230_ADCEN);
outw(devpriv->adcg, dev->iobase + PCI230_ADCG);
outw(devpriv->adccon | PCI230_ADC_FIFO_RESET,