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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25845 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt
index 5ec8da8029abfde07e7dd0bd1993f0c80d93d1f5..e3bc2c63d71aa4490aa7ba6ff0dd7ef3fc7221f7 100644 (file)
--- a/lib/Target/Sparc/README.txt
+++ b/lib/Target/Sparc/README.txt
@@ -37,4 +37,18 @@ t1:
 
 1) should be replaced with a brz in V9 mode.
 
-* Same as above, but emit conditional move on register zero (p192) in V9 mode.
+* Same as above, but emit conditional move on register zero (p192) in V9 
+  mode.  Testcase:
+
+int %t1(int %a, int %b) {
+        %C = seteq int %a, 0
+        %D = select bool %C, int %a, int %b
+        ret int %D
+}
+
+* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
+  with the Y register, if they are faster.
+
+* Codegen bswap(load)/store(bswap) -> load/store ASI
+
+

diff --git a/lib/Target/SparcV8/README.txt b/lib/Target/SparcV8/README.txt
index 5ec8da8029abfde07e7dd0bd1993f0c80d93d1f5..e3bc2c63d71aa4490aa7ba6ff0dd7ef3fc7221f7 100644 (file)
--- a/lib/Target/SparcV8/README.txt
+++ b/lib/Target/SparcV8/README.txt
@@ -37,4 +37,18 @@ t1:
 
 1) should be replaced with a brz in V9 mode.
 
-* Same as above, but emit conditional move on register zero (p192) in V9 mode.
+* Same as above, but emit conditional move on register zero (p192) in V9 
+  mode.  Testcase:
+
+int %t1(int %a, int %b) {
+        %C = seteq int %a, 0
+        %D = select bool %C, int %a, int %b
+        ret int %D
+}
+
+* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
+  with the Y register, if they are faster.
+
+* Codegen bswap(load)/store(bswap) -> load/store ASI
+
+