let isReMaterializable = 1 in {
def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
VFPMiscFrm, IIC_VMOVImm,
- "fconstd", "\t$dst, $imm",
+ "vmov.f64", "\t$dst, $imm",
[(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
let Inst{27-23} = 0b11101;
let Inst{21-20} = 0b11;
def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
VFPMiscFrm, IIC_VMOVImm,
- "fconsts", "\t$dst, $imm",
+ "vmov.f32", "\t$dst, $imm",
[(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
let Inst{27-23} = 0b11101;
let Inst{21-20} = 0b11;
void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
- O << '#' << ARM::getVFPf32Imm(FP->getValueAPF());
+ O << '#' << FP->getValueAPF().convertToFloat();
if (VerboseAsm) {
O.PadToColumn(MAI->getCommentColumn());
O << MAI->getCommentString() << ' ';
void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
- O << '#' << ARM::getVFPf64Imm(FP->getValueAPF());
+ O << '#' << FP->getValueAPF().convertToDouble();
if (VerboseAsm) {
O.PadToColumn(MAI->getCommentColumn());
O << MAI->getCommentString() << ' ';
%4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1]
%5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1]
; CHECK: foo:
-; CHECK: fconsts s{{[0-9]+}}, #112
+; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
%6 = fsub float 1.000000e+00, undef ; <float> [#uses=2]
%7 = fsub float %2, undef ; <float> [#uses=1]
%8 = fsub float 0.000000e+00, undef ; <float> [#uses=3]
define arm_apcscc float @t1(float %x) nounwind readnone optsize {
entry:
; CHECK: t1:
-; CHECK: fconsts s1, #16
+; CHECK: vmov.f32 s1, #4.000000e+00
%0 = fadd float %x, 4.000000e+00
ret float %0
}
define arm_apcscc double @t2(double %x) nounwind readnone optsize {
entry:
; CHECK: t2:
-; CHECK: fconstd d1, #8
+; CHECK: vmov.f64 d1, #3.000000e+00
%0 = fadd double %x, 3.000000e+00
ret double %0
}
define arm_apcscc double @t3(double %x) nounwind readnone optsize {
entry:
; CHECK: t3:
-; CHECK: fconstd d1, #170
+; CHECK: vmov.f64 d1, #-1.300000e+01
%0 = fmul double %x, -1.300000e+01
ret double %0
}
define arm_apcscc float @t4(float %x) nounwind readnone optsize {
entry:
; CHECK: t4:
-; CHECK: fconsts s1, #184
+; CHECK: vmov.f32 s1, #-2.400000e+01
%0 = fmul float %x, -2.400000e+01
ret float %0
}
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 6
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 7
define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind {
entry: