def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
"Enable cryptographic instructions">;
+def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
+ "Enable ARMv8 CRC-32 checksum instructions">;
+
/// Cyclone has register move instructions which are "free".
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
"Has zereo-cycle register moves">;
"Cortex-A53 ARM processors",
[FeatureFPARMv8,
FeatureNEON,
- FeatureCrypto]>;
+ FeatureCrypto,
+ FeatureCRC]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors",
[FeatureFPARMv8,
FeatureNEON,
- FeatureCrypto]>;
+ FeatureCrypto,
+ FeatureCRC]>;
def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
"Cyclone",
[FeatureFPARMv8,
FeatureNEON,
FeatureCrypto,
+ FeatureCRC,
FeatureZCRegMove, FeatureZCZeroing]>;
-def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, FeatureNEON]>;
+def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
+ FeatureNEON,
+ FeatureCRC]>;
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>;
let Inst{11-10} = sz;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
+ let Predicates = [HasCRC];
}
//---
AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
def HasNEON : Predicate<"Subtarget->hasNEON()">,
AssemblerPredicate<"FeatureNEON", "neon">;
-def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
+def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
AssemblerPredicate<"FeatureCrypto", "crypto">;
+def HasCRC : Predicate<"Subtarget->hasCRC()">,
+ AssemblerPredicate<"FeatureCRC", "crc">;
//===----------------------------------------------------------------------===//
// ARM64-specific DAG Nodes.
ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool LittleEndian)
: ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
- HasFPARMv8(false), HasNEON(false), HasCrypto(false),
+ HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false),
HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
CPUString(CPU), TargetTriple(TT), IsLittleEndian(LittleEndian) {
// Determine default and user-specified characteristics
bool HasFPARMv8;
bool HasNEON;
bool HasCrypto;
+ bool HasCRC;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove;
bool hasFPARMv8() const { return HasFPARMv8; }
bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; }
+ bool hasCRC() const { return HasCRC; }
bool isLittleEndian() const { return IsLittleEndian; }
-; RUN: llc -march=arm64 -o - %s | FileCheck %s
+; RUN: llc -march=arm64 -mattr=+crc -o - %s | FileCheck %s
define i32 @test_crc32b(i32 %cur, i8 %next) {
; CHECK-LABEL: test_crc32b:
-// RUN: llvm-mc -triple arm64 -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple arm64 -mattr=+crc -show-encoding < %s | FileCheck %s
crc32b w5, w7, w20
crc32h w28, wzr, w30
-// RUN: not llvm-mc -triple arm64-linux-gnu -mattr=-fp-armv8 < %s 2> %t
+// RUN: not llvm-mc -triple arm64-linux-gnu -mattr=-fp-armv8,-crc < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
pmull v0.1q, v1.1d, v2.1d
// CHECK-ERROR: error: instruction requires: crypto
// CHECK-ERROR-NEXT: pmull v0.1q, v1.1d, v2.1d
+// CHECK-ERROR-NEXT: ^
+
+ crc32b w5, w7, w20
+// CHECK-ERROR: error: instruction requires: crc
+// CHECK-ERROR-NEXT: crc32b w5, w7, w20
// CHECK-ERROR-NEXT: ^
-# RUN: llvm-mc -triple=arm64 -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s
# CHECK: crc32b w5, w7, w20
# CHECK: crc32h w28, wzr, w30