Since ARM's prefetch implementation predicted the presence of a instruction

cache prefetch and now that the info from "prefetch" to "ARMPreload" is present,
only add a testcase for PLI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132978 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll
index 03a6947699a954506804c206caa90a682d7614c3..250a34e8b0e8395b1114ec0b3a4cea024c324ce8 100644 (file)
--- a/test/CodeGen/ARM/prefetch.ll
+++ b/test/CodeGen/ARM/prefetch.ll
@@ -64,3 +64,14 @@ entry:
 }
 
 declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
+
+define void @t5(i8* %ptr) nounwind  {
+entry:
+; ARM: t5:
+; ARM: pli [r0]
+
+; THUMB2: t5:
+; THUMB2: pli [r0]
+  tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
+  ret void
+}