initial support for frame pointers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31197 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index b57bf59c2277577558afe00bb19eab35e22de830..7221818d1752784286a6697916232fafca274c37 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -91,10 +91,13 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::VASTART,       MVT::Other, Custom);
   setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
   setOperationAction(ISD::VAEND,         MVT::Other, Expand);
+  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
 
   setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
   setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
 
+  setStackPointerRegisterToSaveRestore(ARM::R13);
+
   setSchedulingPreference(SchedulingForRegPressure);
   computeRegisterProperties();
 }

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index b313d548578e2bfef16e6a73732f257ac702129e..885c5a7b9eb14101131804458faf86c519aae35e 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -19,10 +19,20 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
 #include "llvm/Type.h"
+#include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/STLExtras.h"
 #include <iostream>
 using namespace llvm;
 
+// hasFP - Return true if the specified function should have a dedicated frame
+// pointer register.  This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+//
+static bool hasFP(const MachineFunction &MF) {
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
+  return NoFramePointerElim || MFI->hasVarSizedObjects();
+}
+
 ARMRegisterInfo::ARMRegisterInfo()
   : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
 }
@@ -88,6 +98,9 @@ ARMRegisterInfo::getCalleeSaveRegClasses() const {
 void ARMRegisterInfo::
 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator I) const {
+  if (hasFP(MF)) {
+    assert(0);
+  }
   MBB.erase(I);
 }
 
@@ -114,17 +127,18 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   Offset += StackSize;
 
   assert (Offset >= 0);
+  unsigned BaseRegister = hasFP(MF) ? ARM::R11 : ARM::R13;
   if (Offset < 4096) {
     // Replace the FrameIndex with r13
-    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13, false);
+    MI.getOperand(FrameIdx).ChangeToRegister(BaseRegister, false);
     // Replace the ldr offset with Offset
     MI.getOperand(OffIdx).ChangeToImmediate(Offset);
   } else {
     // Insert a set of r12 with the full address
     // r12 = r13 + offset
     MachineBasicBlock *MBB2 = MI.getParent();
-    BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(ARM::R13).addImm(Offset)
-           .addImm(0).addImm(ARMShift::LSL);
+    BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(BaseRegister)
+      .addImm(Offset).addImm(0).addImm(ARMShift::LSL);
 
     // Replace the FrameIndex with r12
     MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
@@ -140,6 +154,8 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
   MachineFrameInfo  *MFI = MF.getFrameInfo();
   int           NumBytes = (int) MFI->getStackSize();
 
+  bool HasFP = hasFP(MF);
+
   if (MFI->hasCalls()) {
     // We reserve argument space for call sites in the function immediately on
     // entry to the current function.  This eliminates the need for add/sub
@@ -147,6 +163,10 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
     NumBytes += MFI->getMaxCallFrameSize();
   }
 
+  if (HasFP)
+    // Add space for storing the FP
+    NumBytes += 4;
+
   // Align to 8 bytes
   NumBytes = ((NumBytes + 7) / 8) * 8;
 
@@ -155,6 +175,13 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
   //sub sp, sp, #NumBytes
   BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
          .addImm(0).addImm(ARMShift::LSL);
+
+  if (HasFP) {
+    BuildMI(MBB, MBBI, ARM::str, 3)
+      .addReg(ARM::R11).addImm(0).addReg(ARM::R13);
+    BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
+      addImm(ARMShift::LSL);
+  }
 }
 
 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
@@ -166,6 +193,12 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
   MachineFrameInfo *MFI = MF.getFrameInfo();
   int          NumBytes = (int) MFI->getStackSize();
 
+  if (hasFP(MF)) {
+    BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
+      addImm(ARMShift::LSL);
+    BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R11).addImm(0).addReg(ARM::R13);
+  }
+
   //add sp, sp, #NumBytes
   BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
          .addImm(0).addImm(ARMShift::LSL);
@@ -176,7 +209,7 @@ unsigned ARMRegisterInfo::getRARegister() const {
 }
 
 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
-  return ARM::R13;
+  return hasFP(MF) ? ARM::R11 : ARM::R13;
 }
 
 #include "ARMGenRegisterInfo.inc"

diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index ca57598cc9ed96a96bdcf8e65331620075ffad04..24f53d93314fbe487ac87fd5f2268331bf9420db 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -125,7 +125,10 @@ def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
       // r12 == ip (scratch)
       // r11 == Frame Pointer
       // r10 == Stack Limit
-      return end() - 4;
+      if (hasFP(MF))
+        return end() - 5;
+      else
+        return end() - 4;
     }
   }];
 }

diff --git a/test/CodeGen/ARM/alloca.ll b/test/CodeGen/ARM/alloca.ll
new file mode 100644 (file)
index 0000000..ec598ab
--- /dev/null
+++ b/test/CodeGen/ARM/alloca.ll
@@ -0,0 +1,5 @@
+void %f(uint %a) {
+entry:
+       %tmp1032 = alloca ubyte, uint %a
+       ret void
+}