clk: rockchip: rk3399: add SCLK_RMII_SRC for gmac
authorXing Zheng <zhengxing@rock-chips.com>
Wed, 6 Apr 2016 02:45:05 +0000 (10:45 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Wed, 6 Apr 2016 06:34:02 +0000 (14:34 +0800)
Change-Id: I0b678b60ab99ba8166866a7f664314055f55c606
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c
include/dt-bindings/clock/rk3399-cru.h

index 1d2e32023cee83c6fd27191870be25514e1840ce..226772632a7e19f0682fba2c420851b3b08564d1 100644 (file)
@@ -536,7 +536,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK3399_CLKGATE_CON(5), 5, GFLAGS),
 
-       MUX(0, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
+       MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
        GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
                        RK3399_CLKGATE_CON(5), 6, GFLAGS),
index 244746e7dc4cf3347a01bfac5679f5fb59280211..fce4e0bf79ff590eed0f55b3132d71b5dc388b5b 100644 (file)
 #define SCLK_DPHY_TX0_CFG              163
 #define SCLK_DPHY_TX1RX1_CFG           164
 #define SCLK_DPHY_RX0_CFG              165
+#define SCLK_RMII_SRC                  166
 
 #define DCLK_VOP0                      180
 #define DCLK_VOP1                      181