Fixes a case where we generate an incorrect mask for pshfhw in the presence

of undefs and incorrectly determining if we have punpckldq.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63702 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 416029b6b491625dfea7805e63c0d41868567d90..043e551473635ec236f5d5ef702f4303661674dc 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2317,7 +2317,7 @@ bool static isUNPCKLMask(SDOperand *Elts, unsigned NumElts,
     if (!isUndefOrEqual(BitI, j))
       return false;
     if (V2IsSplat) {
-      if (isUndefOrEqual(BitI1, NumElts))
+      if (!isUndefOrEqual(BitI1, NumElts))
         return false;
     } else {
       if (!isUndefOrEqual(BitI1, j + NumElts))
@@ -2652,9 +2652,10 @@ unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
   for (unsigned i = 7; i >= 4; --i) {
     unsigned Val = 0;
     SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() != ISD::UNDEF)
+    if (Arg.getOpcode() != ISD::UNDEF) {
       Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    Mask |= (Val - 4);
+      Mask |= (Val - 4);
+    }
     if (i != 4)
       Mask <<= 2;
   }
@@ -4200,10 +4201,10 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
     // new vector_shuffle with the corrected mask.
     SDValue NewMask = NormalizeMask(PermMask, DAG);
     if (NewMask.getNode() != PermMask.getNode()) {
-      if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
+      if (X86::isUNPCKLMask(NewMask.getNode(), true)) {
         SDValue NewMask = getUnpacklMask(NumElems, DAG, dl);
         return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
-      } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
+      } else if (X86::isUNPCKHMask(NewMask.getNode(), true)) {
         SDValue NewMask = getUnpackhMask(NumElems, DAG, dl);
         return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
       }

diff --git a/test/CodeGen/X86/vec_shuffle-30.ll b/test/CodeGen/X86/vec_shuffle-30.ll
new file mode 100644 (file)
index 0000000..38f02fe
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-30.ll
@@ -0,0 +1,23 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -disable-mmx -o %t -f
+; RUN: grep pshufhw %t | grep 161 | count 1
+; RUN: grep pslldq %t | count 1
+
+
+
+; Test case when creating pshufhw, we incorrectly set the higher order bit
+; for an undef,
+define void @test(<8 x i16>* %dest, <8 x i16> %in) {
+entry:
+  %0 = load <8 x i16>* %dest
+  %1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
+  store <8 x i16> %1, <8 x i16>* %dest
+  ret void
+}                              
+
+; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq
+define void @test2(<4 x i32>* %dest, <4 x i32> %in) {
+entry:
+  %0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2>
+  store <4 x i32> %0, <4 x i32>* %dest
+  ret void
+}       
\ No newline at end of file