ARM: dts: rockchip: rk3288: add qos node

when pd power on/off, the qos regs need to save and restore.

Change-Id: Idd6854022fb25538e82238f25a650a687e918a56
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 7e65b167ab1e935cb06eeb290fbdb3bcc501b798..131759906f0a08880e6b2507abb173ca9571d487 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -637,6 +637,76 @@
                reg = <0xff720000 0x1000>;
        };
 
+       qos_gpu_r: qos@ffaa0000 {
+               compatible = "syscon";
+               reg = <0xffaa0000 0x20>;
+       };
+
+       qos_gpu_w: qos@ffaa0080 {
+               compatible = "syscon";
+               reg = <0xffaa0080 0x20>;
+       };
+
+       qos_vio1_vop: qos@ffad0000 {
+               compatible = "syscon";
+               reg = <0xffad0000 0x20>;
+       };
+
+       qos_vio1_isp_w0: qos@ffad0100 {
+               compatible = "syscon";
+               reg = <0xffad0100 0x20>;
+       };
+
+       qos_vio1_isp_w1: qos@ffad0180 {
+               compatible = "syscon";
+               reg = <0xffad0180 0x20>;
+       };
+
+       qos_vio0_vop: qos@ffad0400 {
+               compatible = "syscon";
+               reg = <0xffad0400 0x20>;
+       };
+
+       qos_vio0_vip: qos@ffad0480 {
+               compatible = "syscon";
+               reg = <0xffad0480 0x20>;
+       };
+
+       qos_vio0_iep: qos@ffad0500 {
+               compatible = "syscon";
+               reg = <0xffad0500 0x20>;
+       };
+
+       qos_vio2_rga_r: qos@ffad0800 {
+               compatible = "syscon";
+               reg = <0xffad0800 0x20>;
+       };
+
+       qos_vio2_rga_w: qos@ffad0880 {
+               compatible = "syscon";
+               reg = <0xffad0880 0x20>;
+       };
+
+       qos_vio1_isp_r: qos@ffad0900 {
+               compatible = "syscon";
+               reg = <0xffad0900 0x20>;
+       };
+
+       qos_video: qos@ffae0000 {
+               compatible = "syscon";
+               reg = <0xffae0000 0x20>;
+       };
+
+       qos_hevc_r: qos@ffaf0000 {
+               compatible = "syscon";
+               reg = <0xffaf0000 0x20>;
+       };
+
+       qos_hevc_w: qos@ffaf0080 {
+               compatible = "syscon";
+               reg = <0xffaf0080 0x20>;
+       };
+
        pmu: power-management@ff730000 {
                compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
                reg = <0xff730000 0x100>;
@@ -697,6 +767,15 @@
                                         <&cru SCLK_ISP_JPE>,
                                         <&cru SCLK_ISP>,
                                         <&cru SCLK_RGA>;
+                               pm_qos = <&qos_vio0_iep>,
+                                        <&qos_vio1_vop>,
+                                        <&qos_vio1_isp_w0>,
+                                        <&qos_vio1_isp_w1>,
+                                        <&qos_vio0_vop>,
+                                        <&qos_vio0_vip>,
+                                        <&qos_vio2_rga_r>,
+                                        <&qos_vio2_rga_w>,
+                                        <&qos_vio1_isp_r>;
                        };
 
                        /*
@@ -708,6 +787,8 @@
                                clocks = <&cru ACLK_HEVC>,
                                         <&cru SCLK_HEVC_CABAC>,
                                         <&cru SCLK_HEVC_CORE>;
+                               pm_qos = <&qos_hevc_r>,
+                                        <&qos_hevc_w>;
                        };
 
                        /*
@@ -719,6 +800,7 @@
                                reg = <RK3288_PD_VIDEO>;
                                clocks = <&cru ACLK_VCODEC>,
                                         <&cru HCLK_VCODEC>;
+                               pm_qos = <&qos_video>;
                        };
 
                        /*
@@ -728,6 +810,8 @@
                        pd_gpu {
                                reg = <RK3288_PD_GPU>;
                                clocks = <&cru ACLK_GPU>;
+                               pm_qos = <&qos_gpu_r>,
+                                        <&qos_gpu_w>;
                        };
                };