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[X86][Haswell][SchedModel] Add architecture specific scheduling models.
author
Quentin Colombet
<qcolombet@apple.com>
Mon, 18 Aug 2014 17:55:43 +0000
(17:55 +0000)
committer
Quentin Colombet
<qcolombet@apple.com>
Mon, 18 Aug 2014 17:55:43 +0000
(17:55 +0000)
Group: Integer MMX and XMM instructions.
Sub-group: Other instructions.
<rdar://problem/
15607571
>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215917
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/X86/X86SchedHaswell.td
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diff --git
a/lib/Target/X86/X86SchedHaswell.td
b/lib/Target/X86/X86SchedHaswell.td
index 38833de7c25013f289e9f8c63f0c81a7811cb426..f998bb6b4db9433aff98e262897889964bb621fc 100644
(file)
--- a/
lib/Target/X86/X86SchedHaswell.td
+++ b/
lib/Target/X86/X86SchedHaswell.td
@@
-1536,4
+1536,13
@@
def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>;
// PSLL,PSRL DQ.
def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>;
+//-- Other --//
+
+// EMMS.
+def WriteEMMS : SchedWriteRes<[]> {
+ let Latency = 13;
+ let NumMicroOps = 31;
+}
+def : InstRW<[WriteEMMS], (instregex "MMX_EMMS")>;
+
} // SchedModel