we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24859
91177308-0d34-0410-b5e6-
96231b3b80d8
if (RegValuesToPass.size() >= 6) {
ValToStore = Lo;
+ ArgOffset += 4;
+ ObjSize = 4;
} else {
RegValuesToPass.push_back(Lo);
}
if (ValToStore.Val) {
if (!StackPtr.Val) {
- StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32);
+ StackPtr = DAG.getRegister(V8::O6, MVT::i32);
NullSV = DAG.getSrcValue(NULL);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
switch (N->getOpcode()) {
default: break;
+ case ISD::Register: return Op;
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse())
if (RegValuesToPass.size() >= 6) {
ValToStore = Lo;
+ ArgOffset += 4;
+ ObjSize = 4;
} else {
RegValuesToPass.push_back(Lo);
}
if (ValToStore.Val) {
if (!StackPtr.Val) {
- StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32);
+ StackPtr = DAG.getRegister(V8::O6, MVT::i32);
NullSV = DAG.getSrcValue(NULL);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
switch (N->getOpcode()) {
default: break;
+ case ISD::Register: return Op;
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse())