config RTL8188EU
- tristate "Realtek 8188EU USB WiFi Support"
- select WIRELESS_EXT
- select WEXT_PRIV
- select IEEE80211
- default y
+ tristate "Realtek 8188E USB WiFi"
+ depends on USB
---help---
- Help message of RTL8188EU & RTL8189ES
+ Help message of RTL8188EU
CONFIG_LOAD_PHY_PARA_FROM_FILE = y
CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY = n
CONFIG_CALIBRATE_TX_POWER_TO_MAX = n
-CONFIG_ODM_ADAPTIVITY = n
+CONFIG_RTW_ADAPTIVITY_EN = disable
+CONFIG_RTW_ADAPTIVITY_MODE = normal
######################## Wake On Lan ##########################
CONFIG_WOWLAN = n
CONFIG_GPIO_WAKEUP = n
CONFIG_PLATFORM_ARM_TCC8900 = n
CONFIG_PLATFORM_ARM_TCC8920 = n
CONFIG_PLATFORM_ARM_TCC8920_JB42 = n
-CONFIG_PLATFORM_ARM_RK2818 = y
+CONFIG_PLATFORM_ARM_RK2818 = n
CONFIG_PLATFORM_ARM_RK3066 = n
-CONFIG_PLATFORM_ARM_RK3188 = n
+CONFIG_PLATFORM_ARM_RK3188 = y
CONFIG_PLATFORM_ARM_URBETTER = n
CONFIG_PLATFORM_ARM_TI_PANDA = n
CONFIG_PLATFORM_MIPS_JZ4760 = n
CONFIG_PLATFORM_ARM_SUN7I = n
CONFIG_PLATFORM_ARM_SUN8I = n
CONFIG_PLATFORM_ACTIONS_ATM702X = n
+CONFIG_PLATFORM_ACTIONS_ATM705X = n
CONFIG_PLATFORM_ACTIONS_ATV5201 = n
CONFIG_PLATFORM_ARM_RTD299X = n
CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n
hal/OUTSRC/odm_interface.o\
hal/OUTSRC/odm_HWConfig.o\
hal/OUTSRC/odm.o\
- hal/OUTSRC/HalPhyRf.o
+ hal/OUTSRC/HalPhyRf.o\
+ hal/OUTSRC/PhyDM_Adaptivity.o
EXTRA_CFLAGS += -I$(src)/platform
_PLATFORM_FILES := platform/platform_ops.o
EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_TO_MAX
endif
-ifeq ($(CONFIG_ODM_ADAPTIVITY), y)
-EXTRA_CFLAGS += -DCONFIG_ODM_ADAPTIVITY
+ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), disable)
+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=0
+else ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), enable)
+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=1
+endif
+
+ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), normal)
+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=0
+else ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), carrier_sense)
+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=1
endif
ifeq ($(CONFIG_WOWLAN), y)
MODULE_NAME :=wlan
endif
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM705X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ACTIONS_ATM705X
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS
+
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+_PLATFORM_FILES += platform/platform_arm_act_sdio.o
+endif
+
+ARCH := arm
+CROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi-
+KSRC := /home/android_sdk/Action-semi/705a_android_L/android/kernel
+endif
+
ifeq ($(CONFIG_PLATFORM_TI_AM3517), y)
EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE
CROSS_COMPILE := arm-eabi-
endif
ifeq ($(CONFIG_PLATFORM_ARM_RK3188), y)
-EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS -DCONFIG_MINIMAL_MEMORY_USAGE
-EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
-EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_MINIMAL_MEMORY_USAGE
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS
+
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
ARCH := arm
CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
KSRC := /home/android_sdk/Rockchip/Rk3188/kernel
\r
//free bc/mc sta_info\r
psta = rtw_get_bcmc_stainfo(padapter); \r
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); \r
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
rtw_free_stainfo(padapter, psta);\r
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
\r
\r
_rtw_spinlock_free(&pmlmepriv->bcn_update_lock);\r
\r
_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);\r
\r
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); \r
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
rtw_free_stainfo(padapter, psta);\r
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); \r
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
\r
_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);\r
} \r
\r
beacon_updated = bss_cap_update_on_sta_leave(padapter, psta);\r
\r
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); \r
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
rtw_free_stainfo(padapter, psta);\r
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
\r
\r
return beacon_updated;\r
rtw_free_all_stainfo(padapter);\r
\r
psta = rtw_get_bcmc_stainfo(padapter);\r
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); \r
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
rtw_free_stainfo(padapter, psta);\r
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);\r
\r
rtw_init_bcmc_stainfo(padapter); \r
\r
u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
{
uint cnt;
- u8 *wpsie_ptr=NULL;
- u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04};
+ u8 *wpsie_ptr = NULL;
+ u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04};
- if(wps_ielen)
+ if (wps_ielen)
*wps_ielen = 0;
- if(!in_ie || in_len<=0)
+ if (!in_ie) {
+ rtw_warn_on(1);
+ return wpsie_ptr;
+ }
+
+ if (in_len <= 0)
return wpsie_ptr;
cnt = 0;
- while(cnt<in_len)
- {
+ while (cnt + 1 + 4 < in_len) {
eid = in_ie[cnt];
- if((eid==_WPA_IE_ID_)&&(_rtw_memcmp(&in_ie[cnt+2], wps_oui, 4)==_TRUE))
- {
- wpsie_ptr = &in_ie[cnt];
+ if (cnt + 1 + 4 >= MAX_IE_SZ) {
+ rtw_warn_on(1);
+ return NULL;
+ }
- if(wps_ie)
- _rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt+1]+2);
-
- if(wps_ielen)
- *wps_ielen = in_ie[cnt+1]+2;
-
- cnt+=in_ie[cnt+1]+2;
+ if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wps_oui, 4) == _TRUE) {
+ wpsie_ptr = in_ie + cnt;
+
+ if (wps_ie)
+ _rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+ if (wps_ielen)
+ *wps_ielen = in_ie[cnt + 1] + 2;
break;
+ } else {
+ cnt += in_ie[cnt + 1] + 2;
}
- else
- {
- cnt+=in_ie[cnt+1]+2; //goto next
- }
- }
+ }
return wpsie_ptr;
}
*/
u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
{
- uint cnt = 0;
- u8 *p2p_ie_ptr;
- u8 eid, p2p_oui[4]={0x50,0x6F,0x9A,0x09};
+ uint cnt;
+ u8 *p2p_ie_ptr = NULL;
+ u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};
- if ( p2p_ielen != NULL )
+ if (p2p_ielen)
*p2p_ielen = 0;
- while(cnt<in_len)
- {
+ if (!in_ie || in_len < 0) {
+ rtw_warn_on(1);
+ return p2p_ie_ptr;
+ }
+
+ if (in_len <= 0)
+ return p2p_ie_ptr;
+
+ cnt = 0;
+
+ while (cnt + 1 + 4 < in_len) {
eid = in_ie[cnt];
- if ((in_len < 0) || (cnt > MAX_IE_SZ)) {
- rtw_dump_stack();
+
+ if (cnt + 1 + 4 >= MAX_IE_SZ) {
+ rtw_warn_on(1);
return NULL;
- }
- if( ( eid == _VENDOR_SPECIFIC_IE_ ) && ( _rtw_memcmp( &in_ie[cnt+2], p2p_oui, 4) == _TRUE ) )
- {
+ }
+
+ if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], p2p_oui, 4) == _TRUE) {
p2p_ie_ptr = in_ie + cnt;
-
- if ( p2p_ie != NULL )
- {
- _rtw_memcpy( p2p_ie, &in_ie[ cnt ], in_ie[ cnt + 1 ] + 2 );
- }
- if ( p2p_ielen != NULL )
- {
- *p2p_ielen = in_ie[ cnt + 1 ] + 2;
- }
-
- return p2p_ie_ptr;
+ if (p2p_ie)
+ _rtw_memcpy(p2p_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+ if (p2p_ielen)
+ *p2p_ielen = in_ie[cnt + 1] + 2;
break;
+ } else {
+ cnt += in_ie[cnt + 1] + 2;
}
- else
- {
- cnt += in_ie[ cnt + 1 ] +2; //goto next
- }
-
- }
- return NULL;
+ }
+ return p2p_ie_ptr;
}
/**
rtw_tdls_cmd(adapter, myid(&(adapter->eeprompriv)), TDLS_RS_RCR);
rtw_reset_tdls_info(adapter);
rtw_free_all_stainfo(adapter);
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
}
else
#endif //CONFIG_TDLS
{
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
rtw_free_stainfo(adapter, psta);
}
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
}
rtw_free_all_stainfo(adapter);
psta = rtw_get_bcmc_stainfo(adapter);
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
rtw_free_stainfo(adapter, psta);
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
rtw_init_bcmc_stainfo(adapter);
}
#endif // CONFIG_IPS
}
-void rtw_scan_abort(_adapter *adapter)
+u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms)
{
- u32 cnt=0;
u32 start;
- struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
- struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+ u32 pass_ms;
+ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
start = rtw_get_current_time();
pmlmeext->scan_abort = _TRUE;
while (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)
- && rtw_get_passing_time_ms(start) <= 200) {
+ && rtw_get_passing_time_ms(start) <= timeout_ms) {
if (adapter->bDriverStopped || adapter->bSurpriseRemoved)
break;
rtw_indicate_scan_done(adapter, _TRUE);
}
pmlmeext->scan_abort = _FALSE;
+ pass_ms = rtw_get_passing_time_ms(start);
+
+ return pass_ms;
+}
+
+void rtw_scan_abort_no_wait(_adapter *adapter)
+{
+ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+
+ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
+ pmlmeext->scan_abort = _TRUE;
+}
+
+void rtw_scan_abort(_adapter *adapter)
+{
+ rtw_scan_abort_timeout(adapter, 200);
}
static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork)
pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
if(pcur_sta){
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
rtw_free_stainfo(adapter, pcur_sta);
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
}
ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);
check_fwstate(pmlmepriv,WIFI_ADHOC_STATE))
{
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
rtw_free_stainfo(adapter, psta);
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
if(adapter->stapriv.asoc_sta_count== 1) //a sta + bc/mc_stainfo (not Ibss_stainfo)
{
}
#endif //CONFIG_CONCURRENT_MODE
+
+static const char *miracast_mode_str[] = {
+ "DISABLED",
+ "SOURCE",
+ "SINK",
+ "INVALID",
+};
+
+const char *get_miracast_mode_str(int mode)
+{
+ if (mode < MIRACAST_DISABLED || mode >= MIRACAST_INVALID)
+ mode = MIRACAST_INVALID;
+
+ return miracast_mode_str[mode];
+}
+
reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
- DBG_871X("%s Reason code(%d)\n", __FUNCTION__,reason);
-
rtw_lock_rx_suspend_timeout(8000);
#ifdef CONFIG_AP_MODE
//rtw_free_stainfo(padapter, psta);
//_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
- DBG_871X_LEVEL(_drv_always_, "ap recv deauth reason code(%d) sta:%pM\n",
- reason, GetAddr2Ptr(pframe));
+ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
+ , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe));
psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
if(psta)
}
}
- DBG_871X_LEVEL(_drv_always_, "sta recv deauth reason code(%d) sta:%pM, ignore = %d\n",
- reason, GetAddr3Ptr(pframe), ignore_received_deauth);
-
+ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n"
+ , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe), ignore_received_deauth);
+
if ( 0 == ignore_received_deauth )
{
- receive_disconnect(padapter, GetAddr3Ptr(pframe) ,reason);
+ receive_disconnect(padapter, GetAddr2Ptr(pframe), reason);
}
}
pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
- DBG_871X("%s Reason code(%d)\n", __FUNCTION__,reason);
-
rtw_lock_rx_suspend_timeout(8000);
#ifdef CONFIG_AP_MODE
//rtw_free_stainfo(padapter, psta);
//_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
- DBG_871X_LEVEL(_drv_always_, "ap recv disassoc reason code(%d) sta:%pM\n",
- reason, GetAddr2Ptr(pframe));
+ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
+ , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe));
psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
if(psta)
else
#endif
{
- DBG_871X_LEVEL(_drv_always_, "sta recv disassoc reason code(%d) sta:%pM\n",
- reason, GetAddr3Ptr(pframe));
-
- receive_disconnect(padapter, GetAddr3Ptr(pframe), reason);
+ DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
+ , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe));
+
+ receive_disconnect(padapter, GetAddr2Ptr(pframe), reason);
}
pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
return _SUCCESS;
//val8 |= 0x0f;
//rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8));
#if defined(CONFIG_STA_MODE_SCAN_UNDER_AP_MODE) || defined(CONFIG_ATMEL_RC_PATCH)
- if((padapter->pbuddy_adapter->mlmeextpriv.mlmext_info.state&0x03) == WIFI_FW_AP_STATE)
- {
- if( pmlmeinfo->scan_cnt == RTW_SCAN_NUM_OF_CH )
- {
- pmlmeinfo->scan_cnt = 0;
- survey_channel = pbuddy_mlmeext->cur_channel;
- stay_buddy_ch = 1;
- }
- else
- {
- if( pmlmeinfo->scan_cnt == 0 )
+ if ((padapter->pbuddy_adapter->mlmeextpriv.mlmext_info.state&0x03) == WIFI_FW_AP_STATE) {
+ if (pmlmeinfo->scan_cnt == RTW_SCAN_NUM_OF_CH) {
+ if (pmlmeinfo->backop_cnt == 0)
+ stay_buddy_ch = 1;
+ else if (pmlmeinfo->backop_cnt == RTW_STAY_AP_CH_MILLISECOND)
stay_buddy_ch = 2;
+
+ if (stay_buddy_ch == 2) {
+ pmlmeinfo->scan_cnt = 1;
+ pmlmeinfo->backop_cnt = 0;
+ } else if (stay_buddy_ch == 1) {
+ pmlmeinfo->backop_cnt++;
+ survey_channel = pbuddy_mlmeext->cur_channel;
+ } else {
+ pmlmeinfo->backop_cnt++;
+ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time);
+ return;
+ }
+ } else {
pmlmeinfo->scan_cnt++;
}
}
// 1,2-6-3,4-6-5,6-6-7,8-6-9,10-6-11,12-6-13,14
//if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)==_TRUE)
- if( stay_buddy_ch == 1 )
- set_survey_timer(pmlmeext, pmlmeext->chan_scan_time * RTW_STAY_AP_CH_MILLISECOND );
- else {
- if( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
- set_survey_timer(pmlmeext, 20);
- else
- set_survey_timer(pmlmeext, 40);
- }
-#elif defined(CONFIG_STA_MODE_SCAN_UNDER_AP_MODE)
- if( stay_buddy_ch == 1 )
- set_survey_timer(pmlmeext, pmlmeext->chan_scan_time * RTW_STAY_AP_CH_MILLISECOND );
+ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+ set_survey_timer(pmlmeext, 20);
else
- set_survey_timer(pmlmeext, pmlmeext->chan_scan_time);
+ set_survey_timer(pmlmeext, 40);
#else
- set_survey_timer(pmlmeext, pmlmeext->chan_scan_time);
+ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time);
#endif
}
else
#if defined(CONFIG_STA_MODE_SCAN_UNDER_AP_MODE) || defined(CONFIG_ATMEL_RC_PATCH)
pmlmeinfo->scan_cnt = 0;
+ pmlmeinfo->backop_cnt = 0;
#endif
#ifdef CONFIG_ANTENNA_DIVERSITY
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- //check A3
if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
return _SUCCESS;
if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
{
#if defined(CONFIG_STA_MODE_SCAN_UNDER_AP_MODE) || defined(CONFIG_ATMEL_RC_PATCH)
- if( padapter->mlmeextpriv.mlmext_info.scan_cnt != RTW_SCAN_NUM_OF_CH )
+ if (padapter->mlmeextpriv.mlmext_info.scan_cnt != RTW_SCAN_NUM_OF_CH
+ || padapter->mlmeextpriv.mlmext_info.backop_cnt == RTW_STAY_AP_CH_MILLISECOND)
#endif
pmlmeext->sitesurvey_res.channel_idx++;
}
return H2C_SUCCESS;
}
-int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,
+u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num)
+{
+/* interval larger than this is treated as backgroud scan */
+#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS
+#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000
+#endif
+
+#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST
+#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1
+#endif
+#ifndef RTW_SCAN_SPARSE_CH_NUM_BG
+#define RTW_SCAN_SPARSE_CH_NUM_BG 4
+#endif
+
+#define SCAN_SPARSE_CH_NUM_INVALID 255
+
+ static u8 token = 255;
+ u32 interval;
+ bool busy_traffic = _FALSE;
+ bool miracast_enabled = _FALSE;
+ bool bg_scan = _FALSE;
+ u8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID;
+ u8 scan_division_num;
+ u8 ret_num = ch_num;
+ struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+ if (regsty->wifi_spec)
+ goto exit;
+
+ /* assume ch_num > 6 is normal scan */
+ if (ch_num <= 6)
+ goto exit;
+
+ if (mlmeext->last_scan_time == 0)
+ mlmeext->last_scan_time = rtw_get_current_time();
+
+ interval = rtw_get_passing_time_ms(mlmeext->last_scan_time);
+
+ if (adapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE
+ #ifdef CONFIG_CONCURRENT_MODE
+ || (adapter->pbuddy_adapter && adapter->pbuddy_adapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE)
+ #endif
+ )
+ busy_traffic = _TRUE;
+
+ #ifdef CONFIG_WFD
+ if (is_miracast_enabled(adapter->wfd_info.stack_wfd_mode)
+ #ifdef CONFIG_CONCURRENT_MODE
+ || (adapter->pbuddy_adapter && is_miracast_enabled(adapter->pbuddy_adapter->wfd_info.stack_wfd_mode))
+ #endif
+ )
+ miracast_enabled = _TRUE;
+ #endif
+
+ if (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS)
+ bg_scan = _TRUE;
+
+ /* max_allow_ch by conditions*/
+
+ #if RTW_SCAN_SPARSE_MIRACAST
+ if (miracast_enabled == _TRUE && busy_traffic == _TRUE)
+ max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST);
+ #endif
+
+ #if RTW_SCAN_SPARSE_BG
+ if (bg_scan == _TRUE)
+ max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG);
+ #endif
+
+
+ if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) {
+ int i;
+ int k = 0;
+
+ scan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch)?1:0);
+ token = (token + 1) % scan_division_num;
+
+ if (0)
+ DBG_871X("scan_division_num:%u, token:%u\n", scan_division_num, token);
+
+ for (i = 0; i < ch_num; i++) {
+ if (ch[i].hw_value && (i % scan_division_num) == token
+ ) {
+ if (i != k)
+ _rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel));
+ k++;
+ }
+ }
+
+ _rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel));
+
+ ret_num = k;
+ mlmeext->last_scan_time = rtw_get_current_time();
+ }
+
+exit:
+ return ret_num;
+}
+
+static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,
u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num)
{
int i, j;
}
}
-#ifdef CONFIG_SCAN_SPARSE //partial scan, ASUS RK3188 use the feature
- /* assume j>6 is normal scan */
- if ((j > 6) && (padapter->registrypriv.wifi_spec != 1))
- {
- static u8 token = 0;
- u32 interval;
-
- if (pmlmeext->last_scan_time == 0)
- pmlmeext->last_scan_time = rtw_get_current_time();
-
- interval = rtw_get_passing_time_ms(pmlmeext->last_scan_time);
- if ((interval > ALLOW_SCAN_INTERVAL)
-#if 0 // Miracast can't do AP scan
- || (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE)
-#ifdef CONFIG_CONCURRENT_MODE
- || (padapter->pbuddy_adapter
- && (padapter->pbuddy_adapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE))
-#endif // CONFIG_CONCURRENT_MODE
-#endif
- )
- {
- // modify scan plan
- int k = 0;
- _rtw_memset(in, 0, sizeof(struct rtw_ieee80211_channel)*in_num);
- _rtw_memcpy(in, out, sizeof(struct rtw_ieee80211_channel)*j);
- _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel)*j);
-
- for (i=0;i<j;i++) {
- if (in[i].hw_value && (i%SCAN_DIVISION_NUM) == token) {
- _rtw_memcpy(&out[k], &in[i], sizeof(struct rtw_ieee80211_channel));
- k++;
- }
- if(k>=out_num)
- break;
- }
-
- j = k;
- token = (token+1)%SCAN_DIVISION_NUM;
- }
-
- pmlmeext->last_scan_time = rtw_get_current_time();
- }
-#endif //CONFIG_SCAN_SPARSE
+ /* scan_sparse */
+ j = rtw_scan_sparse(padapter, out, j);
return j;
}
psta = rtw_get_stainfo(&Adapter->stapriv, macaddr);
if (psta != NULL) {
- _enter_critical(&(Adapter->stapriv.sta_hash_lock), &irqL);
+ //_enter_critical(&(Adapter->stapriv.sta_hash_lock), &irqL);
rtw_free_stainfo(Adapter, psta);
- _exit_critical(&(Adapter->stapriv.sta_hash_lock), &irqL);
+ //_exit_critical(&(Adapter->stapriv.sta_hash_lock), &irqL);
}
return status;
/* BIT13 */"ODM_COMP_RXHP",
/* BIT14 */"ODM_COMP_MP",
/* BIT15 */"ODM_COMP_DYNAMIC_ATC",
- /* BIT16 */"ODM_COMP_EDCA_TURBO",
- /* BIT17 */"ODM_COMP_EARLY_MODE",
- /* BIT18 */NULL,
- /* BIT19 */NULL,
- /* BIT20 */NULL,
- /* BIT21 */NULL,
- /* BIT22 */NULL,
+ /* BIT16 */"ODM_COMP_ACS",
+ /* BIT17 */"PHYDM_COMP_ADAPTIVITY",
+ /* BIT18 */"PHYDM_COMP_RA_DBG",
+ /* BIT19 */"PHYDM_COMP_TXBF",
+ /* BIT20 */"ODM_COMP_EDCA_TURBO",
+ /* BIT21 */"ODM_COMP_EARLY_MODE",
+ /* BIT22 */"ODM_FW_DEBUG_TRACE",
/* BIT23 */NULL,
/* BIT24 */"ODM_COMP_TX_PWR_TRACK",
/* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
/* BIT26 */"ODM_COMP_CALIBRATION",
/* BIT27 */NULL,
/* BIT28 */NULL,
- /* BIT29 */NULL,
+ /* BIT29 */"BEAMFORMING_DEBUG",
/* BIT30 */"ODM_COMP_COMMON",
/* BIT31 */"ODM_COMP_INIT",
};
/* BIT12 */"ODM_BB_RXHP",
/* BIT13 */"ODM_BB_ADAPTIVITY",
/* BIT14 */"ODM_BB_DYNAMIC_ATC",
- /* BIT15 */NULL,
- /* BIT16 */"ODM_MAC_EDCA_TURBO",
- /* BIT17 */"ODM_MAC_EARLY_MODE",
+ /* BIT15 */"ODM_BB_NHM_CNT",
+ /* BIT16 */"ODM_BB_PRIMARY_CCA",
+ /* BIT17 */"ODM_BB_TXBF",
/* BIT18 */NULL,
/* BIT19 */NULL,
- /* BIT20 */NULL,
- /* BIT21 */NULL,
+ /* BIT20 */"ODM_MAC_EDCA_TURBO",
+ /* BIT21 */"ODM_MAC_EARLY_MODE",
/* BIT22 */NULL,
/* BIT23 */NULL,
/* BIT24 */"ODM_RF_TX_PWR_TRACK",
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
- u64 dbg_comp;
+ u64 dbg_comp = 0;
int i;
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx \n", dbg_comp);
for (i=0;i<RTW_ODM_COMP_MAX;i++) {
if (odm_comp_str[i])
- DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
- (BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
+ DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
+ (BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
}
}
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
- u32 dbg_level;
+ u32 dbg_level = 0;
int i;
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
- DBG_871X_SEL_NL(sel, "odm.DebugDebugLevel = %u\n", dbg_level);
+ DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
for (i=0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
if (odm_dbg_level_str[i])
DBG_871X_SEL_NL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
for (i=0;i<RTW_ODM_ABILITY_MAX;i++) {
if (odm_ability_str[i])
- DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
- (BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
+ DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
+ (BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
}
}
rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
}
+void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
+{
+ DBG_871X_SEL_NL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
+}
+
+#define RTW_ADAPTIVITY_EN_DISABLE 0
+#define RTW_ADAPTIVITY_EN_ENABLE 1
+
+void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
+{
+ struct registry_priv *regsty = &adapter->registrypriv;
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ DM_ODM_T *odm = &hal_data->odmpriv;
+
+ DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_EN_");
+
+ if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE) {
+ DBG_871X_SEL(sel, "DISABLE\n");
+ } else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) {
+ DBG_871X_SEL(sel, "ENABLE\n");
+ } else {
+ DBG_871X_SEL(sel, "INVALID\n");
+ }
+}
+
+#define RTW_ADAPTIVITY_MODE_NORMAL 0
+#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
+
+void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
+{
+ struct registry_priv *regsty = &adapter->registrypriv;
+
+ DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_MODE_");
+
+ if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL) {
+ DBG_871X_SEL(sel, "NORMAL\n");
+ } else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE) {
+ DBG_871X_SEL(sel, "CARRIER_SENSE\n");
+ } else {
+ DBG_871X_SEL(sel, "INVALID\n");
+ }
+}
+
+#define RTW_ADAPTIVITY_DML_DISABLE 0
+#define RTW_ADAPTIVITY_DML_ENABLE 1
+
+void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter)
+{
+ struct registry_priv *regsty = &adapter->registrypriv;
+
+ DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DML_");
+
+ if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE) {
+ DBG_871X_SEL(sel, "DISABLE\n");
+ } else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE) {
+ DBG_871X_SEL(sel, "ENABLE\n");
+ } else {
+ DBG_871X_SEL(sel, "INVALID\n");
+ }
+}
+
+void rtw_odm_adaptivity_dc_backoff_msg(void *sel, _adapter *adapter)
+{
+ struct registry_priv *regsty = &adapter->registrypriv;
+
+ DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DC_BACKOFF:%u\n", regsty->adaptivity_dc_backoff);
+}
+
+bool rtw_odm_adaptivity_needed(_adapter *adapter)
+{
+ struct registry_priv *regsty = &adapter->registrypriv;
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+ bool ret = _FALSE;
+
+ if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
+ ret = _TRUE;
+
+ if (ret == _TRUE) {
+ rtw_odm_adaptivity_ver_msg(RTW_DBGDUMP, adapter);
+ rtw_odm_adaptivity_en_msg(RTW_DBGDUMP, adapter);
+ rtw_odm_adaptivity_mode_msg(RTW_DBGDUMP, adapter);
+ rtw_odm_adaptivity_dml_msg(RTW_DBGDUMP, adapter);
+ rtw_odm_adaptivity_dc_backoff_msg(RTW_DBGDUMP, adapter);
+ }
+
+ return ret;
+}
+
void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
- DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n"
- , "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
- DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n"
+ rtw_odm_adaptivity_ver_msg(sel, adapter);
+ rtw_odm_adaptivity_en_msg(sel, adapter);
+ rtw_odm_adaptivity_mode_msg(sel, adapter);
+ rtw_odm_adaptivity_dml_msg(sel, adapter);
+ rtw_odm_adaptivity_dc_backoff_msg(sel, adapter);
+
+ DBG_871X_SEL_NL(sel, "%10s %16s\n"
+ , "TH_L2H_ini", "TH_EDCCA_HL_diff");
+ DBG_871X_SEL_NL(sel, "0x%-8x %-16d\n"
, (u8)odm->TH_L2H_ini
, odm->TH_EDCCA_HL_diff
- , odm->IGI_Base
- , odm->ForceEDCCA
- , odm->AdapEn_RSSI
- , odm->IGI_LowerBound
);
+
+ DBG_871X_SEL_NL(sel, "%15s %9s\n", "AdapEnableState","Adap_Flag");
+ DBG_871X_SEL_NL(sel, "%-15x %-9x \n"
+ , odm->Adaptivity_enable
+ , odm->adaptivity_flag
+ );
+
+
}
-void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
- s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
+void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
odm->TH_L2H_ini = TH_L2H_ini;
odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
- odm->IGI_Base = IGI_Base;
- odm->ForceEDCCA = ForceEDCCA;
- odm->AdapEn_RSSI = AdapEn_RSSI;
- odm->IGI_LowerBound = IGI_LowerBound;
}
void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
pcfg80211_wdinfo->is_ro_ch = _FALSE;
pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time();
- if (pcfg80211_wdinfo->not_indic_ro_ch_exp == _TRUE)
- return;
-
- DBG_871X("cfg80211_remain_on_channel_expired, ch=%d, bw=%d, offset=%d\n",
- rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter));
+ DBG_871X("cfg80211_remain_on_channel_expired cookie:0x%llx, ch=%d, bw=%d, offset=%d\n"
+ , pcfg80211_wdinfo->remain_on_ch_cookie
+ , rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter));
rtw_cfg80211_remain_on_channel_expired(padapter,
pcfg80211_wdinfo->remain_on_ch_cookie,
if (psta == NULL)
goto exit;
+ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+ rtw_list_delete(&psta->hash_list);
+ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]));
+ pstapriv->asoc_sta_count --;
+ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
_enter_critical_bh(&psta->lock, &irqL0);
psta->state &= ~_FW_LINKED;
_exit_critical_bh(&pxmitpriv->lock, &irqL0);
- rtw_list_delete(&psta->hash_list);
- RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]));
- pstapriv->asoc_sta_count --;
-
-
// re-init sta_info; 20061114 // will be init in alloc_stainfo
//_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
//_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
_rtw_spinlock_free(&psta->lock);
//_enter_critical_bh(&(pfree_sta_queue->lock), &irqL0);
+ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
+ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL0);
exit:
struct sta_info *psta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info* pbcmc_stainfo =rtw_get_bcmc_stainfo( padapter);
+ u8 free_sta_num = 0;
+ char free_sta_list[NUM_STA];
+ int stainfo_offset;
_func_enter_;
plist = get_next(plist);
- if(pbcmc_stainfo!=psta)
- rtw_free_stainfo(padapter , psta);
-
+ if(pbcmc_stainfo!=psta)
+ {
+ rtw_list_delete(&psta->hash_list);
+ //rtw_free_stainfo(padapter , psta);
+ stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
+ if (stainfo_offset_valid(stainfo_offset)) {
+ free_sta_list[free_sta_num++] = stainfo_offset;
+ }
+ }
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+ for (index = 0; index < free_sta_num; free_sta_num++)
+ {
+ psta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]);
+ rtw_free_stainfo(padapter , psta);
+ }
exit:
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+//============================================================\r
+// include files\r
+//============================================================\r
+//#include "Mp_Precomp.h"\r
+#include "odm_precomp.h"\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
+#if WPP_SOFTWARE_TRACE\r
+#include "PhyDM_Adaptivity.tmh"\r
+#endif\r
+#endif\r
+\r
+\r
+VOID\r
+Phydm_CheckAdaptivity(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+ \r
+ if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) {\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH));\r
+ } else\r
+#endif\r
+ {\r
+ if (Adaptivity->DynamicLinkAdaptivity == TRUE) {\r
+ if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) {\r
+ Phydm_NHMCounterStatistics(pDM_Odm);\r
+ Phydm_CheckEnvironment(pDM_Odm);\r
+ } else if (!pDM_Odm->bLinked)\r
+ Adaptivity->bCheck = FALSE;\r
+ } else {\r
+ pDM_Odm->Adaptivity_enable = TRUE;\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8195A))\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ else\r
+ pDM_Odm->adaptivity_flag = TRUE;\r
+ }\r
+ }\r
+ } else {\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ }\r
+\r
+ \r
+\r
+}\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+BOOLEAN\r
+Phydm_CheckChannelPlan(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);\r
+ \r
+ if (pMgntInfo->RegEnableAdaptivity == 2) {\r
+ if (pDM_Odm->Carrier_Sense_enable == FALSE) { /*check domain Code for Adaptivity or CarrierSense*/\r
+ if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&\r
+ !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
+ return TRUE;\r
+ } else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
+ !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
+ return TRUE;\r
+\r
+ } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));\r
+ return TRUE;\r
+ }\r
+ } else {\r
+ if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&\r
+ !(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
+ return TRUE;\r
+ }\r
+\r
+ else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
+ !(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
+ return TRUE;\r
+\r
+ } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));\r
+ return TRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ return FALSE;\r
+\r
+}\r
+#endif\r
+\r
+VOID\r
+Phydm_NHMCounterStatisticsInit(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
+ /*PHY parameters initialize for n series*/\r
+ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/\r
+ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/\r
+ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/\r
+ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ /*PHY parameters initialize for ac series*/\r
+ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/\r
+ ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/\r
+ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/\r
+ ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/\r
+\r
+ }\r
+#endif\r
+}\r
+\r
+VOID\r
+Phydm_NHMCounterStatistics(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))\r
+ return;\r
+\r
+ /*Get NHM report*/\r
+ Phydm_GetNHMCounterStatistics(pDM_Odm);\r
+\r
+ /*Reset NHM counter*/\r
+ Phydm_NHMCounterStatisticsReset(pDM_Odm);\r
+}\r
+\r
+VOID\r
+Phydm_GetNHMCounterStatistics(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u4Byte value32 = 0;\r
+#if (RTL8195A_SUPPORT == 0)\r
+ if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
+ value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
+#endif\r
+ value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);\r
+\r
+ pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);\r
+ pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8);\r
+\r
+}\r
+\r
+VOID\r
+Phydm_NHMCounterStatisticsReset(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);\r
+ }\r
+\r
+#endif\r
+\r
+}\r
+\r
+VOID\r
+Phydm_SetEDCCAThreshold(\r
+ IN PVOID pDM_VOID,\r
+ IN s1Byte H2L,\r
+ IN s1Byte L2H\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)L2H);\r
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)H2L);\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte0, (u1Byte)L2H);\r
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte1, (u1Byte)H2L);\r
+ }\r
+#endif\r
+\r
+}\r
+\r
+VOID\r
+Phydm_SetTRxMux(\r
+ IN PVOID pDM_VOID,\r
+ IN PhyDM_Trx_MUX_Type txMode,\r
+ IN PhyDM_Trx_MUX_Type rxMode\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/\r
+ if (pDM_Odm->RFType > ODM_1T1R) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/\r
+ }\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/\r
+ if (pDM_Odm->RFType > ODM_1T1R) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/\r
+ }\r
+ }\r
+#endif\r
+\r
+}\r
+\r
+VOID\r
+Phydm_MACEDCCAState(\r
+ IN PVOID pDM_VOID,\r
+ IN PhyDM_MACEDCCA_Type State\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ if (State == PhyDM_IGNORE_EDCCA) {\r
+ ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); /*ignore EDCCA reg520[15]=1*/\r
+ ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); /*reg524[11]=0*/\r
+ } else { /*don't set MAC ignore EDCCA signal*/\r
+ ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0\14*/\r
+ ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); /*reg524[11]=1 */\r
+ }\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State));\r
+\r
+}\r
+\r
+BOOLEAN\r
+Phydm_CalNHMcnt(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u2Byte Base = 0;\r
+\r
+ Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;\r
+\r
+ if (Base != 0) {\r
+ pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;\r
+ pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;\r
+ }\r
+ if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)\r
+ return TRUE; /*clean environment*/\r
+ else\r
+ return FALSE; /*noisy environment*/\r
+\r
+}\r
+\r
+\r
+VOID\r
+Phydm_CheckEnvironment(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+ BOOLEAN isCleanEnvironment = FALSE;\r
+\r
+ if (Adaptivity->bFirstLink == TRUE) {\r
+ if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8195A))\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ else\r
+ pDM_Odm->adaptivity_flag = TRUE;\r
+\r
+ Adaptivity->bFirstLink = FALSE;\r
+ return;\r
+ } else {\r
+ if (Adaptivity->NHMWait < 3) { /*Start enter NHM after 4 NHMWait*/\r
+ Adaptivity->NHMWait++;\r
+ Phydm_NHMCounterStatistics(pDM_Odm);\r
+ return;\r
+ } else {\r
+ Phydm_NHMCounterStatistics(pDM_Odm);\r
+ isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);\r
+ if (isCleanEnvironment == TRUE) {\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
+ pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; /*mode 1*/\r
+ pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;\r
+#endif\r
+ pDM_Odm->Adaptivity_enable = TRUE;\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8195A))\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ else\r
+ pDM_Odm->adaptivity_flag = TRUE;\r
+ } else {\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
+#else\r
+ pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_mode2; /*for AP mode 2*/\r
+ pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_mode2;\r
+#endif\r
+ pDM_Odm->adaptivity_flag = FALSE;\r
+ pDM_Odm->Adaptivity_enable = FALSE;\r
+ }\r
+ Adaptivity->NHMWait = 0;\r
+ Adaptivity->bFirstLink = TRUE;\r
+ Adaptivity->bCheck = TRUE;\r
+ }\r
+\r
+ }\r
+\r
+\r
+}\r
+\r
+VOID\r
+Phydm_SearchPwdBLowerBound(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+ u4Byte value32 = 0;\r
+ u1Byte cnt, IGI_Pause = 0x7f, IGI_Resume = 0x20, IGI = 0x50; /*IGI = 0x50 for cal EDCCA lower bound*/\r
+ u1Byte txEdcca1 = 0, txEdcca0 = 0;\r
+ BOOLEAN bAdjust = TRUE;\r
+ s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;\r
+ s1Byte Diff;\r
+\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
+ ODM_Write_DIG(pDM_Odm, IGI_Pause);\r
+\r
+ Diff = IGI_target - (s1Byte)IGI;\r
+ TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
+ if (TH_L2H_dmc > 10)\r
+ TH_L2H_dmc = 10;\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
+ ODM_delay_ms(5);\r
+\r
+ while (bAdjust) {\r
+ for (cnt = 0; cnt < 250; cnt++) {\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
+ value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
+ value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord);\r
+#endif\r
+ if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8723B | ODM_RTL8188E)))\r
+ txEdcca1 = txEdcca1 + 1;\r
+ else if (value32 & BIT29)\r
+ txEdcca1 = txEdcca1 + 1;\r
+ else\r
+ txEdcca0 = txEdcca0 + 1;\r
+ }\r
+\r
+ if (txEdcca1 > 1) {\r
+ IGI = IGI - 1;\r
+ TH_L2H_dmc = TH_L2H_dmc + 1;\r
+ if (TH_L2H_dmc > 10)\r
+ TH_L2H_dmc = 10;\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
+ if (TH_L2H_dmc == 10) {\r
+ bAdjust = FALSE;\r
+ Adaptivity->H2L_lb = TH_H2L_dmc;\r
+ Adaptivity->L2H_lb = TH_L2H_dmc;\r
+ pDM_Odm->Adaptivity_IGI_upper = IGI;\r
+ }\r
+\r
+ txEdcca1 = 0;\r
+ txEdcca0 = 0;\r
+\r
+ } else {\r
+ bAdjust = FALSE;\r
+ Adaptivity->H2L_lb = TH_H2L_dmc;\r
+ Adaptivity->L2H_lb = TH_L2H_dmc;\r
+ pDM_Odm->Adaptivity_IGI_upper = IGI;\r
+ txEdcca1 = 0;\r
+ txEdcca0 = 0;\r
+ }\r
+ }\r
+\r
+ pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff;\r
+ Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff;\r
+ Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff;\r
+\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
+ ODM_Write_DIG(pDM_Odm, IGI_Resume);\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); /*resume to no link state*/\r
+}\r
+\r
+VOID\r
+Phydm_AdaptivityInit(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);\r
+ pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;\r
+ pDM_Odm->DCbackoff = (u1Byte)pMgntInfo->RegDCbackoff;\r
+ Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity;\r
+ Adaptivity->APNumTH = (u1Byte)pMgntInfo->RegAPNumTH;\r
+#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+ pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE;\r
+ pDM_Odm->DCbackoff = pDM_Odm->Adapter->registrypriv.adaptivity_dc_backoff;\r
+ Adaptivity->DynamicLinkAdaptivity = (pDM_Odm->Adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE;\r
+#endif\r
+\r
+#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
+\r
+ if (pDM_Odm->Carrier_Sense_enable == FALSE) {\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ if (pMgntInfo->RegL2HForAdaptivity != 0)\r
+ pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;\r
+ else\r
+#endif\r
+ {\r
+ pDM_Odm->TH_L2H_ini = 0xf5;\r
+ }\r
+ } else {\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ if (pMgntInfo->RegL2HForAdaptivity != 0)\r
+ pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;\r
+ else\r
+#endif\r
+ pDM_Odm->TH_L2H_ini = 0xa;\r
+ }\r
+\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ if (pMgntInfo->RegHLDiffForAdaptivity != 0)\r
+ pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity;\r
+ else\r
+#endif\r
+ pDM_Odm->TH_EDCCA_HL_diff = 7;\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));\r
+\r
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
+ prtl8192cd_priv priv = pDM_Odm->priv;\r
+\r
+ if (pDM_Odm->Carrier_Sense_enable) {\r
+ pDM_Odm->TH_L2H_ini = 0xa;\r
+ pDM_Odm->TH_EDCCA_HL_diff = 7;\r
+ } else {\r
+ pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; /*set by mib*/\r
+ pDM_Odm->TH_EDCCA_HL_diff = 7;\r
+ }\r
+\r
+ Adaptivity->TH_L2H_ini_mode2 = 20;\r
+ Adaptivity->TH_EDCCA_HL_diff_mode2 = 8;\r
+ Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;\r
+ if (priv->pshare->rf_ft_var.adaptivity_enable == 2)\r
+ Adaptivity->DynamicLinkAdaptivity = TRUE;\r
+ else\r
+ Adaptivity->DynamicLinkAdaptivity = FALSE;\r
+\r
+#endif\r
+\r
+ pDM_Odm->Adaptivity_IGI_upper = 0;\r
+ pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/\r
+ \r
+ Adaptivity->IGI_Base = 0x32;\r
+ Adaptivity->IGI_target = 0x1c;\r
+ Adaptivity->H2L_lb = 0;\r
+ Adaptivity->L2H_lb = 0;\r
+ Adaptivity->NHMWait = 0;\r
+ Adaptivity->bCheck = FALSE;\r
+ Adaptivity->bFirstLink = TRUE;\r
+\r
+ Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
+\r
+ /*Search pwdB lower bound*/\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);\r
+#endif\r
+\r
+#if (RTL8195A_SUPPORT == 1)\r
+ if (pDM_Odm->SupportICType & ODM_RTL8195A) {\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7); /*interfernce need > 2^x us, and then EDCCA will be 1*/\r
+ ODM_SetBBReg(pDM_Odm, DOM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
+ }\r
+#else\r
+ if (pDM_Odm->SupportICType & ODM_RTL8814A) { /*8814a no need to find pwdB lower bound, maybe*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7); /*interfernce need > 2^x us, and then EDCCA will be 1*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_POWER_CAL, BIT5, 1); /*0:mean, 1:max pwdB*/\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
+ } else\r
+ Phydm_SearchPwdBLowerBound(pDM_Odm);\r
+#endif\r
+\r
+}\r
+\r
+\r
+VOID\r
+Phydm_Adaptivity(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte IGI\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ s1Byte TH_L2H_dmc, TH_H2L_dmc;\r
+ s1Byte Diff, IGI_target;\r
+ PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ BOOLEAN bFwCurrentInPSMode = FALSE;\r
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);\r
+\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));\r
+\r
+ /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/\r
+ if (bFwCurrentInPSMode)\r
+ return;\r
+#endif\r
+\r
+ if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA()\n"));\r
+ /*Add by Neil Chen to enable edcca to MP Platform */\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ /*Adjust EDCCA.*/\r
+ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
+ Phydm_DynamicEDCCA(pDM_Odm);\r
+#endif\r
+ return;\r
+ }\r
+ \r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ if (Phydm_CheckChannelPlan(pDM_Odm))\r
+ return;\r
+ if (pDM_Odm->APTotalNum > Adaptivity->APNumTH)\r
+ return;\r
+#endif\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",\r
+ Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));\r
+#if (RTL8195A_SUPPORT == 0)\r
+ if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
+ /*fix AC series when enable EDCCA hang issue*/\r
+ ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/\r
+ ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/\r
+ }\r
+#endif\r
+ if (*pDM_Odm->pBandWidth == ODM_BW20M) /*CHANNEL_WIDTH_20*/\r
+ IGI_target = Adaptivity->IGI_Base;\r
+ else if (*pDM_Odm->pBandWidth == ODM_BW40M)\r
+ IGI_target = Adaptivity->IGI_Base + 2;\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else if (*pDM_Odm->pBandWidth == ODM_BW80M)\r
+ IGI_target = Adaptivity->IGI_Base + 2;\r
+#endif\r
+ else\r
+ IGI_target = Adaptivity->IGI_Base;\r
+ Adaptivity->IGI_target = (u1Byte) IGI_target;\r
+\r
+ if (*pDM_Odm->pChannel >= 149) { /*Band4 -> for AP : mode2*/\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
+ s1Byte L2H_nolink_Band4 = 0x7f, H2L_nolink_Band4 = 0x7f;\r
+ if (pDM_Odm->bLinked) {\r
+ if (pDM_Odm->SupportICType & ODM_RTL8814A) {\r
+ L2H_nolink_Band4 = (s1Byte)Adaptivity->TH_L2H_ini_mode2 + IGI_target;\r
+ H2L_nolink_Band4 = L2H_nolink_Band4 - Adaptivity->TH_EDCCA_HL_diff_mode2;\r
+ } else {\r
+ Diff = IGI_target - (s1Byte)IGI;\r
+ L2H_nolink_Band4 = Adaptivity->TH_L2H_ini_mode2 + Diff;\r
+ if (L2H_nolink_Band4 > 10)\r
+ L2H_nolink_Band4 = 10;\r
+ H2L_nolink_Band4 = L2H_nolink_Band4 - Adaptivity->TH_EDCCA_HL_diff_mode2;\r
+ }\r
+ } else {\r
+ L2H_nolink_Band4 = 0x7f;\r
+ H2L_nolink_Band4 = 0x7f;\r
+ }\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, H2L_nolink_Band4, L2H_nolink_Band4);\r
+ return;\r
+#endif\r
+ }\r
+\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d\n",\r
+ (*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity));\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, AdapIGIUpper= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",\r
+ pDM_Odm->RSSI_Min, pDM_Odm->Adaptivity_IGI_upper, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));\r
+\r
+ if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));\r
+ return;\r
+ }\r
+#if (!(DM_ODM_SUPPORT_TYPE & ODM_AP))\r
+ else if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (pDM_Odm->Adaptivity_enable == FALSE)) {\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) disable EDCCA, return!!\n"));\r
+ return;\r
+ }\r
+#endif\r
+\r
+ if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8195A)) {\r
+ TH_L2H_dmc = (s1Byte)pDM_Odm->TH_L2H_ini + IGI_target;\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+ }\r
+#if (RTL8195A_SUPPORT == 0)\r
+ else {\r
+ Diff = IGI_target - (s1Byte)IGI;\r
+ TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
+ if (TH_L2H_dmc > 10)\r
+ TH_L2H_dmc = 10;\r
+\r
+ TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
+\r
+ /*replace lower bound to prevent EDCCA always equal 1*/\r
+ if (TH_H2L_dmc < Adaptivity->H2L_lb)\r
+ TH_H2L_dmc = Adaptivity->H2L_lb;\r
+ if (TH_L2H_dmc < Adaptivity->L2H_lb)\r
+ TH_L2H_dmc = Adaptivity->L2H_lb;\r
+ }\r
+#endif\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));\r
+\r
+ Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
+ return;\r
+}\r
+\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+\r
+VOID\r
+Phydm_AdaptivityBSOD(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);\r
+ u1Byte count = 0;\r
+ u4Byte u4Value;\r
+\r
+ /*\r
+ 1. turn off RF (TRX Mux in standby mode)\r
+ 2. H2C mac id drop\r
+ 3. ignore EDCCA\r
+ 4. wait for clear FIFO\r
+ 5. don't ignore EDCCA\r
+ 6. turn on RF (TRX Mux in TRx mdoe)\r
+ 7. H2C mac id resume\r
+ */\r
+\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));\r
+\r
+ pAdapter->dropPktByMacIdCnt++;\r
+ pMgntInfo->bDropPktInProgress = TRUE;\r
+\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));\r
+\r
+#if 1\r
+\r
+ /*Standby mode*/\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
+ ODM_Write_DIG(pDM_Odm, 0x20);\r
+\r
+ /*H2C mac id drop*/\r
+ MacIdIndicateDisconnect(pAdapter);\r
+\r
+ /*Ignore EDCCA*/\r
+ Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
+\r
+ delay_ms(50);\r
+ count = 5;\r
+\r
+#else\r
+\r
+ do {\r
+\r
+ u8Byte diffTime, curTime, oldestTime;\r
+ u1Byte queueIdx\r
+\r
+ //3 Standby mode\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
+ ODM_Write_DIG(pDM_Odm, 0x20);\r
+\r
+ //3 H2C mac id drop\r
+ MacIdIndicateDisconnect(pAdapter);\r
+\r
+ //3 Ignore EDCCA\r
+ Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
+\r
+ count++;\r
+ delay_ms(10);\r
+\r
+ // Check latest packet\r
+ curTime = PlatformGetCurrentTime();\r
+ oldestTime = 0xFFFFFFFFFFFFFFFF;\r
+\r
+ for (queueIdx = 0; queueIdx < MAX_TX_QUEUE; queueIdx++) {\r
+ if (!IS_DATA_QUEUE(queueIdx))\r
+ continue;\r
+\r
+ if (!pAdapter->bTcbBusyQEmpty[queueIdx]) {\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("oldestTime = %llu\n", oldestTime));\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("Q[%d] = %llu\n", queueIdx, pAdapter->firstTcbSysTime[queueIdx]));\r
+ if (pAdapter->firstTcbSysTime[queueIdx] < oldestTime)\r
+ oldestTime = pAdapter->firstTcbSysTime[queueIdx];\r
+ }\r
+ }\r
+\r
+ diffTime = curTime - oldestTime;\r
+\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("diff s = %llu\n", (diffTime / 1000000)));\r
+\r
+ } while (((diffTime / 1000000) >= 4) && (oldestTime != 0xFFFFFFFFFFFFFFFF));\r
+#endif\r
+\r
+ /*Resume EDCCA*/\r
+ Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
+\r
+ /*Turn on TRx mode*/\r
+ Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
+ ODM_Write_DIG(pDM_Odm, 0x20);\r
+\r
+ /*Resume H2C macid*/\r
+ MacIdRecoverMediaStatus(pAdapter);\r
+\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));\r
+\r
+ pMgntInfo->bDropPktInProgress = FALSE;\r
+ RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));\r
+\r
+}\r
+\r
+VOID\r
+Phydm_EnableEDCCA(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+\r
+ /*This should be moved out of OUTSRC*/\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ /*Enable EDCCA. The value is suggested by SD3 Wilson.*/\r
+\r
+ /*Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.*/\r
+ if ((pDM_Odm->SupportICType == ODM_RTL8723A) && (IS_WIRELESS_MODE_G(pAdapter))) {\r
+ ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x00);\r
+ ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold + 2, 0xFD);\r
+ } else {\r
+ ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x03);\r
+ ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold + 2, 0x00);\r
+ }\r
+}\r
+\r
+VOID\r
+Phydm_DisableEDCCA(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);\r
+ ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold + 2, 0x7f);\r
+}\r
+\r
+VOID\r
+Phydm_DynamicEDCCA(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PADAPTER pAdapter = pDM_Odm->Adapter;\r
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
+ u1Byte RegC50, RegC58;\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
+ BOOLEAN bFwCurrentInPSMode = FALSE;\r
+\r
+ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));\r
+\r
+ /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/\r
+ if (bFwCurrentInPSMode)\r
+ return;\r
+#endif\r
+\r
+ /*2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA.*/\r
+ /*2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop*/\r
+ /*to send beacon in noisy environment or platform.*/\r
+\r
+ if (ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter))) {\r
+ ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n"));\r
+ Phydm_DisableEDCCA(pDM_Odm);\r
+ if (pHalData->bPreEdccaEnable)\r
+ Phydm_DisableEDCCA(pDM_Odm);\r
+ pHalData->bPreEdccaEnable = FALSE;\r
+ return;\r
+ }\r
+\r
+ RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);\r
+ RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);\r
+\r
+\r
+ if ((RegC50 > 0x28 && RegC58 > 0x28) ||\r
+ ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50 > 0x26)) ||\r
+ (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28)) {\r
+ if (!pHalData->bPreEdccaEnable) {\r
+ Phydm_EnableEDCCA(pDM_Odm);\r
+ pHalData->bPreEdccaEnable = TRUE;\r
+ }\r
+\r
+ } else if ((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25)) {\r
+ if (pHalData->bPreEdccaEnable) {\r
+ Phydm_DisableEDCCA(pDM_Odm);\r
+ pHalData->bPreEdccaEnable = FALSE;\r
+ }\r
+ }\r
+}\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
+ * \r
+ * This program is free software; you can redistribute it and/or modify it\r
+ * under the terms of version 2 of the GNU General Public License as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along with\r
+ * this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ \r
+#ifndef __PHYDMADAPTIVITY_H__\r
+#define __PHYDMADAPTIVITY_H__\r
+\r
+#define ADAPTIVITY_VERSION "8.5"\r
+\r
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
+typedef enum _tag_PhyDM_REGULATION_Type {\r
+ REGULATION_FCC = 0,\r
+ REGULATION_MKK = 1,\r
+ REGULATION_ETSI = 2,\r
+ REGULATION_WW = 3, \r
+ \r
+ MAX_REGULATION_NUM = 4\r
+} PhyDM_REGULATION_TYPE;\r
+#endif\r
+\r
+\r
+typedef enum tag_PhyDM_TRx_MUX_Type\r
+{\r
+ PhyDM_SHUTDOWN = 0,\r
+ PhyDM_STANDBY_MODE = 1,\r
+ PhyDM_TX_MODE = 2,\r
+ PhyDM_RX_MODE = 3\r
+}PhyDM_Trx_MUX_Type;\r
+\r
+typedef enum tag_PhyDM_MACEDCCA_Type\r
+{\r
+ PhyDM_IGNORE_EDCCA = 0,\r
+ PhyDM_DONT_IGNORE_EDCCA = 1\r
+}PhyDM_MACEDCCA_Type;\r
+\r
+typedef struct _ADAPTIVITY_STATISTICS {\r
+ s1Byte TH_L2H_ini_mode2;\r
+ s1Byte TH_EDCCA_HL_diff_mode2;\r
+ s1Byte TH_EDCCA_HL_diff_backup;\r
+ s1Byte IGI_Base;\r
+ u1Byte IGI_target;\r
+ u1Byte NHMWait;\r
+ s1Byte H2L_lb;\r
+ s1Byte L2H_lb;\r
+ BOOLEAN bFirstLink;\r
+ BOOLEAN bCheck;\r
+ BOOLEAN DynamicLinkAdaptivity;\r
+ u1Byte APNumTH;\r
+} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS;\r
+\r
+VOID\r
+Phydm_CheckAdaptivity(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID\r
+Phydm_CheckEnvironment(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID\r
+Phydm_NHMCounterStatisticsInit(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID\r
+Phydm_NHMCounterStatistics(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID\r
+Phydm_NHMCounterStatisticsReset(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+Phydm_GetNHMCounterStatistics(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+Phydm_MACEDCCAState(\r
+ IN PVOID pDM_VOID,\r
+ IN PhyDM_MACEDCCA_Type State\r
+);\r
+\r
+VOID\r
+Phydm_SetEDCCAThreshold(\r
+ IN PVOID pDM_VOID,\r
+ IN s1Byte H2L,\r
+ IN s1Byte L2H\r
+);\r
+\r
+VOID\r
+Phydm_SetTRxMux(\r
+ IN PVOID pDM_VOID,\r
+ IN PhyDM_Trx_MUX_Type txMode,\r
+ IN PhyDM_Trx_MUX_Type rxMode\r
+); \r
+\r
+BOOLEAN\r
+Phydm_CalNHMcnt(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+Phydm_SearchPwdBLowerBound(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID \r
+Phydm_AdaptivityInit(\r
+ IN PVOID pDM_VOID\r
+ );\r
+\r
+VOID\r
+Phydm_Adaptivity(\r
+ IN PVOID pDM_VOID,\r
+ IN u1Byte IGI\r
+ );\r
+\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+VOID\r
+Phydm_DisableEDCCA(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+Phydm_DynamicEDCCA(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+VOID\r
+Phydm_AdaptivityBSOD(\r
+ IN PVOID pDM_VOID\r
+);\r
+\r
+#endif\r
+\r
+\r
+#endif\r
IN PDM_ODM_T pDM_Odm
);
-VOID
-odm_AdaptivityInit(
- IN PDM_ODM_T pDM_Odm
-);
-
-VOID
-odm_Adaptivity(
- IN PDM_ODM_T pDM_Odm,
- IN u1Byte IGI
-);
//END---------------DIG---------------------------//
//START-------BB POWER SAVE-----------------------//
odm_CommonInfoSelfInit(pDM_Odm);
odm_CmnInfoInit_Debug(pDM_Odm);
odm_DIGInit(pDM_Odm);
- odm_AdaptivityInit(pDM_Odm);
+ Phydm_AdaptivityInit(pDM_Odm);
odm_RateAdaptiveMaskInit(pDM_Odm);
odm_RSSIMonitorInit(pDM_Odm);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
odm_DIGbyRSSI_LPS(pDM_Odm);
+ {
+ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
+ Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue);
+ }
+
}
else
//#endif
#endif
+
+ Phydm_CheckAdaptivity(pDM_Odm);
+
{
odm_DIG(pDM_Odm);
}
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
- odm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue);
+ Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue);
}
odm_CCKPacketDetectionThresh(pDM_Odm);
}
}
-
-VOID
-odm_AdaptivityInit(
-IN PDM_ODM_T pDM_Odm
-)
-{
- if(pDM_Odm->SupportICType == ODM_RTL8723B)
- {
- pDM_Odm->TH_L2H_ini = 0xf8; // -8
- }
- if((pDM_Odm->SupportICType == ODM_RTL8192E)&&(pDM_Odm->SupportInterface == ODM_ITRF_PCIE))
- {
- pDM_Odm->TH_L2H_ini = 0xf0; // -16
- }
- else
- {
- pDM_Odm->TH_L2H_ini = 0xf9; // -7
- }
-
- pDM_Odm->TH_EDCCA_HL_diff = 7;
- pDM_Odm->IGI_Base = 0x32;
- pDM_Odm->IGI_target = 0x1c;
- pDM_Odm->ForceEDCCA = 0;
- pDM_Odm->AdapEn_RSSI = 20;
-
- //Reg524[11]=0 is easily to transmit packets during adaptivity test
-
- //ODM_SetBBReg(pDM_Odm, 0x524, BIT11, 1);// stop counting if EDCCA is asserted
-}
-
// Add by Neil Chen to enable edcca to MP Platform
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#endif // end MP platform support
-VOID
-odm_Adaptivity(
- IN PDM_ODM_T pDM_Odm,
- IN u1Byte IGI
-)
-{
- s1Byte TH_L2H_dmc, TH_H2L_dmc;
- s1Byte Diff, IGI_target;
- BOOLEAN EDCCA_State = 0;
-
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PADAPTER pAdapter = pDM_Odm->Adapter;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- BOOLEAN bFwCurrentInPSMode=FALSE;
- PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
-
- pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
-
- // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
- if(bFwCurrentInPSMode)
- return;
-#endif
-
- if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY))
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
- // Add by Neil Chen to enable edcca to MP Platform
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- // Adjust EDCCA.
- if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- odm_DynamicEDCCA(pDM_Odm);
-#endif
- return;
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
- pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
-
- if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
-
- if((!pDM_Odm->bLinked)||(*pDM_Odm->pChannel > 149)) // Band4 doesn't need adaptivity
- {
- if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
- ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, 0x7f);
- ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, 0x7f);
- }
- else
- ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, (0x7f<<8) | 0x7f);
- return;
- }
-
-#if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
- if(pMgntInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
- ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0a);
- else
- ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0e);
-#endif
- if(!pDM_Odm->ForceEDCCA)
- {
- if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI)
- EDCCA_State = 1;
- else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))
- EDCCA_State = 0;
- }
- else
- EDCCA_State = 1;
- //if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (*pDM_Odm->pBandType == BAND_ON_5G))
- //IGI_target = pDM_Odm->IGI_Base;
- //else
- {
-
- if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20
- IGI_target = pDM_Odm->IGI_Base;
- else if(*pDM_Odm->pBandWidth == ODM_BW40M)
- IGI_target = pDM_Odm->IGI_Base + 2;
- else if(*pDM_Odm->pBandWidth == ODM_BW80M)
- IGI_target = pDM_Odm->IGI_Base + 6;
- else
- IGI_target = pDM_Odm->IGI_Base;
- }
-
- pDM_Odm->IGI_target = (u1Byte) IGI_target;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
- (*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State));
-
- if(EDCCA_State == 1)
- {
- Diff = IGI_target -(s1Byte)IGI;
- TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
- if(TH_L2H_dmc > 10) TH_L2H_dmc = 10;
- TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
- }
- else
- {
- TH_L2H_dmc = 0x7f;
- TH_H2L_dmc = 0x7f;
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n",
- IGI, TH_L2H_dmc, TH_H2L_dmc));
-
- if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
- ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
- ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
- }
- else
- ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc);
-}
-
VOID
ODM_DynamicATCSwitch_init(
IN PDM_ODM_T pDM_Odm
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x \n",
ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm)));
- if(pDM_DigTable->CurIGValue != CurrentIGI)//if(pDM_DigTable->PreIGValue != CurrentIGI)
+ //1 Check initial gain by upper bound
+ //if(!pDM_DigTable->bPSDInProgress)
{
- if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_WIN))
+ if(CurrentIGI > pDM_DigTable->rx_gain_range_max)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_TRACE, ("CurrentIGI(0x%02x) is larger than upper bound !!\n",CurrentIGI));
+ CurrentIGI = pDM_DigTable->rx_gain_range_max;
+ }
+ if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY && pDM_Odm->adaptivity_flag == TRUE)
+ {
+ if(CurrentIGI > pDM_Odm->Adaptivity_IGI_upper)
+ CurrentIGI = pDM_Odm->Adaptivity_IGI_upper;
+
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_DIG(): Adaptivity case: Force upper bound to 0x%x !!!!!!\n", CurrentIGI));
+ }
+ }
+
+ if(pDM_DigTable->CurIGValue != CurrentIGI)
+ {
+ //1 Set IGI value
+ if(pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE))
{
- ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
- if(pDM_Odm->RFType != ODM_1T1R)
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+
+ if(pDM_Odm->RFType > ODM_1T1R)
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+
+ if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R))
+ {
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
}
+ }
else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
{
switch(*(pDM_Odm->pOnePathCCA))
{
- case ODM_CCA_2R:
- ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
- if(pDM_Odm->RFType != ODM_1T1R)
- ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
- break;
- case ODM_CCA_1R_A:
- ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+ case ODM_CCA_2R:
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+
+ if(pDM_Odm->RFType > ODM_1T1R)
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+
+ if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R))
+ {
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+ }
+ break;
+ case ODM_CCA_1R_A:
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
if(pDM_Odm->RFType != ODM_1T1R)
- ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
- break;
- case ODM_CCA_1R_B:
- ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
+ break;
+ case ODM_CCA_1R_B:
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
if(pDM_Odm->RFType != ODM_1T1R)
- ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
+ ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
break;
- }
+ }
}
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI));
- //pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue;
pDM_DigTable->CurIGValue = CurrentIGI;
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x \n",CurrentIGI));
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI));
}
BOOLEAN FirstConnect, FirstDisConnect;
u1Byte dm_dig_max, dm_dig_min, offset;
u1Byte CurrentIGI = pDM_DigTable->CurIGValue;
- u1Byte Adap_IGI_Upper = pDM_Odm->IGI_target + 30 + (u1Byte) pDM_Odm->TH_L2H_ini -(u1Byte) pDM_Odm->TH_EDCCA_HL_diff;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
// This should be moved out of OUTSRC
return;
}
#endif
-/*
- if (pDM_Odm->SupportICType==ODM_RTL8723B)
- return;
-*/
if(pDM_Odm->bBtHsOperation)
{
return;
}
}
-
+
+ //1 Update status
+#if (RTL8192D_SUPPORT==1)
if(pDM_Odm->SupportICType == ODM_RTL8192D)
{
if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
if(*(pDM_Odm->pbMasterOfDMSP))
{
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
- FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
+ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
}
else
{
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
- FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
+ FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
}
}
}
}
else
+#endif
{
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
}
//1 Boundary Decision
- if(pDM_Odm->SupportICType & (ODM_RTL8192C) &&(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)))
+#if (RTL8192C_SUPPORT==1)
+ if((pDM_Odm->SupportICType & ODM_RTL8192C) && (pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)))
{
+ //2 High power case
if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
{
-
dm_dig_max = DM_DIG_MAX_AP_HP;
dm_dig_min = DM_DIG_MIN_AP_HP;
}
DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
}
else
+#endif
{
if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
{
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n"));
- //1 Check initial gain by upper/lower bound
- if(CurrentIGI > pDM_DigTable->rx_gain_range_max)
- CurrentIGI = pDM_DigTable->rx_gain_range_max;
+ //1 Check initial gain by upper/lower bound
if(CurrentIGI < pDM_DigTable->rx_gain_range_min)
CurrentIGI = pDM_DigTable->rx_gain_range_min;
-
- if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)
- {
- if(CurrentIGI > Adap_IGI_Upper)
- CurrentIGI = Adap_IGI_Upper;
-
- if(pDM_Odm->IGI_LowerBound != 0)
- {
- if(CurrentIGI < pDM_Odm->IGI_LowerBound)
- CurrentIGI = pDM_Odm->IGI_LowerBound;
- }
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_Odm->IGI_LowerBound = %d\n", pDM_Odm->IGI_LowerBound));
- }
+ if(CurrentIGI > pDM_DigTable->rx_gain_range_max)
+ CurrentIGI = pDM_DigTable->rx_gain_range_max;
+
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI));
- //2 High power RSSI threshold
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
- //PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
- // for LC issue to dymanic modify DIG lower bound----------LC Mocca Issue
- u8Byte curTxOkCnt=0, curRxOkCnt=0;
- static u8Byte lastTxOkCnt=0, lastRxOkCnt=0;
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x, TotalFA=%d\n\n", CurrentIGI, pFalseAlmCnt->Cnt_all));
- //u8Byte OKCntAll=0;
- //static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
- //u8Byte CurByteCnt=0, PreByteCnt=0;
-
- curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
- curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
- lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast;
- lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast;
- //----------------------------------------------------------end for LC Mocca issue
+ //1 High power RSSI threshold
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
if((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD))
{
// High power IGI lower bound
CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
}
}
- if((pDM_Odm->SupportICType & ODM_RTL8723A) &&
- IS_WIRELESS_MODE_G(pAdapter))
- {
- if(pHalData->UndecoratedSmoothedPWDB > 0x28)
- {
- if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND)
- {
- //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
- CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
- }
- }
- }
-#if 0
- if((pDM_Odm->SupportICType & ODM_RTL8723A)&&(pMgntInfo->CustomerID = RT_CID_LENOVO_CHINA))
+ if((pDM_Odm->SupportICType & ODM_RTL8723A) && IS_WIRELESS_MODE_G(pAdapter))
{
- OKCntAll = (curTxOkCnt+curRxOkCnt);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", CurrentIGI));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): OKCntAll(%#x)\n", OKCntAll));
- //8723AS_VAU
- if(pDM_Odm->SupportInterface==ODM_ITRF_USB)
+ if(pHalData->UndecoratedSmoothedPWDB > 0x28)
{
- if(pHalData->UndecoratedSmoothedPWDB < 12)
+ if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND)
{
- if(CurrentIGI > DM_DIG_MIN_NIC)
- {
- if(OKCntAll >= 1500000) // >=6Mbps
- CurrentIGI=0x1B;
- else if(OKCntAll >= 1000000) //4Mbps
- CurrentIGI=0x1A;
- else if(OKCntAll >= 500000) //2Mbps
- CurrentIGI=0x19;
- else if(OKCntAll >= 250000) //1Mbps
- CurrentIGI=0x18;
- else
- {
- CurrentIGI=0x17; //SCAN mode
- }
- }
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Modify---->CurIGValue(%#x)\n", CurrentIGI));
- }
- }
- }
-#endif
-}
+ //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
+ CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
+ }
+ }
+ }
#endif
-
+
+ //1 Update status
#if (RTL8192D_SUPPORT==1)
if(pDM_Odm->SupportICType == ODM_RTL8192D)
{
//sherry delete DualMacSmartConncurrent 20110517
if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
{
- ODM_Write_DIG_DMSP(pDM_Odm, (u1Byte)CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue);
+ ODM_Write_DIG_DMSP(pDM_Odm, CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue);
if(*(pDM_Odm->pbMasterOfDMSP))
{
pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
else
#endif
{
+#if ((DM_ODM_SUPPORT_TYPE & ODM_WIN) || ((DM_ODM_SUPPORT_TYPE & ODM_CE) && (ODM_CONFIG_BT_COEXIST == 1)))
if(pDM_Odm->bBtHsOperation)
{
if(pDM_Odm->bLinked)
{
if(pDM_DigTable->BT30_CurIGI > (CurrentIGI))
- {
ODM_Write_DIG(pDM_Odm, CurrentIGI);
-
- }
else
- {
ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);
- }
+
pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
}
else
{
if(pDM_Odm->bLinkInProcess)
- {
ODM_Write_DIG(pDM_Odm, 0x1c);
- }
else if(pDM_Odm->bBtConnectProcess)
- {
ODM_Write_DIG(pDM_Odm, 0x28);
- }
else
- {
ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
- }
}
- }
+ }
else // BT is not using
+#endif
{
ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
}
}
-
BOOLEAN
odm_DigAbort(
IN PDM_ODM_T pDM_Odm
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
+PVOID
+PhyDM_Get_Structure(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte Structure_Type
+)
+
+{
+ PVOID pStruct = NULL;
+#if RTL8195A_SUPPORT
+ switch (Structure_Type){
+ case PHYDM_FALSEALMCNT:
+ pStruct = &FalseAlmCnt;
+ break;
+
+ case PHYDM_CFOTRACK:
+ pStruct = &DM_CfoTrack;
+ break;
+
+ case PHYDM_ADAPTIVITY:
+ pStruct = &(pDM_Odm->Adaptivity);
+ break;
+
+ default:
+ break;
+ }
+
+#else
+ switch (Structure_Type){
+ case PHYDM_FALSEALMCNT:
+ pStruct = &(pDM_Odm->FalseAlmCnt);
+ break;
+
+ //case PHYDM_CFOTRACK:
+ // pStruct = &(pDM_Odm->DM_CfoTrack);
+ //break;
+
+ case PHYDM_ADAPTIVITY:
+ pStruct = &(pDM_Odm->Adaptivity);
+ break;
+
+ default:
+ break;
+ }
+
+#endif
+ return pStruct;
+}
+
#ifndef __HALDMOUTSRC_H__\r
#define __HALDMOUTSRC_H__\r
\r
+#include "PhyDM_Adaptivity.h"\r
+\r
//============================================================\r
// Definition \r
//============================================================\r
ODM_BB_RXHP = BIT12,\r
ODM_BB_ADAPTIVITY = BIT13,\r
ODM_BB_DYNAMIC_ATC = BIT14,\r
+ ODM_BB_NHM_CNT = BIT15,\r
+ ODM_BB_PRIMARY_CCA = BIT16,\r
+ ODM_BB_TXBF = BIT17,\r
\r
//\r
- // MAC DM section BIT 16-23\r
+ // MAC DM section BIT 20-23\r
//\r
- ODM_MAC_EDCA_TURBO = BIT16,\r
- ODM_MAC_EARLY_MODE = BIT17,\r
+ ODM_MAC_EDCA_TURBO = BIT20,\r
+ ODM_MAC_EARLY_MODE = BIT21,\r
\r
//\r
// RF ODM section BIT 24-31\r
// ODM_CMNINFO_IC_TYPE\r
typedef enum tag_ODM_Support_IC_Type_Definition\r
{\r
- ODM_RTL8192S = BIT0,\r
- ODM_RTL8192C = BIT1,\r
- ODM_RTL8192D = BIT2,\r
- ODM_RTL8723A = BIT3,\r
- ODM_RTL8188E = BIT4,\r
+ ODM_RTL8192S = BIT0,\r
+ ODM_RTL8192C = BIT1,\r
+ ODM_RTL8192D = BIT2,\r
+ ODM_RTL8723A = BIT3,\r
+ ODM_RTL8188E = BIT4,\r
ODM_RTL8812 = BIT5,\r
ODM_RTL8821 = BIT6,\r
- ODM_RTL8192E = BIT7, \r
+ ODM_RTL8192E = BIT7, \r
ODM_RTL8723B = BIT8,\r
- ODM_RTL8813A = BIT9, \r
- ODM_RTL8881A = BIT10\r
+ ODM_RTL8814A = BIT9, \r
+ ODM_RTL8881A = BIT10,\r
+ ODM_RTL8821B = BIT11,\r
+ ODM_RTL8822B = BIT12,\r
+ ODM_RTL8703B = BIT13,\r
+ ODM_RTL8195A = BIT14,\r
+ ODM_RTL8188F = BIT15\r
}ODM_IC_TYPE_E;\r
\r
#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)\r
-#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8813A|ODM_RTL8881A)\r
+#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A)\r
\r
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
#ifdef RTK_AC_SUPPORT\r
#define ODM_IC_11AC_SERIES_SUPPORT 1\r
#endif\r
\r
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
+#ifdef CONFIG_BT_COEXIST\r
+#define ODM_CONFIG_BT_COEXIST 1\r
+#else\r
+#define ODM_CONFIG_BT_COEXIST 0\r
+#endif\r
+#endif\r
+\r
//ODM_CMNINFO_CUT_VER\r
typedef enum tag_ODM_Cut_Version_Definition\r
{\r
BOOLEAN IsBbSwingOffsetPositiveA;\r
u4Byte BbSwingOffsetB;\r
BOOLEAN IsBbSwingOffsetPositiveB;\r
+\r
+ //For Adaptivtiy\r
+ u2Byte NHM_cnt_0;\r
+ u2Byte NHM_cnt_1;\r
s1Byte TH_L2H_ini;\r
s1Byte TH_EDCCA_HL_diff;\r
- s1Byte IGI_Base;\r
- u1Byte IGI_target;\r
- BOOLEAN ForceEDCCA;\r
- u1Byte AdapEn_RSSI;\r
- s1Byte Force_TH_H;\r
- s1Byte Force_TH_L;\r
- u1Byte IGI_LowerBound;\r
+ s1Byte TH_L2H_ini_backup;\r
+ BOOLEAN Carrier_Sense_enable;\r
+ u1Byte Adaptivity_IGI_upper;\r
+ BOOLEAN adaptivity_flag;\r
+ u1Byte DCbackoff;\r
+ BOOLEAN Adaptivity_enable;\r
+ u1Byte APTotalNum;\r
+ ADAPTIVITY_STATISTICS Adaptivity;\r
+ //For Adaptivtiy\r
+ \r
u1Byte antdiv_rssi;\r
u1Byte AntType;\r
u1Byte pre_AntType;\r
void odm_dtc(PDM_ODM_T pDM_Odm);\r
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */\r
\r
+typedef enum _PHYDM_STRUCTURE_TYPE{\r
+ PHYDM_FALSEALMCNT,\r
+ PHYDM_CFOTRACK,\r
+ PHYDM_ADAPTIVITY,\r
+ PHYDM_ROMINFO,\r
+ \r
+}PHYDM_STRUCTURE_TYPE;\r
+\r
+PVOID\r
+PhyDM_Get_Structure(\r
+ IN PDM_ODM_T pDM_Odm,\r
+ IN u1Byte Structure_Type\r
+);\r
+\r
#endif\r
\r
PSTA_INFO_T pEntry;\r
\r
\r
- if(pPktinfo->StationID == 0xFF)\r
+ if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM)\r
return;\r
\r
//\r
#endif\r
\r
#if (RTL8813A_SUPPORT == 1)\r
- if (pDM_Odm->SupportICType == ODM_RTL8813A)\r
+ if (pDM_Odm->SupportICType == ODM_RTL8814A)\r
{\r
/*\r
if(ConfigType == CONFIG_RF_TXPWR_LMT) {\r
}\r
#endif\r
#if (RTL8813A_SUPPORT == 1)\r
- if(pDM_Odm->SupportICType == ODM_RTL8813A)\r
+ if(pDM_Odm->SupportICType == ODM_RTL8814A)\r
{\r
\r
if(ConfigType == CONFIG_BB_PHY_REG)\r
//PAGE 8\r
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804\r
#define ODM_REG_BB_RX_PATH_11AC 0x808\r
+#define ODM_REG_BB_TX_PATH_11AC 0x80c\r
+#define ODM_REG_BB_ATC_11AC 0x860\r
+#define ODM_REG_EDCCA_POWER_CAL 0x8dc\r
+#define ODM_REG_DBG_RPT_11AC 0x8fc\r
//PAGE 9\r
+#define ODM_REG_EDCCA_DOWN_OPT 0x900\r
+#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944\r
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4\r
+#define ODM_REG_NHM_TIMER_11AC 0x990\r
+#define ODM_REG_NHM_TH9_TH10_11AC 0x994\r
+#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998\r
+#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c\r
+#define ODM_REG_NHM_TH8_11AC 0x9a0\r
+#define ODM_REG_NHM_9E8_11AC 0x9e8\r
//PAGE A\r
#define ODM_REG_CCK_CCA_11AC 0xA0A\r
#define ODM_REG_CCK_FA_RST_11AC 0xA2C\r
#define ODM_REG_CCK_FA_11AC 0xA5C\r
+//PAGE B\r
+#define ODM_REG_RST_RPT_11AC 0xB58\r
//PAGE C\r
+#define ODM_REG_TRMUX_11AC 0xC08\r
#define ODM_REG_IGI_A_11AC 0xC50\r
//PAGE E\r
#define ODM_REG_IGI_B_11AC 0xE50\r
+#define ODM_REG_TRMUX_11AC_B 0xE08\r
//PAGE F\r
+#define ODM_REG_CCK_CCA_CNT_11AC 0xF08\r
#define ODM_REG_OFDM_FA_11AC 0xF48\r
-\r
+#define ODM_REG_RPT_11AC 0xfa0\r
+#define ODM_REG_NHM_CNT_11AC 0xfa8\r
+//PAGE 18\r
+#define ODM_REG_IGI_C_11AC 0x1850\r
+//PAGE 1A\r
+#define ODM_REG_IGI_D_11AC 0x1A50\r
\r
//2 MAC REG LIST\r
#define ODM_REG_RESP_TX_11AC 0x6D8\r
#define ODM_BIT_IGI_11AC 0xFFFFFFFF\r
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16\r
#define ODM_BIT_BB_RX_PATH_11AC 0xF\r
+#define ODM_BIT_BB_TX_PATH_11AC 0xF\r
+#define ODM_BIT_BB_ATC_11AC BIT14\r
\r
#endif\r
\r
#define ODM_REG_TX_ANT_CTRL_11N 0x80C\r
#define ODM_REG_BB_PWR_SAV5_11N 0x818\r
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824\r
+#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C\r
#define ODM_REG_RX_DEFUALT_A_11N 0x858\r
#define ODM_REG_RX_DEFUALT_B_11N 0x85A\r
#define ODM_REG_BB_PWR_SAV3_11N 0x85C\r
#define ODM_REG_ANTSEL_PATH_11N 0x878\r
#define ODM_REG_BB_3WIRE_11N 0x88C\r
#define ODM_REG_SC_CNT_11N 0x8C4\r
-#define ODM_REG_PSD_DATA_11N 0x8B4\r
+#define ODM_REG_PSD_DATA_11N 0x8B4\r
+#define ODM_REG_PSD_DATA_11N 0x8B4\r
+#define ODM_REG_NHM_TIMER_11N 0x894\r
+#define ODM_REG_NHM_TH9_TH10_11N 0x890\r
+#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898\r
+#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c\r
+#define ODM_REG_NHM_CNT_11N 0x8d8\r
//PAGE 9\r
+#define ODM_REG_DBG_RPT_11N 0x908\r
+#define ODM_REG_BB_TX_PATH_11N 0x90c\r
#define ODM_REG_ANT_MAPPING1_11N 0x914\r
#define ODM_REG_ANT_MAPPING2_11N 0x918\r
+#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948\r
+\r
//PAGE A\r
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00\r
#define ODM_REG_CCK_CCA_11N 0xA0A\r
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0\r
//PAGE D\r
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00\r
+#define ODM_REG_BB_ATC_11N 0xD2C\r
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0\r
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4\r
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8\r
+#define ODM_REG_RPT_11N 0xDF4\r
//PAGE E\r
#define ODM_REG_TXAGC_A_6_18_11N 0xE00\r
#define ODM_REG_TXAGC_A_24_54_11N 0xE04\r
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14\r
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18\r
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C\r
+#define DOM_REG_EDCCA_DCNF_11N 0xE24\r
#define ODM_REG_FPGA0_IQK_11N 0xE28\r
#define ODM_REG_TXIQK_TONE_A_11N 0xE30\r
#define ODM_REG_RXIQK_TONE_A_11N 0xE34\r
#define ODM_REG_STANDBY_11N 0xEDC\r
#define ODM_REG_SLEEP_11N 0xEE0\r
#define ODM_REG_PMPD_ANAEN_11N 0xEEC\r
-\r
-\r
-\r
-\r
-\r
-\r
+#define ODM_REG_IGI_C_11N 0xF84\r
+#define ODM_REG_IGI_D_11N 0xF88\r
\r
//2 MAC REG LIST\r
#define ODM_REG_BB_RST_11N 0x02\r
#define ODM_BIT_IGI_11N 0x0000007F\r
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9\r
#define ODM_BIT_BB_RX_PATH_11N 0xF\r
+#define ODM_BIT_BB_TX_PATH_11N 0xF\r
+#define ODM_BIT_BB_ATC_11N BIT11\r
+\r
\r
#endif\r
\r
//\r
//-----------------------------------------------------------------------------\r
//BB Functions\r
-#define ODM_COMP_DIG BIT0 \r
-#define ODM_COMP_RA_MASK BIT1 \r
+#define ODM_COMP_DIG BIT0 \r
+#define ODM_COMP_RA_MASK BIT1 \r
#define ODM_COMP_DYNAMIC_TXPWR BIT2\r
#define ODM_COMP_FA_CNT BIT3\r
#define ODM_COMP_RSSI_MONITOR BIT4\r
#define ODM_COMP_CCK_PD BIT5\r
-#define ODM_COMP_ANT_DIV BIT6\r
+#define ODM_COMP_ANT_DIV BIT6\r
#define ODM_COMP_PWR_SAVE BIT7\r
#define ODM_COMP_PWR_TRAIN BIT8\r
#define ODM_COMP_RATE_ADAPTIVE BIT9\r
-#define ODM_COMP_PATH_DIV BIT10\r
-#define ODM_COMP_PSD BIT11\r
+#define ODM_COMP_PATH_DIV BIT10\r
+#define ODM_COMP_PSD BIT11\r
#define ODM_COMP_DYNAMIC_PRICCA BIT12\r
-#define ODM_COMP_RXHP BIT13 \r
+#define ODM_COMP_RXHP BIT13\r
#define ODM_COMP_MP BIT14\r
-#define ODM_COMP_DYNAMIC_ATC BIT15\r
+#define ODM_COMP_DYNAMIC_ATC BIT15\r
+#define ODM_COMP_ACS BIT16\r
+#define PHYDM_COMP_ADAPTIVITY BIT17\r
+#define PHYDM_COMP_RA_DBG BIT18\r
+#define PHYDM_COMP_TXBF BIT19\r
//MAC Functions\r
-#define ODM_COMP_EDCA_TURBO BIT16\r
-#define ODM_COMP_EARLY_MODE BIT17\r
+#define ODM_COMP_EDCA_TURBO BIT20\r
+#define ODM_COMP_EARLY_MODE BIT21\r
+#define ODM_FW_DEBUG_TRACE BIT22\r
//RF Functions\r
#define ODM_COMP_TX_PWR_TRACK BIT24\r
#define ODM_COMP_RX_GAIN_TRACK BIT25\r
-#define ODM_COMP_CALIBRATION BIT26\r
+#define ODM_COMP_CALIBRATION BIT26\r
//Common Functions\r
+#define BEAMFORMING_DEBUG BIT29\r
#define ODM_COMP_COMMON BIT30\r
-#define ODM_COMP_INIT BIT31\r
+#define ODM_COMP_INIT BIT31\r
\r
/*------------------------Export Marco Definition---------------------------*/\r
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
| ODM_BB_PWR_SAVE \r
| ODM_RF_CALIBRATION\r
| ODM_RF_TX_PWR_TRACK\r
-#ifdef CONFIG_ODM_ADAPTIVITY\r
- | ODM_BB_ADAPTIVITY\r
-#endif\r
;\r
\r
+ if (rtw_odm_adaptivity_needed(Adapter) == _TRUE)\r
+ pdmpriv->InitODMFlag |= ODM_BB_ADAPTIVITY;\r
+\r
if (!Adapter->registrypriv.qos_opt_enable) {\r
pdmpriv->InitODMFlag |= ODM_MAC_EDCA_TURBO;\r
}\r
ODM_PACKET_INFO_T pkt_info;
u8 *sa = NULL;
struct sta_priv *pstapriv;
- struct sta_info *psta;
+ struct sta_info *psta = NULL;
//_irqL irqL;
pkt_info.bPacketMatchBSSID =_FALSE;
}
*/
sa = get_ta(wlanhdr);
-
- pstapriv = &padapter->stapriv;
+
pkt_info.StationID = 0xFF;
- psta = rtw_get_stainfo(pstapriv, sa);
- if (psta)
- {
- pkt_info.StationID = psta->mac_id;
- //DBG_8192C("%s ==> StationID(%d)\n",__FUNCTION__,pkt_info.StationID);
- }
+
+ if (_rtw_memcmp(myid(&padapter->eeprompriv), sa, ETH_ALEN) == _TRUE) {
+ static u32 start_time = 0;
+
+ if ((start_time == 0) || (rtw_get_passing_time_ms(start_time) > 5000)) {
+ DBG_871X_LEVEL(_drv_always_, "Warning!!! %s: Confilc mac addr!!\n", __func__);
+ start_time = rtw_get_current_time();
+ }
+ } else {
+ pstapriv = &padapter->stapriv;
+ psta = rtw_get_stainfo(pstapriv, sa);
+ if (psta)
+ pkt_info.StationID = psta->mac_id;
+ }
+
pkt_info.DataRate = pattrib->data_rate;
//rtl8188e_query_rx_phy_status(precvframe, pphy_status);
rtw_skb_free(pskb);
break;
}
-
- recvbuf2recvframe(padapter, pskb);
-
-#ifdef CONFIG_PREALLOC_RECV_SKB
+ recvbuf2recvframe(padapter, pskb);
skb_reset_tail_pointer(pskb);
-
pskb->len = 0;
skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
-
-#else
- rtw_skb_free(pskb);
-#endif
-
- }
- while (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue)))
- {
- DBG_871X("dequeue_recvbuf %p\n", precvbuf);
- precvbuf->pskb = NULL;
- precvbuf->reuse = _FALSE;
- rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
+ if (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue))) {
+ precvbuf->pskb = NULL;
+ precvbuf->reuse = _FALSE;
+ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
+ }
}
-
}
//re-assign for linux based on skb
if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL))
{
+ #ifndef CONFIG_FIX_NR_BULKIN_BUFFER
precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
+ #endif
if(precvbuf->pskb == NULL)
{
- RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n"));
- DBG_8192C("#### usb_read_port() alloc_skb fail! precvbuf=%p #####\n", precvbuf);
+ if (0)
+ DBG_871X("usb_read_port() enqueue precvbuf=%p \n", precvbuf);
//enqueue precvbuf and wait for free skb
rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue);
return _FAIL;
#define PLATFORM_LINUX
-#define CONFIG_IOCTL_CFG80211
+//#define CONFIG_IOCTL_CFG80211
//#define CONFIG_IEEE80211W
#if defined(CONFIG_PLATFORM_ACTIONS_ATM702X)
#endif
#ifdef CONFIG_IOCTL_CFG80211
- #define RTW_USE_CFG80211_STA_EVENT /* Indecate new sta asoc through cfg80211_new_sta */
+ //#define RTW_USE_CFG80211_STA_EVENT /* Indecate new sta asoc through cfg80211_new_sta */
#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
//#define CONFIG_DEBUG_CFG80211
//#define CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2
#endif
- #define CONFIG_CONCURRENT_MODE
+ //#define CONFIG_CONCURRENT_MODE
#ifdef CONFIG_CONCURRENT_MODE
//#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri
#define CONFIG_RUNTIME_PORT_SWITCH
//#define CONFIG_DBG_P2P
#define CONFIG_P2P_PS
- #define CONFIG_P2P_IPS
+ //#define CONFIG_P2P_IPS
#define CONFIG_P2P_OP_CHK_SOCIAL_CH
#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT //replace CONFIG_P2P_CHK_INVITE_CH_LIST flag
#define CONFIG_P2P_INVITE_IOT
#define CONFIG_USB_RX_AGGREGATION
#endif
-#define CONFIG_PREALLOC_RECV_SKB
//#define CONFIG_REDUCE_USB_TX_INT // Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms.
//#define CONFIG_EASY_REPLACEMENT
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
-#undef CONFIG_PREALLOC_RECV_SKB
+
+#else
+ #define CONFIG_PREALLOC_RECV_SKB
+ #ifdef CONFIG_PREALLOC_RECV_SKB
+ //#define CONFIG_FIX_NR_BULKIN_BUFFER /* only use PREALLOC_RECV_SKB buffer, don't alloc skb at runtime */
+ #endif
#endif
/*
#define RTL8192E_SUPPORT 0
#define RTL8813A_SUPPORT 0
+#define RTL8195A_SUPPORT 0
+
//#if (RTL8188E_SUPPORT==1)
#define RATE_ADAPTIVE_SUPPORT 1
#define DYNAMIC_CAMID_ALLOC
+#define RTW_SCAN_SPARSE_MIRACAST 1
+#define RTW_SCAN_SPARSE_BG 0
+
#ifndef CONFIG_RTW_HIQ_FILTER
#define CONFIG_RTW_HIQ_FILTER 1
#endif
+#ifndef CONFIG_RTW_ADAPTIVITY_EN
+ #define CONFIG_RTW_ADAPTIVITY_EN 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_MODE
+ #define CONFIG_RTW_ADAPTIVITY_MODE 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_DML
+ #define CONFIG_RTW_ADAPTIVITY_DML 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF
+ #define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 2
+#endif
+
//#include <rtl871x_byteorder.h>
#endif // __DRV_CONF_H__
u8 qos_opt_enable;
u8 hiq_filter;
+
+ u8 adaptivity_en;
+ u8 adaptivity_mode;
+ u8 adaptivity_dml;
+ u8 adaptivity_dc_backoff;
+
};
#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv))
#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv)
+#define dvobj_to_regsty(dvobj) (&(dvobj->if1->registrypriv))
#ifdef PLATFORM_LINUX
static struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
\r
u8 bandroid_scan;\r
bool block;\r
+ bool block_scan;\r
bool power_mgmt;\r
\r
#ifdef CONFIG_CONCURRENT_MODE\r
return i;
}
+#define rtw_min(a, b) ((a>b)?b:a)
+
#ifndef MAC_FMT
#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
ANDROID_WIFI_CMD_P2P_GET_NOA,
ANDROID_WIFI_CMD_P2P_SET_PS,
ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE,
+
+ ANDROID_WIFI_CMD_MIRACAST,
+
#ifdef CONFIG_PNO_SUPPORT
ANDROID_WIFI_CMD_PNOSSIDCLR_SET,
ANDROID_WIFI_CMD_PNOSETUP_SET,
ANDROID_WIFI_CMD_MACADDR,
+ ANDROID_WIFI_CMD_BLOCK_SCAN,
ANDROID_WIFI_CMD_BLOCK,
ANDROID_WIFI_CMD_WFD_ENABLE,
u8 token; // Used to record the dialog token of p2p invitation request frame.
};
+#define MIRACAST_DISABLED 0
+#define MIRACAST_SOURCE 1
+#define MIRACAST_SINK 2
+#define MIRACAST_INVALID 3
+
+#define is_miracast_enabled(mode) \
+ (mode == MIRACAST_SOURCE || mode == MIRACAST_SINK)
+
+const char *get_miracast_mode_str(int mode);
+
#ifdef CONFIG_WFD
struct wifi_display_info{
// 0 -> WFD Source Device
// 1 -> WFD Primary Sink Device
enum SCAN_RESULT_TYPE scan_result_type; // Used when P2P is enable. This parameter will impact the scan result.
-
+ u8 stack_wfd_mode;
};
#endif //CONFIG_WFD
u8 restore_channel;
struct ieee80211_channel remain_on_ch_channel;
enum nl80211_channel_type remain_on_ch_type;
- u64 remain_on_ch_cookie;
- bool not_indic_ro_ch_exp;
+ ATOMIC_T ro_ch_cookie_gen;
+ u64 remain_on_ch_cookie;
bool is_ro_ch;
u32 last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */
};
extern void rtw_indicate_disconnect(_adapter* adapter);
extern void rtw_indicate_connect(_adapter* adapter);
void rtw_indicate_scan_done( _adapter *padapter, bool aborted);
+
+u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms);
+void rtw_scan_abort_no_wait(_adapter *adapter);
void rtw_scan_abort(_adapter *adapter);
extern int rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie,u8 *out_ie,uint in_len);
#if defined(CONFIG_STA_MODE_SCAN_UNDER_AP_MODE) || defined(CONFIG_ATMEL_RC_PATCH)
u8 scan_cnt;
+ u8 backop_cnt;
#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
};
void rtw_odm_ability_msg(void *sel, _adapter *adapter);
void rtw_odm_ability_set(_adapter *adapter, u32 ability);
+bool rtw_odm_adaptivity_needed(_adapter *adapter);
void rtw_odm_adaptivity_parm_msg(void *sel,_adapter *adapter);
-void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
- s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound);
+void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff);
void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter);
#endif // __RTW_ODM_H__
-#define DRIVERVERSION "v4.3.0.7_12758.20141114"
+#define DRIVERVERSION "v4.3.0.8_13522.20150213_beta"
#include <rtw_wifi_regd.h>\r
\r
#define RTW_MAX_MGMT_TX_CNT (8)\r
+#define RTW_MAX_MGMT_TX_MS_GAS (500)\r
\r
#define RTW_SCAN_IE_LEN_MAX 2304\r
#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 5000 //ms\r
struct cfg80211_ssid *ssids = request->ssids;\r
int social_channel = 0, j = 0;\r
bool need_indicate_scan_done = _FALSE;\r
+ bool ps_denied = _FALSE;\r
\r
_adapter *padapter;\r
struct rtw_wdev_priv *pwdev_priv;\r
pwdev_priv->scan_request = request;\r
_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);\r
\r
+ if (adapter_wdev_data(padapter)->block_scan == _TRUE) {\r
+ DBG_871X(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter));\r
+ need_indicate_scan_done = _TRUE;\r
+ goto check_need_indicate_scan_done;\r
+ }\r
+\r
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)\r
{\r
#ifdef CONFIG_DEBUG_CFG80211\r
}\r
\r
rtw_ps_deny(padapter, PS_DENY_SCAN);\r
+ ps_denied = _TRUE;\r
if(_FAIL == rtw_pwr_wakeup(padapter)) {\r
need_indicate_scan_done = _TRUE;\r
goto check_need_indicate_scan_done;\r
}\r
\r
cancel_ps_deny:\r
- rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);\r
+ if (ps_denied == _TRUE)\r
+ rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);\r
\r
exit:\r
return ret;\r
pstapriv->asoc_list_cnt--;\r
\r
//_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);\r
- updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING);\r
+ if (check_fwstate(pmlmepriv, (WIFI_AP_STATE)) == _TRUE)\r
+ updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID);\r
+ else\r
+ updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING);\r
//_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);\r
\r
psta = NULL;\r
\r
rtw_action_frame_parse(frame, frame_len, &category, &action);\r
\r
- DBG_8192C("RTW_Rx:cur_ch=%d\n", channel);\r
- if (msg)\r
- DBG_871X("RTW_Rx:%s\n", msg);\r
- else\r
- DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action);\r
+ if (action == ACT_PUBLIC_GAS_INITIAL_REQ) {\r
+ rtw_set_scan_deny(adapter, 200);\r
+ rtw_scan_abort_no_wait(adapter);\r
+ #ifdef CONFIG_CONCURRENT_MODE\r
+ if (rtw_buddy_adapter_up(adapter))\r
+ rtw_scan_abort_no_wait(adapter->pbuddy_adapter);\r
+ #endif\r
+ }\r
\r
if (channel <= RTW_CH_MAX_2G_CHANNEL)\r
freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);\r
cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);\r
#endif\r
\r
+ DBG_8192C("RTW_Rx:cur_ch=%d\n", channel);\r
+ if (msg)\r
+ DBG_871X("RTW_Rx:%s\n", msg);\r
+ else\r
+ DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action);\r
}\r
\r
#ifdef CONFIG_P2P\r
struct wifidirect_info *pwdinfo;\r
struct cfg80211_wifidirect_info *pcfg80211_wdinfo;\r
\r
+#ifndef CONFIG_RADIO_WORK\r
+ #define RTW_ROCH_DURATION_ENLARGE\r
+ #define RTW_ROCH_BACK_OP\r
+#endif\r
+\r
if (ndev == NULL) {\r
return -EINVAL;\r
}\r
pwdinfo = &padapter->wdinfo;\r
pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;\r
\r
- DBG_871X(FUNC_ADPT_FMT" ch:%u duration:%d\n", FUNC_ADPT_ARG(padapter), remain_ch, duration);\r
+ *cookie = ATOMIC_INC_RETURN(&pcfg80211_wdinfo->ro_ch_cookie_gen);\r
+\r
+ DBG_871X(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n", FUNC_ADPT_ARG(padapter), remain_ch, duration, *cookie);\r
\r
if(pcfg80211_wdinfo->is_ro_ch == _TRUE)\r
{\r
- pcfg80211_wdinfo->not_indic_ro_ch_exp = _TRUE;\r
DBG_8192C("%s, cancel ro ch timer\n", __func__);\r
_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);\r
#ifdef CONFIG_CONCURRENT_MODE\r
ATOMIC_SET(&pwdev_priv->ro_ch_to, 1);\r
#endif //CONFIG_CONCURRENT_MODE\r
p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK);\r
- pcfg80211_wdinfo->not_indic_ro_ch_exp = _FALSE;\r
}\r
\r
pcfg80211_wdinfo->is_ro_ch = _TRUE;\r
\r
\r
rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);\r
- \r
- \r
- if(duration < 400)\r
- duration = duration*3;//extend from exper.\r
\r
+ #ifdef RTW_ROCH_DURATION_ENLARGE\r
+ if (duration < 400)\r
+ duration = duration * 3; /* extend from exper */\r
+ #endif\r
\r
+#ifdef RTW_ROCH_BACK_OP\r
#ifdef CONFIG_CONCURRENT_MODE\r
if(check_buddy_fwstate(padapter, _FW_LINKED) &&\r
(duration<pwdinfo->ext_listen_interval)) \r
duration = duration + pwdinfo->ext_listen_interval;\r
}\r
#endif\r
+#endif /* RTW_ROCH_BACK_OP */\r
\r
pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter);\r
\r
}\r
\r
ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);\r
- \r
+\r
+ #ifdef RTW_ROCH_BACK_OP\r
DBG_8192C("%s, set switch ch timer, duration=%d\n", __func__, duration-pwdinfo->ext_listen_interval);\r
- _set_timer(&pwdinfo->ap_p2p_switch_timer, duration-pwdinfo->ext_listen_interval); \r
+ _set_timer(&pwdinfo->ap_p2p_switch_timer, duration-pwdinfo->ext_listen_interval);\r
+ #endif\r
} \r
}\r
\r
pwdinfo = &padapter->wdinfo;\r
pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;\r
\r
- DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));\r
+ DBG_871X(FUNC_ADPT_FMT" cookie:0x%llx\n", FUNC_ADPT_ARG(padapter), cookie);\r
\r
if (pcfg80211_wdinfo->is_ro_ch == _TRUE) {\r
- pcfg80211_wdinfo->not_indic_ro_ch_exp = _TRUE;\r
DBG_8192C("%s, cancel ro ch timer\n", __func__);\r
_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);\r
#ifdef CONFIG_CONCURRENT_MODE\r
ATOMIC_SET(&pwdev_priv->ro_ch_to, 1);\r
#endif\r
p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK);\r
- pcfg80211_wdinfo->not_indic_ro_ch_exp = _FALSE;\r
}\r
\r
#if 0\r
goto cancel_ps_deny;\r
}\r
\r
- do {\r
+ while (1) {\r
+ u32 sleep_ms = 0;\r
+ u32 retry_guarantee_ms = 0;\r
+\r
dump_cnt++;\r
tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, buf, len);\r
- } while (dump_cnt < dump_limit && tx_ret != _SUCCESS);\r
+\r
+ switch (action) {\r
+ case ACT_PUBLIC_GAS_INITIAL_REQ:\r
+ case ACT_PUBLIC_GAS_INITIAL_RSP:\r
+ sleep_ms = 50;\r
+ retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS;\r
+ }\r
+\r
+ if (tx_ret == _SUCCESS\r
+ || (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms))\r
+ break;\r
+\r
+ if (sleep_ms > 0)\r
+ rtw_msleep_os(sleep_ms);\r
+ }\r
\r
if (tx_ret != _SUCCESS || dump_cnt > 1) {\r
DBG_871X(FUNC_ADPT_FMT" %s (%d/%d) in %d ms\n", FUNC_ADPT_ARG(padapter),\r
\r
DBG_8192C("%s:rf_type=%d\n", __func__, rf_type);\r
\r
- /* if (padapter->registrypriv.wireless_mode & WIRELESS_11G) */\r
+ if (padapter->registrypriv.wireless_mode & WIRELESS_11G)\r
{\r
bands = wiphy->bands[IEEE80211_BAND_2GHZ];\r
if(bands)\r
rtw_cfg80211_init_ht_capab(&bands->ht_cap, IEEE80211_BAND_2GHZ, rf_type);\r
}\r
\r
- /* if (padapter->registrypriv.wireless_mode & WIRELESS_11A) */\r
+ if (padapter->registrypriv.wireless_mode & WIRELESS_11A)\r
{\r
bands = wiphy->bands[IEEE80211_BAND_5GHZ];\r
if(bands)\r
| BIT(NL80211_IFTYPE_ADHOC)\r
#ifdef CONFIG_AP_MODE\r
| BIT(NL80211_IFTYPE_AP)\r
+ #ifndef CONFIG_RADIO_WORK\r
| BIT(NL80211_IFTYPE_MONITOR)\r
+ #endif\r
#endif\r
#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE))\r
| BIT(NL80211_IFTYPE_P2P_CLIENT)\r
#endif \r
\r
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0))\r
+ #ifndef CONFIG_RADIO_WORK\r
wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR);\r
+ #endif\r
#endif\r
\r
/*\r
\r
/* if (padapter->registrypriv.wireless_mode & WIRELESS_11G) */\r
wiphy->bands[IEEE80211_BAND_2GHZ] = rtw_spt_band_alloc(IEEE80211_BAND_2GHZ);\r
+#ifdef CONFIG_IEEE80211_BAND_5GHZ\r
/* if (padapter->registrypriv.wireless_mode & WIRELESS_11A) */\r
wiphy->bands[IEEE80211_BAND_5GHZ] = rtw_spt_band_alloc(IEEE80211_BAND_5GHZ);\r
+#endif\r
\r
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) && LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0))\r
wiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS;\r
if(psta)
{
DBG_871X("rtw_add_sta(), free has been added psta=%p\n", psta);
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
rtw_free_stainfo(padapter, psta);
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
psta = NULL;
}
module_param(rtw_hiq_filter, uint, 0644);
MODULE_PARM_DESC(rtw_hiq_filter, "0:allow all, 1:allow special, 2:deny all");
+uint rtw_adaptivity_en = CONFIG_RTW_ADAPTIVITY_EN;
+module_param(rtw_adaptivity_en, uint, 0644);
+MODULE_PARM_DESC(rtw_adaptivity_en, "0:disable, 1:enable");
+
+uint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE;
+module_param(rtw_adaptivity_mode, uint, 0644);
+MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense");
+
+uint rtw_adaptivity_dml = CONFIG_RTW_ADAPTIVITY_DML;
+module_param(rtw_adaptivity_dml, uint, 0644);
+MODULE_PARM_DESC(rtw_adaptivity_dml, "0:disable, 1:enable");
+
+uint rtw_adaptivity_dc_backoff = CONFIG_RTW_ADAPTIVITY_DC_BACKOFF;
+module_param(rtw_adaptivity_dc_backoff, uint, 0644);
+MODULE_PARM_DESC(rtw_adaptivity_dc_backoff, "DC backoff for Adaptivity");
+
#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY) //eFuse: Regulatory selection=1
int rtw_tx_pwr_lmt_enable = 1;
int rtw_tx_pwr_by_rate = 1;
registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable;
registry_par->hiq_filter = (u8)rtw_hiq_filter;
+
+ registry_par->adaptivity_en = (u8)rtw_adaptivity_en;
+ registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode;
+ registry_par->adaptivity_dml = (u8)rtw_adaptivity_dml;
+ registry_par->adaptivity_dc_backoff = (u8)rtw_adaptivity_dc_backoff;
+
_func_exit_;
return status;
"P2P_GET_NOA",
"P2P_SET_PS",
"SET_AP_WPS_P2P_IE",
+
+ "MIRACAST",
+
#ifdef CONFIG_PNO_SUPPORT
"PNOSSIDCLR",
"PNOSETUP",
"MACADDR",
+ "BLOCK_SCAN",
"BLOCK",
"WFD-ENABLE",
"WFD-DISABLE",
return bytes_written;
}
+int rtw_android_set_block_scan(struct net_device *net, char *command, int total_len)
+{
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(net);
+ char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK_SCAN]) + 1;
+
+ #ifdef CONFIG_IOCTL_CFG80211
+ adapter_wdev_data(adapter)->block_scan = (*block_value == '0')?_FALSE:_TRUE;
+ #endif
+
+ return 0;
+}
+
int rtw_android_set_block(struct net_device *net, char *command, int total_len)
{
_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
return bytes_written;
}
+#ifdef CONFIG_WFD
+int rtw_android_set_miracast_mode(struct net_device *net, char *command, int total_len)
+{
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(net);
+ struct wifi_display_info *wfd_info = &adapter->wfd_info;
+ char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_MIRACAST]) + 1;
+ u8 mode;
+ int num;
+ int ret = _FAIL;
+
+ num = sscanf(arg, "%hhu", &mode);
+
+ if (num >= 1) {
+ wfd_info->stack_wfd_mode = mode;
+ DBG_871X("Miracast mode: %s(%u)\n", get_miracast_mode_str(wfd_info->stack_wfd_mode), wfd_info->stack_wfd_mode);
+ ret = _SUCCESS;
+ }
+
+ return (ret == _SUCCESS)?0:-1;
+}
+#endif /* CONFIG_WFD */
+
int get_int_from_command( char* pcmd )
{
int i = 0;
case ANDROID_WIFI_CMD_MACADDR:
bytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len);
break;
-
+
+ case ANDROID_WIFI_CMD_BLOCK_SCAN:
+ bytes_written = rtw_android_set_block_scan(net, command, priv_cmd.total_len);
+ break;
+
case ANDROID_WIFI_CMD_BLOCK:
bytes_written = rtw_android_set_block(net, command, priv_cmd.total_len);
break;
case ANDROID_WIFI_CMD_GETBAND:
bytes_written = rtw_android_getband(net, command, priv_cmd.total_len);
break;
-
+
case ANDROID_WIFI_CMD_COUNTRY:
bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len);
break;
#endif //CONFIG_IOCTL_CFG80211
#ifdef CONFIG_WFD
+
+ case ANDROID_WIFI_CMD_MIRACAST:
+ bytes_written = rtw_android_set_miracast_mode(net, command, priv_cmd.total_len);
+ break;
+
case ANDROID_WIFI_CMD_WFD_ENABLE:
{
// Commented by Albert 2012/07/24
char tmp[32];
u32 TH_L2H_ini;
s8 TH_EDCCA_HL_diff;
- u32 IGI_Base;
- int ForceEDCCA;
- u8 AdapEn_RSSI;
- u8 IGI_LowerBound;
if (count < 1)
return -EFAULT;
if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
- int num = sscanf(tmp, "%x %hhd %x %d %hhu %hhu",
- &TH_L2H_ini, &TH_EDCCA_HL_diff, &IGI_Base, &ForceEDCCA, &AdapEn_RSSI, &IGI_LowerBound);
+ int num = sscanf(tmp, "%x %hhd", &TH_L2H_ini, &TH_EDCCA_HL_diff);
- if (num != 6)
+ if (num != 2)
return count;
- rtw_odm_adaptivity_parm_set(padapter, (s8)TH_L2H_ini, TH_EDCCA_HL_diff, (s8)IGI_Base, (bool)ForceEDCCA, AdapEn_RSSI, IGI_LowerBound);
+ rtw_odm_adaptivity_parm_set(padapter, (s8)TH_L2H_ini, TH_EDCCA_HL_diff);
}
return count;
/*
* Broadcom BCM4319 driver version.
*/
-#define RTL8192_DRV_VERSION "3.80.WFD"
+#define RTL8192_DRV_VERSION "3.80.WFD.beta"
#endif /* WIFI_VERSION_H */
projects / firefly-linux-kernel-4.4.55.git / commitdiff