change gpu clk name aclk_gpu to clk_gpu.
Change-Id: I0ee1fc47b94d7459914c6040aa3bcfc616626a83
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
#address-cells = <1>;
#size-cells = <1>;
- aclk_gpu_div: aclk_gpu_div {
+ clk_gpu_div: clk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
- clocks = <&aclk_gpu>;
- clock-output-names = "aclk_gpu";
+ clocks = <&clk_gpu>;
+ clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
};
- aclk_gpu: aclk_gpu_mux {
+ clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <5 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
- clock-output-names = "aclk_gpu";
+ clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
testclk: testclk_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 4>;
- clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&aclk_gpu>, <&aclk_peri>, <&aclk_core>;
+ clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&clk_gpu>, <&aclk_peri>, <&aclk_core>;
clock-output-names = "testclk";
#clock-cells = <0>;
#clock-init-cells = <1>;
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
- <&aclk_gpu>, <&aclk_gpu>;
+ <&clk_gpu>, <&clk_gpu>;
clock-output-names =
"clk_ddrphy", "clk4x_ddrphy",
rockchip,clocks-init-parent =
<&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
<&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
- <&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
+ <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
<&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
<&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
<&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
<&aclk_peri 250000000>, <&hclk_peri 125000000>,
<&pclk_peri 62500000>, <&clk_mac 125000000>,
<&aclk_iep 250000000>, <&hclk_vio 125000000>,
- <&aclk_rga 250000000>, <&aclk_gpu 250000000>,
+ <&aclk_rga 250000000>, <&clk_gpu 250000000>,
<&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
<&clk_vdec_cabac 250000000>;
/*
rockchip,clocks-init-parent =
<&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
<&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
- <&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
+ <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
<&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
<&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
<&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
<&aclk_peri 250000000>, <&hclk_peri 125000000>,
<&pclk_peri 62500000>, <&clk_mac 125000000>,
<&aclk_iep 250000000>, <&hclk_vio 125000000>,
- <&aclk_rga 250000000>, <&aclk_gpu 250000000>,
+ <&aclk_rga 250000000>, <&clk_gpu 250000000>,
<&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
<&clk_vdec_cabac 250000000>;
/*