ARM: dts: rk3228: clk: rename gpu clk name
authorzhangqing <zhangqing@rock-chips.com>
Wed, 14 Oct 2015 15:42:16 +0000 (08:42 -0700)
committerGerrit Code Review <gerrit@rock-chips.com>
Wed, 14 Oct 2015 08:27:54 +0000 (16:27 +0800)
change gpu clk name aclk_gpu to clk_gpu.

Change-Id: I0ee1fc47b94d7459914c6040aa3bcfc616626a83
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
arch/arm/boot/dts/rk3228-clocks.dtsi
arch/arm/boot/dts/rk3228-fpga.dts
arch/arm/boot/dts/rk3228.dtsi

index b8da26ea235e2d446dbf8421f15a1e39aea2747b..e874a3f87a764a576d9b9b235226ac644551d828 100644 (file)
                                        #address-cells = <1>;
                                        #size-cells = <1>;
 
-                                       aclk_gpu_div: aclk_gpu_div {
+                                       clk_gpu_div: clk_gpu_div {
                                                compatible = "rockchip,rk3188-div-con";
                                                rockchip,bits = <0 5>;
-                                               clocks = <&aclk_gpu>;
-                                               clock-output-names = "aclk_gpu";
+                                               clocks = <&clk_gpu>;
+                                               clock-output-names = "clk_gpu";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
                                        };
 
-                                       aclk_gpu: aclk_gpu_mux {
+                                       clk_gpu: clk_gpu_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <5 2>;
                                                clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
-                                               clock-output-names = "aclk_gpu";
+                                               clock-output-names = "clk_gpu";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
                                        };
                                         testclk: testclk_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <8 4>;
-                                               clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&aclk_gpu>, <&aclk_peri>, <&aclk_core>;
+                                               clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&clk_gpu>, <&aclk_peri>, <&aclk_core>;
                                                clock-output-names = "testclk";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;
                                        <&dummy>,       <&dummy>,
 
                                        <&dummy>,       <&dummy>,
-                                       <&aclk_gpu>,    <&aclk_gpu>;
+                                       <&clk_gpu>,     <&clk_gpu>;
 
                                        clock-output-names =
                                        "clk_ddrphy",   "clk4x_ddrphy",
index a91a869a4a83490b4ec01d1b536a303fed6296af..51eee57cb2ba5b734647f56a22f6fa4ebb9444b2 100644 (file)
                rockchip,clocks-init-parent =
                        <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
                        <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
-                       <&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
+                       <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
                        <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
                        <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
                        <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
                        <&aclk_peri 250000000>, <&hclk_peri 125000000>,
                        <&pclk_peri 62500000>, <&clk_mac 125000000>,
                        <&aclk_iep 250000000>, <&hclk_vio 125000000>,
-                       <&aclk_rga 250000000>, <&aclk_gpu 250000000>,
+                       <&aclk_rga 250000000>, <&clk_gpu 250000000>,
                        <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
                        <&clk_vdec_cabac 250000000>;
 /*
index b59ee5925449767573b4ab1efd2b7e32c5cf655f..1c36a651207eb29b68bb86f24d9a8a85add77c7b 100644 (file)
@@ -90,7 +90,7 @@
                rockchip,clocks-init-parent =
                        <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
                        <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
-                       <&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
+                       <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
                        <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
                        <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
                        <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
                        <&aclk_peri 250000000>, <&hclk_peri 125000000>,
                        <&pclk_peri 62500000>, <&clk_mac 125000000>,
                        <&aclk_iep 250000000>, <&hclk_vio 125000000>,
-                       <&aclk_rga 250000000>, <&aclk_gpu 250000000>,
+                       <&aclk_rga 250000000>, <&clk_gpu 250000000>,
                        <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
                        <&clk_vdec_cabac 250000000>;
 /*