ath5k: Fix reset sequence for AR5212 in general and RF5111 in particular
authorElias Oltmanns <eo@nebensachen.de>
Wed, 29 Oct 2008 13:25:42 +0000 (14:25 +0100)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 29 Oct 2008 21:54:35 +0000 (17:54 -0400)
Take care to handle register 0xa228 exactly as in the HAL released by
Atheros. This change is required to make ath5k work again on my system
since commit 2203d6be (ath5k: Misc hw_reset updates), thus fixing a
regression in 2.6.27 and therefore hopefully eligible for inclusion into
a stable release.

v2: Only overwrite initial register values on later revisions of AR5212
    chips.
v3: Use standard macros to manipulate the register.

Signed-off-by: Elias Oltmanns <eo@nebensachen.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath5k/initvals.c
drivers/net/wireless/ath5k/reset.c

index ea2e1a20b499d9cb696c7b1ea57c450d428f3f74..ceaa6c475c0615bb786cf52bb7c0f1838ee557c9 100644 (file)
@@ -806,6 +806,8 @@ static const struct ath5k_ini_mode ar5212_rf5111_ini_mode_end[] = {
                { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
        { AR5K_PHY(642),
                { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+       { 0xa228,
+               { 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } },
        { 0xa23c,
                { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
 };
index 8f1886834e61fba8fe2bd5a7554b978b68717dd0..1b6d45b6772db39c269752e1b5bbef4e328d6389 100644 (file)
@@ -537,9 +537,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                mdelay(1);
 
                /*
-                * Write some more initial register settings
+                * Write some more initial register settings for revised chips
                 */
-               if (ah->ah_version == AR5K_AR5212) {
+               if (ah->ah_version == AR5K_AR5212 &&
+                   ah->ah_phy_revision > 0x41) {
                        ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
 
                        if (channel->hw_value == CHANNEL_G)
@@ -558,19 +559,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                        else
                                ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
 
-                       /* Some bits are disabled here, we know nothing about
-                        * register 0xa228 yet, most of the times this ends up
-                        * with a value 0x9b5 -haven't seen any dump with
-                        * a different value- */
-                       /* Got this from decompiling binary HAL */
-                       data = ath5k_hw_reg_read(ah, 0xa228);
-                       data &= 0xfffffdff;
-                       ath5k_hw_reg_write(ah, data, 0xa228);
-
-                       data = ath5k_hw_reg_read(ah, 0xa228);
-                       data &= 0xfffe03ff;
-                       ath5k_hw_reg_write(ah, data, 0xa228);
-                       data = 0;
+                       /* Got this from legacy-hal */
+                       AR5K_REG_DISABLE_BITS(ah, 0xa228, 0x200);
+
+                       AR5K_REG_MASKED_BITS(ah, 0xa228, 0x800, 0xfffe03ff);
 
                        /* Just write 0x9b5 ? */
                        /* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */