Removing some unused instruction definitions from the Hexagon backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168388 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 84354403084de11d2f2f85f84d5a8b76dcf7d93d..c9e0025453be3f155e1570a3197de9ba1f3b3672 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -941,42 +941,36 @@ unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
     case Hexagon::TFR_FI:
         return Hexagon::TFR_FI_immext_V4;
 
-    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
     case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
     case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
     case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
     case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
     case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
     case Hexagon::MEMw_ORr_indexed_MEM_V4 :
-    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
     case Hexagon::MEMw_ADDi_MEM_V4 :
     case Hexagon::MEMw_SUBi_MEM_V4 :
     case Hexagon::MEMw_ADDr_MEM_V4 :
     case Hexagon::MEMw_SUBr_MEM_V4 :
     case Hexagon::MEMw_ANDr_MEM_V4 :
     case Hexagon::MEMw_ORr_MEM_V4 :
-    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
     case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
     case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
     case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
     case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
     case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
     case Hexagon::MEMh_ORr_indexed_MEM_V4 :
-    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
     case Hexagon::MEMh_ADDi_MEM_V4 :
     case Hexagon::MEMh_SUBi_MEM_V4 :
     case Hexagon::MEMh_ADDr_MEM_V4 :
     case Hexagon::MEMh_SUBr_MEM_V4 :
     case Hexagon::MEMh_ANDr_MEM_V4 :
     case Hexagon::MEMh_ORr_MEM_V4 :
-    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
     case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
     case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
     case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
     case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
     case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
     case Hexagon::MEMb_ORr_indexed_MEM_V4 :
-    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
     case Hexagon::MEMb_ADDi_MEM_V4 :
     case Hexagon::MEMb_SUBi_MEM_V4 :
     case Hexagon::MEMb_ADDr_MEM_V4 :
@@ -2391,14 +2385,12 @@ isValidOffset(const int Opcode, const int Offset) const {
     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
       (Offset <= Hexagon_ADDI_OFFSET_MAX);
 
-  case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
   case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
   case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
   case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
   case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
   case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
   case Hexagon::MEMw_ORr_indexed_MEM_V4 :
-  case Hexagon::MEMw_ADDSUBi_MEM_V4 :
   case Hexagon::MEMw_ADDi_MEM_V4 :
   case Hexagon::MEMw_SUBi_MEM_V4 :
   case Hexagon::MEMw_ADDr_MEM_V4 :
@@ -2408,14 +2400,12 @@ isValidOffset(const int Opcode, const int Offset) const {
     assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
     return (0 <= Offset && Offset <= 255);
 
-  case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
   case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
   case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
   case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
   case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
   case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
   case Hexagon::MEMh_ORr_indexed_MEM_V4 :
-  case Hexagon::MEMh_ADDSUBi_MEM_V4 :
   case Hexagon::MEMh_ADDi_MEM_V4 :
   case Hexagon::MEMh_SUBi_MEM_V4 :
   case Hexagon::MEMh_ADDr_MEM_V4 :
@@ -2425,14 +2415,12 @@ isValidOffset(const int Opcode, const int Offset) const {
     assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
     return (0 <= Offset && Offset <= 127);
 
-  case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
   case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
   case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
   case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
   case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
   case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
   case Hexagon::MEMb_ORr_indexed_MEM_V4 :
-  case Hexagon::MEMb_ADDSUBi_MEM_V4 :
   case Hexagon::MEMb_ADDi_MEM_V4 :
   case Hexagon::MEMb_SUBi_MEM_V4 :
   case Hexagon::MEMb_ADDr_MEM_V4 :
@@ -2491,42 +2479,36 @@ isMemOp(const MachineInstr *MI) const {
   switch (MI->getOpcode())
   {
     default: return false;
-    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
     case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
     case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
     case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
     case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
     case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
     case Hexagon::MEMw_ORr_indexed_MEM_V4 :
-    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
     case Hexagon::MEMw_ADDi_MEM_V4 :
     case Hexagon::MEMw_SUBi_MEM_V4 :
     case Hexagon::MEMw_ADDr_MEM_V4 :
     case Hexagon::MEMw_SUBr_MEM_V4 :
     case Hexagon::MEMw_ANDr_MEM_V4 :
     case Hexagon::MEMw_ORr_MEM_V4 :
-    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
     case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
     case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
     case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
     case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
     case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
     case Hexagon::MEMh_ORr_indexed_MEM_V4 :
-    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
     case Hexagon::MEMh_ADDi_MEM_V4 :
     case Hexagon::MEMh_SUBi_MEM_V4 :
     case Hexagon::MEMh_ADDr_MEM_V4 :
     case Hexagon::MEMh_SUBr_MEM_V4 :
     case Hexagon::MEMh_ANDr_MEM_V4 :
     case Hexagon::MEMh_ORr_MEM_V4 :
-    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
     case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
     case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
     case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
     case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
     case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
     case Hexagon::MEMb_ORr_indexed_MEM_V4 :
-    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
     case Hexagon::MEMb_ADDi_MEM_V4 :
     case Hexagon::MEMb_SUBi_MEM_V4 :
     case Hexagon::MEMb_ADDr_MEM_V4 :

diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td
index a610168e343908517115120ae5d6029d64d87890..b40fc418c172e8424af6174bcb51df8030a6377a 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfoV4.td
+++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td
@@ -4417,18 +4417,6 @@ def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
 //===----------------------------------------------------------------------===//
 
 
-// MEMw_ADDSUBi_indexed_V4:
-//   pseudo operation for MEMw_ADDi_indexed_V4 and
-//   MEMw_SUBi_indexed_V4 a later pass will change it
-//   to the corresponding pattern.
-let AddedComplexity = 30 in
-def MEMw_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_2Imm:$offset, m6Imm:$addend),
-            "Error; should not emit",
-            [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
-                         m6ImmPred:$addend),
-                    (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
-            Requires<[HasV4T, UseMEMOP]>;
 
 // memw(Rs+#u6:2) += #U5
 let AddedComplexity = 30 in
@@ -4486,17 +4474,6 @@ def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
             Requires<[HasV4T, UseMEMOP]>;
 
-// MEMw_ADDSUBi_V4:
-//   Pseudo operation for MEMw_ADDi_V4 and MEMw_SUBi_V4
-//   a later pass will change it to the right pattern.
-let AddedComplexity = 30 in
-def MEMw_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
-            (ins MEMri:$addr, m6Imm:$addend),
-            "Error; should not emit",
-            [(store (add (load ADDRriU6_2:$addr), m6ImmPred:$addend),
-                    ADDRriU6_2:$addr)]>,
-            Requires<[HasV4T, UseMEMOP]>;
-
 // memw(Rs+#u6:2) += #U5
 let AddedComplexity = 30 in
 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
@@ -4574,20 +4551,6 @@ def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
 //===----------------------------------------------------------------------===//
 
 
-// MEMh_ADDSUBi_indexed_V4:
-//   Pseudo operation for MEMh_ADDi_indexed_V4 and
-//   MEMh_SUBi_indexed_V4 a later pass will change it
-//   to the corresponding pattern.
-let AddedComplexity = 30 in
-def MEMh_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_1Imm:$offset, m6Imm:$addend),
-            "Error; should not emit",
-            [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
-                                                   u6_1ImmPred:$offset)),
-                                 m6ImmPred:$addend),
-                            (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
-            Requires<[HasV4T, UseMEMOP]>;
-
 // memh(Rs+#u6:1) += #U5
 let AddedComplexity = 30 in
 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
@@ -4648,17 +4611,6 @@ def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
             Requires<[HasV4T, UseMEMOP]>;
 
-// MEMh_ADDSUBi_V4:
-//   Pseudo operation for MEMh_ADDi_V4 and MEMh_SUBi_V4
-//   a later pass will change it to the right pattern.
-let AddedComplexity = 30 in
-def MEMh_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
-            (ins MEMri:$addr, m6Imm:$addend),
-            "Error; should not emit",
-            [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
-                                 m6ImmPred:$addend), ADDRriU6_1:$addr)]>,
-            Requires<[HasV4T, UseMEMOP]>;
-
 // memh(Rs+#u6:1) += #U5
 let AddedComplexity = 30 in
 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
@@ -4736,21 +4688,6 @@ def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
 //     MEMb_SETi_V4          : memb(Rs+#u6:0)=setbit(#U5)
 //===----------------------------------------------------------------------===//
 
-
-// MEMb_ADDSUBi_indexed_V4:
-//   Pseudo operation for MEMb_ADDi_indexed_V4 and
-//   MEMb_SUBi_indexed_V4 a later pass will change it
-//   to the corresponding pattern.
-let AddedComplexity = 30 in
-def MEMb_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
-            (ins IntRegs:$base, u6_0Imm:$offset, m6Imm:$addend),
-            "Error; should not emit",
-            [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
-                                                 u6_0ImmPred:$offset)),
-                                m6ImmPred:$addend),
-                           (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
-            Requires<[HasV4T, UseMEMOP]>;
-
 // memb(Rs+#u6:0) += #U5
 let AddedComplexity = 30 in
 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
@@ -4811,17 +4748,6 @@ def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
             Requires<[HasV4T, UseMEMOP]>;
 
-// MEMb_ADDSUBi_V4:
-//   Pseudo operation for MEMb_ADDi_V4 and MEMb_SUBi_V4
-//   a later pass will change it to the right pattern.
-let AddedComplexity = 30 in
-def MEMb_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
-            (ins MEMri:$addr, m6Imm:$addend),
-            "Error; should not emit",
-            [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
-                                m6ImmPred:$addend), ADDRriU6_0:$addr)]>,
-            Requires<[HasV4T, UseMEMOP]>;
-
 // memb(Rs+#u6:0) += #U5
 let AddedComplexity = 30 in
 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),