Remove no-longer-correct special case for disasm of ARM BL instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127517 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp
index 2ebfb2e477babac8aa9fbd04210bba634019415a..09243e116b3b2f32d43b2bfdb0edf128b6a61ec7 100644 (file)
--- a/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/utils/TableGen/ARMDecoderEmitter.cpp
@@ -1592,11 +1592,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
     // better off using the generic RSCri and RSCrs instructions.
     if (Name == "RSCSri" || Name == "RSCSrs") return false;
 
-    // Ignore the non-Darwin BL instructions and the TPsoft (TLS) instruction.
-    if (Name == "BL" || Name == "BL_pred" || Name == "BLX" ||
-        Name == "BLX_pred" || Name == "TPsoft")
-      return false;
-
     // A8-598: VEXT
     // Vector Extract extracts elements from the bottom end of the second
     // operand vector and the top end of the first, concatenates them and