*/
#include <linux/kernel.h>
+#include <linux/init.h>
#include "board-stingray.h"
#include "tegra2_emc.h"
-static const struct tegra_emc_table stingray_emc_tables[] = {
+static long stingray_mem_vid;
+static long stingray_mem_pid;
+
+static const struct tegra_emc_table stingray_emc_tables_samsung[] = {
+ {
+ .rate = 60000, /* SDRAM frquency */
+ .regs = {
+ 0x00000004, /* RC */
+ 0x00000008, /* RFC */
+ 0x00000003, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x000000a8, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x00000008, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x000000e1, /* TREFBW */
+ 0x00000004, /* QUSE_EXTRA */
+ 0x00000000, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa09404ae, /* CFG_DIG_DLL */
+ 0x007fa010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000005, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 120000, /* SDRAM frquency */
+ .regs = {
+ 0x00000007, /* RC */
+ 0x0000000f, /* RFC */
+ 0x00000005, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x0000017f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x00000010, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x000001c2, /* TREFBW */
+ 0x00000004, /* QUSE_EXTRA */
+ 0x00000001, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa09404ae, /* CFG_DIG_DLL */
+ 0x007fd010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x0000000a, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
{
- .rate = 150000, /* SDRAM frquency */
+ .rate = 200000, /* SDRAM frquency */
.regs = {
0x00000009, /* RC */
0x00000014, /* RFC */
0x00000000, /* CFG_CLKTRIM_0 */
0x00000000, /* CFG_CLKTRIM_1 */
0x00000000, /* CFG_CLKTRIM_2 */
- }
+ }
},
{
.rate = 300000, /* SDRAM frquency */
0x00000000, /* CFG_CLKTRIM_1 */
0x00000000, /* CFG_CLKTRIM_2 */
}
+ }
+};
+
+static const struct tegra_emc_table stingray_emc_tables_elpida[] = {
+ {
+ .rate = 60000, /* SDRAM frquency */
+ .regs = {
+ 0x00000004, /* RC */
+ 0x00000008, /* RFC */
+ 0x00000003, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x000000a8, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x00000008, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x000000e1, /* TREFBW */
+ 0x00000004, /* QUSE_EXTRA */
+ 0x00000000, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa06804ae, /* CFG_DIG_DLL */
+ 0x00004810, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000005, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 120000, /* SDRAM frquency */
+ .regs = {
+ 0x00000007, /* RC */
+ 0x0000000f, /* RFC */
+ 0x00000005, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x0000017f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x00000010, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x000001c2, /* TREFBW */
+ 0x00000004, /* QUSE_EXTRA */
+ 0x00000001, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa06804ae, /* CFG_DIG_DLL */
+ 0x007fd010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x0000000a, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 200000, /* SDRAM frquency */
+ .regs = {
+ 0x00000009, /* RC */
+ 0x00000014, /* RFC */
+ 0x00000007, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x0000021f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x00000015, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000270, /* TREFBW */
+ 0x00000004, /* QUSE_EXTRA */
+ 0x00000001, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa04c04ae, /* CFG_DIG_DLL */
+ 0x007fe010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x0000000e, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
},
+ {
+ .rate = 300000, /* SDRAM frquency */
+ .regs = {
+ 0x00000012, /* RC */
+ 0x00000027, /* RFC */
+ 0x0000000d, /* RAS */
+ 0x00000006, /* RP */
+ 0x00000007, /* R2W */
+ 0x00000005, /* W2R */
+ 0x00000003, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000006, /* RD_RCD */
+ 0x00000006, /* WR_RCD */
+ 0x00000003, /* RRD */
+ 0x00000003, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000006, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000009, /* QSAFE */
+ 0x0000000c, /* RDV */
+ 0x0000045f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000004, /* PDEX2WR */
+ 0x00000004, /* PDEX2RD */
+ 0x00000006, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000e, /* RW2PDEN */
+ 0x0000002a, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x0000000f, /* TFAW */
+ 0x00000007, /* TRPAB */
+ 0x00000005, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x000004e0, /* TREFBW */
+ 0x00000005, /* QUSE_EXTRA */
+ 0x00000002, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000282, /* FBIO_CFG5 */
+ 0xe03c048b, /* CFG_DIG_DLL */
+ 0x007fb010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x0000001b, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ }
};
+static int __init stingray_param_mem_vid(char *options)
+{
+ return strict_strtol(options, 0, &stingray_mem_vid);
+}
+__setup("mem_vid=", stingray_param_mem_vid);
+
+static int __init stingray_param_mem_pid(char *options)
+{
+ return strict_strtol(options, 0, &stingray_mem_pid);
+}
+__setup("mem_pid=", stingray_param_mem_pid);
+
void stingray_init_emc(void)
{
- tegra_init_emc(stingray_emc_tables, ARRAY_SIZE(stingray_emc_tables));
+ if (stingray_mem_vid == 0x101 && stingray_mem_pid == 0x5454) {
+ pr_info("%s: Samsung memory found\n", __func__);
+ tegra_init_emc(stingray_emc_tables_samsung,
+ ARRAY_SIZE(stingray_emc_tables_samsung));
+ } else if (stingray_mem_vid == 0x303 && stingray_mem_pid == 0x5454) {
+ pr_info("%s: Elpida memory found\n", __func__);
+ tegra_init_emc(stingray_emc_tables_elpida,
+ ARRAY_SIZE(stingray_emc_tables_elpida));
+ } else {
+ pr_info("%s: Memory not recognized, memory scaling disabled\n",
+ __func__);
+ }
}
projects / firefly-linux-kernel-4.4.55.git / commitdiff